* [PATCH 2/3] ddr: imx8m: clean up entry points
2020-11-05 14:10 [PATCH 1/3] ddr: imx8m: correct the pwrctl setting of selfref_en Lucas Stach
@ 2020-11-05 14:10 ` Lucas Stach
2020-11-05 14:10 ` [PATCH 3/3] ddr: imx8m: add workaround for DDRPHY rank to rank issue Lucas Stach
2020-11-09 7:45 ` [PATCH 1/3] ddr: imx8m: correct the pwrctl setting of selfref_en Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Lucas Stach @ 2020-11-05 14:10 UTC (permalink / raw)
To: barebox
The DDRC address in the memory map and the TF-A parameter store address
is the same for all i.MX8M* SoCs. The only difference (for now) is in the
power up sequence. Add a enum for the DDRC type, so we can take different
code paths in imx8m_ddr_init() depending on the SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm/boards/nxp-imx8mp-evk/lowlevel.c | 2 +-
drivers/ddr/imx8m/ddr_init.c | 82 ++++++++++-------------
include/soc/imx8m/ddr.h | 7 ++
3 files changed, 45 insertions(+), 46 deletions(-)
diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
index e4f994a1d1b8..3298ded5866d 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
@@ -118,7 +118,7 @@ static void start_atf(void)
power_init_board();
- imx8mm_ddr_init(&imx8mp_evk_dram_timing);
+ imx8mp_ddr_init(&imx8mp_evk_dram_timing);
imx8mp_get_boot_source(&src, &instance);
switch (src) {
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c
index bc64e7c17e1a..230fa7ef4266 100644
--- a/drivers/ddr/imx8m/ddr_init.c
+++ b/drivers/ddr/imx8m/ddr_init.c
@@ -13,8 +13,6 @@
#include <mach/imx8m-regs.h>
#include <mach/imx8m-ccm-regs.h>
-#define SRC_DDRC_RCR_ADDR MX8MQ_SRC_DDRC_RCR_ADDR
-
static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
{
int i = 0;
@@ -25,14 +23,37 @@ static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
}
}
-static int imx8m_ddr_init(unsigned long src_ddrc_rcr,
- struct dram_timing_info *dram_timing)
+/*
+ * We store the timing parameters here. the TF-A will pick these up.
+ * Note that the timing used we leave the driver with is a PLL bypass 25MHz
+ * mode. So if your board runs horribly slow you'll likely have to provide a
+ * TF-A binary.
+ */
+#define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000
+
+static int imx8m_ddr_init(struct dram_timing_info *dram_timing,
+ enum ddrc_type type)
{
+ unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR;
unsigned int tmp, initial_drate, target_freq;
int ret;
pr_debug("start DRAM init\n");
+ /* Step1: Follow the power up procedure */
+ switch (type) {
+ case DDRC_TYPE_MQ:
+ reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f);
+ reg32_write(src_ddrc_rcr, 0x8f00000f);
+ reg32_write(src_ddrc_rcr + 0x04, 0x8f000000);
+ break;
+ case DDRC_TYPE_MM:
+ case DDRC_TYPE_MP:
+ reg32_write(src_ddrc_rcr, 0x8f00001f);
+ reg32_write(src_ddrc_rcr, 0x8f00000f);
+ break;
+ }
+
pr_debug("cfg clk\n");
/* disable iso */
@@ -44,7 +65,7 @@ static int imx8m_ddr_init(unsigned long src_ddrc_rcr,
ddrphy_init_set_dfi_clk(initial_drate);
/* D-aasert the presetn */
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+ reg32_write(src_ddrc_rcr, 0x8F000006);
/* Step2: Program the dwc_ddr_umctl2 registers */
pr_debug("ddrc config start\n");
@@ -52,8 +73,8 @@ static int imx8m_ddr_init(unsigned long src_ddrc_rcr,
pr_debug("ddrc config done\n");
/* Step3: De-assert reset signal(core_ddrc_rstn & aresetn_n) */
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
- reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+ reg32_write(src_ddrc_rcr, 0x8F000004);
+ reg32_write(src_ddrc_rcr, 0x8F000000);
/*
* Step4: Disable auto-refreshes, self-refresh, powerdown, and
@@ -162,52 +183,23 @@ static int imx8m_ddr_init(unsigned long src_ddrc_rcr,
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
pr_debug(" ddrmix config done\n");
+ /* save the dram timing config into memory */
+ dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE);
+
return 0;
}
-/*
- * We store the timing parameters here. the TF-A will pick these up.
- * Note that the timing used we leave the driver with is a PLL bypass 25MHz
- * mode. So if your board runs horribly slow you'll likely have to provide a
- * TF-A binary.
- */
-#define IMX8M_SAVED_DRAM_TIMING_BASE 0x180000
-
int imx8mm_ddr_init(struct dram_timing_info *dram_timing)
{
- unsigned long src_ddrc_rcr = MX8M_SRC_DDRC_RCR_ADDR;
- int ret;
-
- /* Step1: Follow the power up procedure */
- reg32_write(src_ddrc_rcr, 0x8f00001f);
- reg32_write(src_ddrc_rcr, 0x8f00000f);
-
- ret = imx8m_ddr_init(src_ddrc_rcr, dram_timing);
- if (ret)
- return ret;
-
- /* save the dram timing config into memory */
- dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE);
-
- return 0;
+ return imx8m_ddr_init(dram_timing, DDRC_TYPE_MM);
}
int imx8mq_ddr_init(struct dram_timing_info *dram_timing)
{
- unsigned long src_ddrc_rcr = MX8MQ_SRC_DDRC_RCR_ADDR;
- int ret;
-
- /* Step1: Follow the power up procedure */
- reg32_write(src_ddrc_rcr + 0x04, 0x8f00000f);
- reg32_write(src_ddrc_rcr, 0x8f00000f);
- reg32_write(src_ddrc_rcr + 0x04, 0x8f000000);
-
- ret = imx8m_ddr_init(src_ddrc_rcr, dram_timing);
- if (ret)
- return ret;
-
- /* save the dram timing config into memory */
- dram_config_save(dram_timing, IMX8M_SAVED_DRAM_TIMING_BASE);
+ return imx8m_ddr_init(dram_timing, DDRC_TYPE_MQ);
+}
- return 0;
+int imx8mp_ddr_init(struct dram_timing_info *dram_timing)
+{
+ return imx8m_ddr_init(dram_timing, DDRC_TYPE_MP);
}
diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h
index 5b2747ed1f7b..1408ffcfb557 100644
--- a/include/soc/imx8m/ddr.h
+++ b/include/soc/imx8m/ddr.h
@@ -363,8 +363,15 @@ struct dram_timing_info {
extern struct dram_timing_info dram_timing;
+enum ddrc_type {
+ DDRC_TYPE_MM,
+ DDRC_TYPE_MQ,
+ DDRC_TYPE_MP,
+};
+
int imx8mm_ddr_init(struct dram_timing_info *timing_info);
int imx8mq_ddr_init(struct dram_timing_info *timing_info);
+int imx8mp_ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
--
2.20.1
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^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH 3/3] ddr: imx8m: add workaround for DDRPHY rank to rank issue
2020-11-05 14:10 [PATCH 1/3] ddr: imx8m: correct the pwrctl setting of selfref_en Lucas Stach
2020-11-05 14:10 ` [PATCH 2/3] ddr: imx8m: clean up entry points Lucas Stach
@ 2020-11-05 14:10 ` Lucas Stach
2020-11-09 7:45 ` [PATCH 1/3] ddr: imx8m: correct the pwrctl setting of selfref_en Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Lucas Stach @ 2020-11-05 14:10 UTC (permalink / raw)
To: barebox
This is a port of upstream U-Boot commit b335966958a9. Sadly there is no
more information to be found about the issue. The currently available
errata documents don't mention this issue at all and the U-Boot commit
doesn't tell much either, however this commit has been pointed out by
NXP engineers as a solution to reports of board instabilities.
| drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
|
| Add logic to automatically update umctl2's setting based
| on phy training CDD value for rank to rank space issue
|
| Acked-by: Ye Li <ye.li@nxp.com>
| Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
| Signed-off-by: Jacky Bai <ping.bai@nxp.com>
| Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
This fixes a severe instability caused by memory corruptions in the
booted Linux system on the i.MX8MM EVK board I'm working with. This
commit has not been tested on i.MX8MP, yet.
---
drivers/ddr/imx8m/ddr_init.c | 3 +
drivers/ddr/imx8m/ddrphy_train.c | 5 +
drivers/ddr/imx8m/ddrphy_utils.c | 169 +++++++++++++++++++++++++++++++
include/soc/imx8m/ddr.h | 4 +
4 files changed, 181 insertions(+)
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c
index 230fa7ef4266..1cd7b7406dc7 100644
--- a/drivers/ddr/imx8m/ddr_init.c
+++ b/drivers/ddr/imx8m/ddr_init.c
@@ -134,6 +134,9 @@ static int imx8m_ddr_init(struct dram_timing_info *dram_timing,
/* Step15: Set SWCTL.sw_done to 0 */
reg32_write(DDRC_SWCTL(0), 0x00000000);
+ /* Apply rank-to-rank workaround */
+ update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1, type);
+
/* Step16: Set DFIMISC.dfi_init_start to 1 */
setbits_le32(DDRC_DFIMISC(0), (0x1 << 5));
diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c
index ca0bb2f57bb7..9280c853aa1c 100644
--- a/drivers/ddr/imx8m/ddrphy_train.c
+++ b/drivers/ddr/imx8m/ddrphy_train.c
@@ -93,7 +93,12 @@ int ddr_cfg_phy(struct dram_timing_info *dram_timing)
/* Read the Message Block results */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
+
ddrphy_init_read_msg_block(fsp_msg->fw_type);
+
+ if (fsp_msg->fw_type != FW_2D_IMAGE)
+ get_trained_CDD(i);
+
dwc_ddrphy_apb_wr(0xd0000, 0x1);
fsp_msg++;
diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c
index 222b61be3d55..c48372491015 100644
--- a/drivers/ddr/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx8m/ddrphy_utils.c
@@ -306,3 +306,172 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
void ddrphy_init_read_msg_block(enum fw_type type)
{
}
+
+static unsigned int g_cdd_rr_max[4];
+static unsigned int g_cdd_rw_max[4];
+static unsigned int g_cdd_wr_max[4];
+static unsigned int g_cdd_ww_max[4];
+
+static unsigned int look_for_max(unsigned int data[], unsigned int addr_start,
+ unsigned int addr_end)
+{
+ unsigned int i, imax = 0;
+
+ for (i = addr_start; i <= addr_end; i++) {
+ if (((data[i] >> 7) == 0) && (data[i] > imax))
+ imax = data[i];
+ }
+
+ return imax;
+}
+
+void get_trained_CDD(u32 fsp)
+{
+ unsigned int i, ddr_type, tmp;
+ unsigned int cdd_cha[12], cdd_chb[12];
+ unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
+ unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
+
+ ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
+ if (ddr_type == 0x20) {
+ for (i = 0; i < 6; i++) {
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
+ (0x54013UL + i) * 4);
+ cdd_cha[i * 2] = tmp & 0xff;
+ cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
+ }
+
+ for (i = 0; i < 7; i++) {
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
+ (0x5402cUL + i) * 4);
+ if (i == 0) {
+ cdd_cha[0] = (tmp >> 8) & 0xff;
+ } else if (i == 6) {
+ cdd_cha[11] = tmp & 0xff;
+ } else {
+ cdd_chb[ i * 2 - 1] = tmp & 0xff;
+ cdd_chb[i * 2] = (tmp >> 8) & 0xff;
+ }
+ }
+
+ cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
+ cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
+ cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
+ cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
+ cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
+ cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
+ cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
+ cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
+ g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
+ g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
+ g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
+ g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
+ } else {
+ unsigned int ddr4_cdd[64];
+
+ for( i = 0; i < 29; i++) {
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
+ (0x54012UL + i) * 4);
+ ddr4_cdd[i * 2] = tmp & 0xff;
+ ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
+ }
+
+ g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
+ g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
+ g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
+ g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
+ }
+}
+
+void update_umctl2_rank_space_setting(unsigned int pstat_num,
+ enum ddrc_type type)
+{
+ unsigned int i,ddr_type;
+ unsigned int rdata, tmp, tmp_t;
+ unsigned int ddrc_w2r,ddrc_r2w,ddrc_wr_gap,ddrc_rd_gap;
+ unsigned long addr_slot;
+
+ ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
+ for (i = 0; i < pstat_num; i++) {
+ addr_slot = i ? (i + 1) * 0x1000 : 0;
+ if (ddr_type == 0x20) {
+ /* update r2w:[13:8], w2r:[5:0] */
+ rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
+ ddrc_w2r = rdata & 0x3f;
+ if (type == DDRC_TYPE_MP)
+ tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
+ else
+ tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
+ ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
+
+ ddrc_r2w = (rdata >> 8) & 0x3f;
+ if (type == DDRC_TYPE_MP)
+ tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
+ else
+ tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
+ ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
+
+ tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
+ reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
+ } else {
+ /* update w2r:[5:0] */
+ rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
+ ddrc_w2r = rdata & 0x3f;
+ if (type == DDRC_TYPE_MP)
+ tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
+ else
+ tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
+ ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
+ tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
+ reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
+
+ /* update r2w:[13:8] */
+ rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
+ ddrc_r2w = (rdata >> 8) & 0x3f;
+ if (type == DDRC_TYPE_MP)
+ tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
+ else
+ tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
+ ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
+
+ tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
+ reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
+ }
+
+ if (type != DDRC_TYPE_MQ) {
+ /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
+ rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
+ ddrc_wr_gap = (rdata >> 8) & 0xf;
+ if (type == DDRC_TYPE_MP)
+ tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
+ else
+ tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
+ ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
+
+ ddrc_rd_gap = (rdata >> 4) & 0xf;
+ if (type == DDRC_TYPE_MP)
+ tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
+ else
+ tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
+ ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
+
+ tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
+ reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
+ }
+ }
+
+ if (type == DDRC_TYPE_MQ) {
+ /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
+ rdata = reg32_read(DDRC_RANKCTL(0));
+ ddrc_wr_gap = (rdata >> 8) & 0xf;
+ tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
+ ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
+
+ ddrc_rd_gap = (rdata >> 4) & 0xf;
+ tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
+ ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
+
+ tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
+ reg32_write(DDRC_RANKCTL(0), tmp_t);
+ }
+}
diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h
index 1408ffcfb557..a5a610909212 100644
--- a/include/soc/imx8m/ddr.h
+++ b/include/soc/imx8m/ddr.h
@@ -382,6 +382,10 @@ int wait_ddrphy_training_complete(void);
void ddrphy_init_set_dfi_clk(unsigned int drate);
void ddrphy_init_read_msg_block(enum fw_type type);
+void update_umctl2_rank_space_setting(unsigned int pstat_num,
+ enum ddrc_type type);
+void get_trained_CDD(unsigned int fsp);
+
#define reg32_write(a, v) writel(v, a)
#define reg32_read(a) readl(a)
--
2.20.1
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH 1/3] ddr: imx8m: correct the pwrctl setting of selfref_en
2020-11-05 14:10 [PATCH 1/3] ddr: imx8m: correct the pwrctl setting of selfref_en Lucas Stach
2020-11-05 14:10 ` [PATCH 2/3] ddr: imx8m: clean up entry points Lucas Stach
2020-11-05 14:10 ` [PATCH 3/3] ddr: imx8m: add workaround for DDRPHY rank to rank issue Lucas Stach
@ 2020-11-09 7:45 ` Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Sascha Hauer @ 2020-11-09 7:45 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On Thu, Nov 05, 2020 at 03:10:13PM +0100, Lucas Stach wrote:
> Port of upstream U-Boot commit: 1eb325af16e2
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/ddr/imx8m/ddr_init.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks
Sascha
>
> diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c
> index d4efee613343..bc64e7c17e1a 100644
> --- a/drivers/ddr/imx8m/ddr_init.c
> +++ b/drivers/ddr/imx8m/ddr_init.c
> @@ -156,7 +156,7 @@ static int imx8m_ddr_init(unsigned long src_ddrc_rcr,
> /* Step26: Set back register in Step4 to the original values if desired */
> reg32_write(DDRC_RFSHCTL3(0), 0x0000000);
> /* enable selfref_en by default */
> - setbits_le32(DDRC_PWRCTL(0), 0x1 << 3);
> + setbits_le32(DDRC_PWRCTL(0), 0x1);
>
> /* enable port 0 */
> reg32_write(DDRC_PCTRL_0(0), 0x00000001);
> --
> 2.20.1
>
>
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