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From: Stafford Horne <shorne@gmail.com>
To: Barebox <barebox@lists.infradead.org>
Cc: Openrisc <openrisc@lists.librecores.org>,
	Ahmad Fatoum <a.fatoum@pengutronix.de>,
	Stafford Horne <shorne@gmail.com>
Subject: [PATCH 1/4] openrisc: Use movhi to zero registers
Date: Wed,  3 Mar 2021 22:50:23 +0900	[thread overview]
Message-ID: <20210303135026.3450789-2-shorne@gmail.com> (raw)
In-Reply-To: <20210303135026.3450789-1-shorne@gmail.com>

This is needed when running on FPGA as registers are not guaranteed
to be initialized to 0.  Using movhi allows to explicitly set 0.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/cpu/start.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/openrisc/cpu/start.S b/arch/openrisc/cpu/start.S
index 7ac790b05..c448d3775 100644
--- a/arch/openrisc/cpu/start.S
+++ b/arch/openrisc/cpu/start.S
@@ -37,10 +37,10 @@
 	.org	0x100
 __reset:
 	/* there is no guarantee r0 is hardwired to zero, clear it here */
-	l.andi	r0, r0, 0
+	l.movhi	r0, 0x0
 	/* reset stack and frame pointers */
-	l.andi	r1, r0, 0
-	l.andi	r2, r0, 0
+	l.movhi	r1, 0x0
+	l.movhi	r2, 0x0
 
 	/* set supervisor mode */
 	l.ori	r3,r0,SPR_SR_SM
-- 
2.26.2


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  reply	other threads:[~2021-03-03 14:03 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-03 13:50 [PATCH 0/4] OpenRISC fixes and setjmp/longjmp work Stafford Horne
2021-03-03 13:50 ` Stafford Horne [this message]
2021-03-03 13:50 ` [PATCH 2/4] openrisc: Add gitignore for dtb files Stafford Horne
2021-03-03 13:50 ` [PATCH 3/4] openrisc: Add linkage.h Stafford Horne
2021-03-03 13:50 ` [PATCH 4/4] openrisc: Implement setjmp/longjmp/initjmp Stafford Horne
2021-03-03 14:03 ` [PATCH 0/4] OpenRISC fixes and setjmp/longjmp work Ahmad Fatoum
2021-03-03 14:12   ` Stafford Horne
2021-03-03 20:25     ` Stafford Horne

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