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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Peter Mamonov <pmamonov@gmail.com>,
	Peter Korsgaard <peter@korsgaard.com>,
	Sascha Hauer <sha@pengutronix.de>,
	Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH v3 05/16] riscv: Add asm/asm.h
Date: Wed, 10 Mar 2021 09:47:49 +0100	[thread overview]
Message-ID: <20210310084800.3584-6-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20210310084800.3584-1-a.fatoum@pengutronix.de>

From: Sascha Hauer <s.hauer@pengutronix.de>

Various definitions for assembly code, taken as-is from Linux.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/riscv/include/asm/asm.h | 69 ++++++++++++++++++++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 arch/riscv/include/asm/asm.h

diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
new file mode 100644
index 000000000000..9c992a88d858
--- /dev/null
+++ b/arch/riscv/include/asm/asm.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_ASM_H
+#define _ASM_RISCV_ASM_H
+
+#ifdef __ASSEMBLY__
+#define __ASM_STR(x)	x
+#else
+#define __ASM_STR(x)	#x
+#endif
+
+#if __riscv_xlen == 64
+#define __REG_SEL(a, b)	__ASM_STR(a)
+#elif __riscv_xlen == 32
+#define __REG_SEL(a, b)	__ASM_STR(b)
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+#define REG_L		__REG_SEL(ld, lw)
+#define REG_S		__REG_SEL(sd, sw)
+#define REG_SC		__REG_SEL(sc.d, sc.w)
+#define SZREG		__REG_SEL(8, 4)
+#define LGREG		__REG_SEL(3, 2)
+
+#if __SIZEOF_POINTER__ == 8
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.dword
+#define RISCV_SZPTR		8
+#define RISCV_LGPTR		3
+#else
+#define RISCV_PTR		".dword"
+#define RISCV_SZPTR		"8"
+#define RISCV_LGPTR		"3"
+#endif
+#elif __SIZEOF_POINTER__ == 4
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.word
+#define RISCV_SZPTR		4
+#define RISCV_LGPTR		2
+#else
+#define RISCV_PTR		".word"
+#define RISCV_SZPTR		"4"
+#define RISCV_LGPTR		"2"
+#endif
+#else
+#error "Unexpected __SIZEOF_POINTER__"
+#endif
+
+#if (__SIZEOF_INT__ == 4)
+#define RISCV_INT		__ASM_STR(.word)
+#define RISCV_SZINT		__ASM_STR(4)
+#define RISCV_LGINT		__ASM_STR(2)
+#else
+#error "Unexpected __SIZEOF_INT__"
+#endif
+
+#if (__SIZEOF_SHORT__ == 2)
+#define RISCV_SHORT		__ASM_STR(.half)
+#define RISCV_SZSHORT		__ASM_STR(2)
+#define RISCV_LGSHORT		__ASM_STR(1)
+#else
+#error "Unexpected __SIZEOF_SHORT__"
+#endif
+
+#endif /* _ASM_RISCV_ASM_H */
-- 
2.29.2


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  parent reply	other threads:[~2021-03-10  8:50 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-10  8:47 [PATCH v3 00/16] common: introduce bthreads, co-operative Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 01/16] common: introduce HAS_ARCH_SJLJ Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 02/16] ARM: asm: setjmp: annotate setjmp/longjmp for GCC Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 03/16] ARM: asm: setjmp: implement coroutine dependency initjmp() Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 04/16] sandbox: asm: implement setjmp/longjmp/initjmp Ahmad Fatoum
2021-03-10  8:47 ` Ahmad Fatoum [this message]
2021-03-10  8:47 ` [PATCH v3 06/16] riscv: Add asm/linkage.h Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 07/16] riscv: Implement setjmp/longjmp/initjmp for RV32I Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 08/16] mips: Add linkage.h Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 09/16] mips: Implement setjmp/longjmp/initjmp for 32BIT Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 10/16] powerpc: Implement initjmp/setjmp/longjmp Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 11/16] x86: implement setjmp/longjmp/initjmp Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 12/16] common: poller: replace explicit calls to poller_call() with resched() Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 13/16] console: unconditionally run resched() in ctrlc() Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 14/16] common: introduce bthreads, co-operative barebox threads Ahmad Fatoum
2021-03-10  8:47 ` [PATCH v3 15/16] commands: add new bthread test command Ahmad Fatoum
2021-03-10  8:48 ` [PATCH v3 16/16] RFC: led: migrate from poller to bthread Ahmad Fatoum
2021-03-15  8:34 ` [PATCH v3 00/16] common: introduce bthreads, co-operative Sascha Hauer

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