* [PATCH 01/20] partitions: don't allocate dma capable memory
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 02/20] images: make BOARD_ARM_GENERIC_DT available for other arches Ahmad Fatoum
` (19 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
While block drivers may do DMA, they always use block caching chunks as
bounce buffer. No dma is every done directly to the block_read data
argument, so it doesn't need to be allocated with dma_alloc. The buffer
also need not be zeroed, as block_read will either overwrite it
completely or fail.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
common/partitions.c | 5 ++---
common/partitions/dos.c | 7 +++----
common/partitions/efi.c | 1 -
3 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/common/partitions.c b/common/partitions.c
index 1f0c544c6067..deb931f3290f 100644
--- a/common/partitions.c
+++ b/common/partitions.c
@@ -17,7 +17,6 @@
#include <asm/unaligned.h>
#include <disks.h>
#include <filetype.h>
-#include <dma.h>
#include <linux/err.h>
#include "partitions/parser.h"
@@ -120,7 +119,7 @@ int parse_partition_table(struct block_device *blk)
uint8_t *buf;
pdesc = xzalloc(sizeof(*pdesc));
- buf = dma_alloc(SECTOR_SIZE * 2);
+ buf = malloc(2 * SECTOR_SIZE);
rc = block_read(blk, buf, 0, 2);
if (rc != 0) {
@@ -149,7 +148,7 @@ int parse_partition_table(struct block_device *blk)
}
on_error:
- dma_free(buf);
+ free(buf);
free(pdesc);
return rc;
}
diff --git a/common/partitions/dos.c b/common/partitions/dos.c
index 488c2936f715..0012c4875658 100644
--- a/common/partitions/dos.c
+++ b/common/partitions/dos.c
@@ -16,7 +16,6 @@
#include <disks.h>
#include <init.h>
#include <asm/unaligned.h>
-#include <dma.h>
#include <linux/err.h>
#include "parser.h"
@@ -64,7 +63,7 @@ static uint64_t disk_guess_size(struct device_d *dev,
static void *read_mbr(struct block_device *blk)
{
- void *buf = dma_alloc(SECTOR_SIZE);
+ void *buf = malloc(SECTOR_SIZE);
int ret;
ret = block_read(blk, buf, 0, 1);
@@ -135,7 +134,7 @@ static int dos_get_disk_signature(struct param_d *p, void *_priv)
static void dos_extended_partition(struct block_device *blk, struct partition_desc *pd,
struct partition *partition, uint32_t signature)
{
- uint8_t *buf = dma_alloc(SECTOR_SIZE);
+ uint8_t *buf = malloc(SECTOR_SIZE);
uint32_t ebr_sector = partition->first_sec;
struct partition_entry *table = (struct partition_entry *)&buf[0x1be];
unsigned partno = 5;
@@ -185,7 +184,7 @@ static void dos_extended_partition(struct block_device *blk, struct partition_de
}
out:
- dma_free(buf);
+ free(buf);
return;
}
diff --git a/common/partitions/efi.c b/common/partitions/efi.c
index f20fd0d9b9e8..437c3d64f889 100644
--- a/common/partitions/efi.c
+++ b/common/partitions/efi.c
@@ -16,7 +16,6 @@
#include <disks.h>
#include <init.h>
#include <asm/unaligned.h>
-#include <dma.h>
#include <crc.h>
#include <linux/ctype.h>
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 02/20] images: make BOARD_ARM_GENERIC_DT available for other arches
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 01/20] partitions: don't allocate dma capable memory Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 03/20] ARM: rename CONFIG_ARM_USE_COMPRESSED_DTB to CONFIG_USE_COMPRESSED_DTB Ahmad Fatoum
` (18 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
Other architectures would benefit from the generic DT image too.
Add a new arch-agnostic symbol that arches besides ARM can select.
The new symbol itself should not have a prompt as the help text for
each architecture likely differs (e.g. device tree handoff register).
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/Kconfig | 2 +-
images/Makefile | 4 ++--
pbl/Kconfig | 4 ++++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a1f781b60f95..3b983c8b3d0a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -323,7 +323,7 @@ config BOARD_ARM_VIRT
select OF_OVERLAY
config BOARD_ARM_GENERIC_DT
- select LIBFDT
+ select BOARD_GENERIC_DT
select ARM_AMBA
depends on HAVE_PBL_MULTI_IMAGES
depends on OFDEVICE
diff --git a/images/Makefile b/images/Makefile
index b8899dcd2a81..84492a154d16 100644
--- a/images/Makefile
+++ b/images/Makefile
@@ -166,9 +166,9 @@ include $(srctree)/images/Makefile.zynqmp
include $(srctree)/images/Makefile.layerscape
-pblb-$(CONFIG_BOARD_ARM_GENERIC_DT) += start_dt_2nd
+pblb-$(CONFIG_BOARD_GENERIC_DT) += start_dt_2nd
FILE_barebox-dt-2nd.img = start_dt_2nd.pblb
-image-$(CONFIG_BOARD_ARM_GENERIC_DT) += barebox-dt-2nd.img
+image-$(CONFIG_BOARD_GENERIC_DT) += barebox-dt-2nd.img
ifdef CONFIG_ARM
pblb-$(CONFIG_PBL_SINGLE_IMAGE) += start_pbl
diff --git a/pbl/Kconfig b/pbl/Kconfig
index 6e8cc3ac04ae..2eea5aef7a30 100644
--- a/pbl/Kconfig
+++ b/pbl/Kconfig
@@ -40,6 +40,10 @@ config PBL_VERIFY_PIGGY
depends on ARM
bool
+config BOARD_GENERIC_DT
+ bool
+ select LIBFDT
+
config IMAGE_COMPRESSION
bool
depends on HAVE_IMAGE_COMPRESSION
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 03/20] ARM: rename CONFIG_ARM_USE_COMPRESSED_DTB to CONFIG_USE_COMPRESSED_DTB
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 01/20] partitions: don't allocate dma capable memory Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 02/20] images: make BOARD_ARM_GENERIC_DT available for other arches Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 04/20] ARM: aarch64: ommit unused label in assembly Ahmad Fatoum
` (17 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
Other PBL-enabled architecture can benefit from compressed dtbs as well.
As the symbol doesn't have a prompt, it's safe to rename all of
instances of it to drop the ARM qualifier.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/Kconfig | 7 +------
arch/arm/cpu/start.c | 2 +-
arch/arm/mach-at91/Kconfig | 2 +-
arch/arm/mach-imx/Kconfig | 26 +++++++++++++-------------
arch/arm/mach-omap/Kconfig | 2 +-
common/Kconfig | 6 ++++++
6 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3b983c8b3d0a..0e444d17d5af 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -17,11 +17,6 @@ config ARM_LINUX
config HAVE_MACH_ARM_HEAD
bool
-config ARM_USE_COMPRESSED_DTB
- bool
- select UNCOMPRESS
- select LZO_DECOMPRESS
-
config TEXT_BASE
hex
default 0x0
@@ -208,7 +203,7 @@ config ARCH_STM32MP
select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_SMCCC
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config ARCH_VERSATILE
bool "ARM Versatile boards (ARM926EJ-S)"
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index f48f5beea807..5533466e01a7 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -75,7 +75,7 @@ void *barebox_arm_boot_dtb(void)
return barebox_boarddata;
}
- if (!IS_ENABLED(CONFIG_ARM_USE_COMPRESSED_DTB) || !barebox_boarddata
+ if (!IS_ENABLED(CONFIG_USE_COMPRESSED_DTBS) || !barebox_boarddata
|| !blob_is_compressed_fdt(barebox_boarddata))
return NULL;
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 52eefc736138..2d13b71ce3a1 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -573,7 +573,7 @@ endif
config AT91_MULTI_BOARDS
bool "Allow multiple boards to be selected"
select HAVE_PBL_MULTI_IMAGES
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
if AT91_MULTI_BOARDS
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3f8012c73211..55931058f6d7 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -345,7 +345,7 @@ config MACH_PROTONIC_IMX6
bool "Protonic-Holland i.MX6 based boards"
select ARCH_IMX6
select ARCH_IMX6UL
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_KONTRON_SAMX6I
bool "Kontron sAMX6i"
@@ -409,18 +409,18 @@ config MACH_TECHNEXION_PICO_HOBBIT
bool "Technexion Pico Hobbit"
select ARCH_IMX6
select ARCH_IMX6UL
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_TECHNEXION_WANDBOARD
bool "Technexion Wandboard"
select ARCH_IMX6
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
select MCI_IMX_ESDHC_PBL
config MACH_EMBEST_MARSBOARD
bool "Embest MarSboard"
select ARCH_IMX6
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_EMBEST_RIOTBOARD
bool "Embest RIoTboard"
@@ -454,7 +454,7 @@ config MACH_CM_FX6
config MACH_ADVANTECH_ROM_742X
bool "Advantech ROM 742X"
select ARCH_IMX6
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_WARP7
bool "NXP i.MX7: element 14 WaRP7 Board"
@@ -464,7 +464,7 @@ config MACH_AC_SXB
bool "Atlas Copco: SXB board"
select ARCH_IMX7
select MCI_IMX_ESDHC_PBL
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_VF610_TWR
bool "Freescale VF610 Tower Board"
@@ -479,14 +479,14 @@ config MACH_ZII_RDU1
select MACH_FREESCALE_MX51_PDK_POWER
select CRC8
select MACH_ZII_COMMON
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_ZII_RDU2
bool "ZII i.MX6Q(+) RDU2"
select ARCH_IMX6
select MCI_IMX_ESDHC_PBL
select MACH_ZII_COMMON
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_ZII_IMX8MQ_DEV
bool "ZII i.MX8MQ based devices"
@@ -496,19 +496,19 @@ config MACH_ZII_IMX8MQ_DEV
select ARM_SMCCC
select MCI_IMX_ESDHC_PBL
select MACH_ZII_COMMON
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_ZII_VF610_DEV
bool "ZII VF610 Dev Family"
select ARCH_VF610
select CLKDEV_LOOKUP
select MACH_ZII_COMMON
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_ZII_IMX7D_DEV
bool "ZII i.MX7D based devices"
select ARCH_IMX7
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_PHYTEC_PHYCORE_IMX7
bool "Phytec phyCORE i.MX7"
@@ -576,12 +576,12 @@ config MACH_DIGI_CCIMX6ULSBCPRO
bool "Digi Internal CC-IMX6UL SBC Pro"
select ARCH_IMX6
select ARCH_IMX6UL
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_WEBASTO_CCBV2
bool "Webasto Common Communication Board V2"
select ARCH_IMX6UL
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
config MACH_MNT_REFORM
bool "MNT Reform"
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 220b6351679c..3347d277bbb0 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -41,7 +41,7 @@ config ARCH_AM33XX
select GENERIC_GPIO
select OFTREE
select CLOCKSOURCE_TI_DM
- select ARM_USE_COMPRESSED_DTB
+ select USE_COMPRESSED_DTB
help
Say Y here if you are using Texas Instrument's AM33xx based platform
diff --git a/common/Kconfig b/common/Kconfig
index b1f4543e03cd..36207274f07f 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -42,6 +42,12 @@ config BLOCK
config BLOCK_WRITE
bool
+config USE_COMPRESSED_DTB
+ bool
+ depends on ARM
+ select UNCOMPRESS
+ select LZO_DECOMPRESS
+
config ELF
bool "ELF Support" if COMPILE_TEST
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 04/20] ARM: aarch64: ommit unused label in assembly
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (2 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 03/20] ARM: rename CONFIG_ARM_USE_COMPRESSED_DTB to CONFIG_USE_COMPRESSED_DTB Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 05/20] serial: virtio-console: depend on, but don't select VIRTIO Ahmad Fatoum
` (16 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
The 1: is a left-over from before 5f04e5e03e94 ("ARM: aarch64: Fix
get_runtime_offset after relocation"). It's unused now, so drop it.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/lib64/runtime-offset.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib64/runtime-offset.S b/arch/arm/lib64/runtime-offset.S
index 5e5ab9a8d136..e2ff5d21036d 100644
--- a/arch/arm/lib64/runtime-offset.S
+++ b/arch/arm/lib64/runtime-offset.S
@@ -8,7 +8,7 @@
* we are currently running at.
*/
ENTRY(get_runtime_offset)
-1: adr x0, _text
+ adr x0, _text
ldr x1, linkadr
subs x0, x0, x1
ret
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 05/20] serial: virtio-console: depend on, but don't select VIRTIO
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (3 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 04/20] ARM: aarch64: ommit unused label in assembly Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 06/20] filetype: detect RISC-V Linux kernel image Ahmad Fatoum
` (15 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
VIRTIO has multiple backends, each with is its own dependencies.
It's thus wrong to select it from drivers. Fix this.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/serial/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 09434c1ba86c..db924efa02a6 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -158,7 +158,7 @@ config DRIVER_SERIAL_LPUART
config VIRTIO_CONSOLE
tristate "Virtio console"
- select VIRTIO
+ depends on VIRTIO
help
Virtio console for use with hypervisors.
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 06/20] filetype: detect RISC-V Linux kernel image
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (4 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 05/20] serial: virtio-console: depend on, but don't select VIRTIO Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 07/20] asm: unaligned: don't do unaligned accesses Ahmad Fatoum
` (14 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
We still have no boot support for RISC-V, take the first step by
enabling barebox to detect a RISC-V Linux kernel image. The header
format is aligned with that of arm64.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
common/filetype.c | 3 +++
include/filetype.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/common/filetype.c b/common/filetype.c
index 539c96b74527..d89a5bcffea5 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -61,6 +61,7 @@ static const struct filetype_str filetype_str[] = {
[filetype_kwbimage_v1] = { "MVEBU kwbimage (v1)", "kwb1" },
[filetype_android_sparse] = { "Android sparse image", "sparse" },
[filetype_arm64_linux_image] = { "ARM aarch64 Linux image", "aarch64-linux" },
+ [filetype_riscv_linux_image] = { "RISC-V Linux image", "riscv-linux" },
[filetype_elf] = { "ELF", "elf" },
[filetype_imx_image_v1] = { "i.MX image (v1)", "imx-image-v1" },
[filetype_imx_image_v2] = { "i.MX image (v2)", "imx-image-v2" },
@@ -303,6 +304,8 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
return filetype_bpk;
if (le32_to_cpu(buf[14]) == 0x644d5241)
return filetype_arm64_linux_image;
+ if (le32_to_cpu(buf[14]) == 0x05435352)
+ return filetype_riscv_linux_image;
if ((buf8[0] == 0x5a || buf8[0] == 0x69 || buf8[0] == 0x78 ||
buf8[0] == 0x8b || buf8[0] == 0x9c) &&
buf8[0x1] == 0 && buf8[0x2] == 0 && buf8[0x3] == 0 &&
diff --git a/include/filetype.h b/include/filetype.h
index 3019dda6ed78..cc97f0a6ba9f 100644
--- a/include/filetype.h
+++ b/include/filetype.h
@@ -43,6 +43,7 @@ enum filetype {
filetype_kwbimage_v1,
filetype_android_sparse,
filetype_arm64_linux_image,
+ filetype_riscv_linux_image,
filetype_elf,
filetype_imx_image_v1,
filetype_imx_image_v2,
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 07/20] asm: unaligned: don't do unaligned accesses
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (5 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 06/20] filetype: detect RISC-V Linux kernel image Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 08/20] RISC-V: debug_ll: ns16550: align C access size with assembly's Ahmad Fatoum
` (13 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
While HW can emulate unaligned accesses at a performance penalty,
it's probably best to just not generate them.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/include/asm/unaligned.h | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/include/asm/unaligned.h b/arch/riscv/include/asm/unaligned.h
index aaebc064114e..c37b71c21ee5 100644
--- a/arch/riscv/include/asm/unaligned.h
+++ b/arch/riscv/include/asm/unaligned.h
@@ -1,19 +1,11 @@
#ifndef _ASM_RISCV_UNALIGNED_H
#define _ASM_RISCV_UNALIGNED_H
-/*
- * FIXME: this file is copy-n-pasted from sandbox's unaligned.h
- */
-
-#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/generic.h>
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-#else
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-#endif
+#define get_unaligned __get_unaligned_le
+#define put_unaligned __put_unaligned_le
#endif /* _ASM_RISCV_UNALIGNED_H */
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 08/20] RISC-V: debug_ll: ns16550: align C access size with assembly's
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (6 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 07/20] asm: unaligned: don't do unaligned accesses Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 09/20] RISC-V: drop duplicate or unneeded cflags Ahmad Fatoum
` (12 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
The assembly putc routines do accesses the same size of the register
stride. Do likewise for the C implementation.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/include/asm/debug_ll_ns16550.h | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/debug_ll_ns16550.h b/arch/riscv/include/asm/debug_ll_ns16550.h
index f1c2ccbd0afb..7d6d12df74fe 100644
--- a/arch/riscv/include/asm/debug_ll_ns16550.h
+++ b/arch/riscv/include/asm/debug_ll_ns16550.h
@@ -51,9 +51,13 @@
#if defined(DEBUG_LL_UART_IOSIZE32)
#define UART_REG_L lw
#define UART_REG_S sw
+#define __uart_read readl
+#define __uart_write writel
#elif defined(DEBUG_LL_UART_IOSIZE8)
#define UART_REG_L lbu
#define UART_REG_S sb
+#define __uart_read readb
+#define __uart_write writeb
#else
#error "Please define DEBUG_LL_UART_IOSIZE{8,32}"
#endif
@@ -68,19 +72,19 @@
static inline void PUTC_LL(char ch)
{
#ifdef CONFIG_DEBUG_LL
- while (!(__raw_readl((u8 *)DEBUG_LL_UART_ADDR + UART_LSR) & UART_LSR_THRE))
+ while (!(__uart_read((u8 *)DEBUG_LL_UART_ADDR + UART_LSR) & UART_LSR_THRE))
;
- __raw_writel(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_THR);
+ __uart_write(ch, (u8 *)DEBUG_LL_UART_ADDR + UART_THR);
#endif /* CONFIG_DEBUG_LL */
}
static inline void debug_ll_ns16550_init(void)
{
#ifdef CONFIG_DEBUG_LL
- __raw_writel(UART_LCR_DLAB, (u8 *)DEBUG_LL_UART_ADDR + UART_LCR);
- __raw_writel(DEBUG_LL_UART_DIVISOR & 0xff, (u8 *)DEBUG_LL_UART_ADDR + UART_DLL);
- __raw_writel((DEBUG_LL_UART_DIVISOR >> 8) & 0xff, (u8 *)DEBUG_LL_UART_ADDR + UART_DLM);
- __raw_writel(UART_LCR_W, (u8 *)DEBUG_LL_UART_ADDR + UART_LCR);
+ __uart_write(UART_LCR_DLAB, (u8 *)DEBUG_LL_UART_ADDR + UART_LCR);
+ __uart_write(DEBUG_LL_UART_DIVISOR & 0xff, (u8 *)DEBUG_LL_UART_ADDR + UART_DLL);
+ __uart_write((DEBUG_LL_UART_DIVISOR >> 8) & 0xff, (u8 *)DEBUG_LL_UART_ADDR + UART_DLM);
+ __uart_write(UART_LCR_W, (u8 *)DEBUG_LL_UART_ADDR + UART_LCR);
#endif /* CONFIG_DEBUG_LL */
}
#else /* __ASSEMBLY__ */
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 09/20] RISC-V: drop duplicate or unneeded cflags
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (7 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 08/20] RISC-V: debug_ll: ns16550: align C access size with assembly's Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 10/20] RISC-V: add cacheless HAS_DMA support Ahmad Fatoum
` (11 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
-pipe -Wall is specified in top-level Makefile. Disabling warnings is
unneeded on the arch and is a left-over from MIPS port probably.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/Makefile | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 8cd5f51e3052..edf3a971e615 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -7,9 +7,7 @@ ifeq ($(CONFIG_ARCH_RV32I),y)
riscv-ldflags-y += -melf32lriscv
endif
-cflags-y += -fno-pic -pipe
-cflags-y += -Wall -Wstrict-prototypes \
- -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany
+cflags-y += -fno-pic -Wstrict-prototypes -mcmodel=medany
LDFLAGS_barebox += -nostdlib
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 10/20] RISC-V: add cacheless HAS_DMA support
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (8 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 09/20] RISC-V: drop duplicate or unneeded cflags Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 11/20] RISC-V: erizo: move to arch/riscv/boards/erizo Ahmad Fatoum
` (10 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
Define some stubs, so we can get virtio MMIO working on RISC-V
in QEMU. As we don't yet have MMU support, this is sufficient.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/dma.h | 44 ++++++++++++++++++++++++++++++++++++
include/dma.h | 1 +
3 files changed, 46 insertions(+)
create mode 100644 arch/riscv/include/asm/dma.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c8d63f99bb28..a7f362d8e80c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,6 +8,7 @@ config RISCV
select COMMON_CLK
select COMMON_CLK_OF_PROVIDER
select CLKDEV_LOOKUP
+ select HAS_DMA
config ARCH_TEXT_BASE
hex
diff --git a/arch/riscv/include/asm/dma.h b/arch/riscv/include/asm/dma.h
new file mode 100644
index 000000000000..4204653984a3
--- /dev/null
+++ b/arch/riscv/include/asm/dma.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_DMA_MAPPING_H
+#define _ASM_DMA_MAPPING_H
+
+#include <common.h>
+#include <xfuncs.h>
+#include <linux/build_bug.h>
+#include <malloc.h>
+
+#ifdef CONFIG_MMU
+#error DMA stubs need be replaced when using MMU and caches
+#endif
+
+static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
+{
+ void *ret;
+
+ ret = xmemalign(PAGE_SIZE, size);
+
+ memset(ret, 0, size);
+
+ if (dma_handle)
+ *dma_handle = (dma_addr_t)ret;
+
+ return ret;
+}
+
+static inline void dma_free_coherent(void *vaddr, dma_addr_t dma_handle,
+ size_t size)
+{
+ free(vaddr);
+}
+
+static inline void dma_sync_single_for_cpu(dma_addr_t address, size_t size,
+ enum dma_data_direction dir)
+{
+}
+
+static inline void dma_sync_single_for_device(dma_addr_t address, size_t size,
+ enum dma_data_direction dir)
+{
+}
+
+#endif /* _ASM_DMA_MAPPING_H */
diff --git a/include/dma.h b/include/dma.h
index 07b79cd91893..1b1cb3a40796 100644
--- a/include/dma.h
+++ b/include/dma.h
@@ -11,6 +11,7 @@
#include <dma-dir.h>
#include <asm/dma.h>
+#include <driver.h>
#define DMA_ADDRESS_BROKEN NULL
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 11/20] RISC-V: erizo: move to arch/riscv/boards/erizo
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (9 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 10/20] RISC-V: add cacheless HAS_DMA support Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 12/20] RISC-V: import Linux' optimized string functions Ahmad Fatoum
` (9 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
In preparation for migrating to PBL for RISC-V platforms, move the only
existing board support to a new arch/riscv/boards/ directory.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/Makefile | 2 +-
arch/riscv/boards/Makefile | 2 ++
arch/riscv/boards/erizo/Makefile | 5 +++++
arch/riscv/{boot/dtb.c => boards/erizo/board.c} | 0
arch/riscv/{boot/main_entry.c => boards/erizo/lowlevel.c} | 0
arch/riscv/{boot => boards/erizo}/start.S | 0
arch/riscv/boot/Makefile | 3 ---
7 files changed, 8 insertions(+), 4 deletions(-)
create mode 100644 arch/riscv/boards/Makefile
create mode 100644 arch/riscv/boards/erizo/Makefile
rename arch/riscv/{boot/dtb.c => boards/erizo/board.c} (100%)
rename arch/riscv/{boot/main_entry.c => boards/erizo/lowlevel.c} (100%)
rename arch/riscv/{boot => boards/erizo}/start.S (100%)
delete mode 100644 arch/riscv/boot/Makefile
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index edf3a971e615..d9cefe32c057 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -41,7 +41,7 @@ MACH :=
endif
common-y += $(MACH)
-common-y += arch/riscv/boot/
+common-y += arch/riscv/boards/
common-y += arch/riscv/lib/
common-$(CONFIG_OFTREE) += arch/riscv/dts/
diff --git a/arch/riscv/boards/Makefile b/arch/riscv/boards/Makefile
new file mode 100644
index 000000000000..2ce9af41e03b
--- /dev/null
+++ b/arch/riscv/boards/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo/
diff --git a/arch/riscv/boards/erizo/Makefile b/arch/riscv/boards/erizo/Makefile
new file mode 100644
index 000000000000..72b9a13ba73f
--- /dev/null
+++ b/arch/riscv/boards/erizo/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += lowlevel.o
+obj-y += start.o
+obj-y += board.o
diff --git a/arch/riscv/boot/dtb.c b/arch/riscv/boards/erizo/board.c
similarity index 100%
rename from arch/riscv/boot/dtb.c
rename to arch/riscv/boards/erizo/board.c
diff --git a/arch/riscv/boot/main_entry.c b/arch/riscv/boards/erizo/lowlevel.c
similarity index 100%
rename from arch/riscv/boot/main_entry.c
rename to arch/riscv/boards/erizo/lowlevel.c
diff --git a/arch/riscv/boot/start.S b/arch/riscv/boards/erizo/start.S
similarity index 100%
rename from arch/riscv/boot/start.S
rename to arch/riscv/boards/erizo/start.S
diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
deleted file mode 100644
index fd62cab8c127..000000000000
--- a/arch/riscv/boot/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += start.o
-obj-y += main_entry.o
-obj-$(CONFIG_OFDEVICE) += dtb.o
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 12/20] RISC-V: import Linux' optimized string functions
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (10 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 11/20] RISC-V: erizo: move to arch/riscv/boards/erizo Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 13/20] RISC-V: implement PBL and relocation support Ahmad Fatoum
` (8 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
For non-NMON enabled board the RISC-V specific settings menu will be
empty. Improve UI/UX by adding something there.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/Kconfig | 7 ++
arch/riscv/include/asm/string.h | 21 +++++-
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/memcpy.S | 108 ++++++++++++++++++++++++++++++
arch/riscv/lib/memmove.S | 64 ++++++++++++++++++
arch/riscv/lib/memset.S | 113 ++++++++++++++++++++++++++++++++
6 files changed, 313 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/lib/memcpy.S
create mode 100644 arch/riscv/lib/memmove.S
create mode 100644 arch/riscv/lib/memset.S
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a7f362d8e80c..b1b24f2e5764 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -70,6 +70,13 @@ endmenu
menu "RISC-V specific settings"
+config RISCV_OPTIMZED_STRING_FUNCTIONS
+ bool "use assembler optimized string functions"
+ help
+ Say yes here to use assembler optimized memcpy / memset functions.
+ These functions work faster than the normal versions but increase
+ your binary size.
+
config HAS_NMON
bool
diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h
index 2997587d820c..1e920c8688ce 100644
--- a/arch/riscv/include/asm/string.h
+++ b/arch/riscv/include/asm/string.h
@@ -1 +1,20 @@
-/* dummy */
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_RISCV_STRING_H
+#define __ASM_RISCV_STRING_H
+
+#ifdef CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#endif
+
+extern void *__memcpy(void *, const void *, __kernel_size_t);
+extern void *__memset(void *, int, __kernel_size_t);
+extern void *__memmove(void *, const void *, __kernel_size_t);
+
+#endif
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 7fe57b0b554c..b983ca8cdca0 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -2,3 +2,4 @@ extra-y += barebox.lds
obj-y += riscv_timer.o
obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o longjmp.o
+obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
new file mode 100644
index 000000000000..51ab716253fa
--- /dev/null
+++ b/arch/riscv/lib/memcpy.S
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 Regents of the University of California
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+/* void *memcpy(void *, const void *, size_t) */
+ENTRY(__memcpy)
+WEAK(memcpy)
+ move t6, a0 /* Preserve return value */
+
+ /* Defer to byte-oriented copy for small sizes */
+ sltiu a3, a2, 128
+ bnez a3, 4f
+ /* Use word-oriented copy only if low-order bits match */
+ andi a3, t6, SZREG-1
+ andi a4, a1, SZREG-1
+ bne a3, a4, 4f
+
+ beqz a3, 2f /* Skip if already aligned */
+ /*
+ * Round to nearest double word-aligned address
+ * greater than or equal to start address
+ */
+ andi a3, a1, ~(SZREG-1)
+ addi a3, a3, SZREG
+ /* Handle initial misalignment */
+ sub a4, a3, a1
+1:
+ lb a5, 0(a1)
+ addi a1, a1, 1
+ sb a5, 0(t6)
+ addi t6, t6, 1
+ bltu a1, a3, 1b
+ sub a2, a2, a4 /* Update count */
+
+2:
+ andi a4, a2, ~((16*SZREG)-1)
+ beqz a4, 4f
+ add a3, a1, a4
+3:
+ REG_L a4, 0(a1)
+ REG_L a5, SZREG(a1)
+ REG_L a6, 2*SZREG(a1)
+ REG_L a7, 3*SZREG(a1)
+ REG_L t0, 4*SZREG(a1)
+ REG_L t1, 5*SZREG(a1)
+ REG_L t2, 6*SZREG(a1)
+ REG_L t3, 7*SZREG(a1)
+ REG_L t4, 8*SZREG(a1)
+ REG_L t5, 9*SZREG(a1)
+ REG_S a4, 0(t6)
+ REG_S a5, SZREG(t6)
+ REG_S a6, 2*SZREG(t6)
+ REG_S a7, 3*SZREG(t6)
+ REG_S t0, 4*SZREG(t6)
+ REG_S t1, 5*SZREG(t6)
+ REG_S t2, 6*SZREG(t6)
+ REG_S t3, 7*SZREG(t6)
+ REG_S t4, 8*SZREG(t6)
+ REG_S t5, 9*SZREG(t6)
+ REG_L a4, 10*SZREG(a1)
+ REG_L a5, 11*SZREG(a1)
+ REG_L a6, 12*SZREG(a1)
+ REG_L a7, 13*SZREG(a1)
+ REG_L t0, 14*SZREG(a1)
+ REG_L t1, 15*SZREG(a1)
+ addi a1, a1, 16*SZREG
+ REG_S a4, 10*SZREG(t6)
+ REG_S a5, 11*SZREG(t6)
+ REG_S a6, 12*SZREG(t6)
+ REG_S a7, 13*SZREG(t6)
+ REG_S t0, 14*SZREG(t6)
+ REG_S t1, 15*SZREG(t6)
+ addi t6, t6, 16*SZREG
+ bltu a1, a3, 3b
+ andi a2, a2, (16*SZREG)-1 /* Update count */
+
+4:
+ /* Handle trailing misalignment */
+ beqz a2, 6f
+ add a3, a1, a2
+
+ /* Use word-oriented copy if co-aligned to word boundary */
+ or a5, a1, t6
+ or a5, a5, a3
+ andi a5, a5, 3
+ bnez a5, 5f
+7:
+ lw a4, 0(a1)
+ addi a1, a1, 4
+ sw a4, 0(t6)
+ addi t6, t6, 4
+ bltu a1, a3, 7b
+
+ ret
+
+5:
+ lb a4, 0(a1)
+ addi a1, a1, 1
+ sb a4, 0(t6)
+ addi t6, t6, 1
+ bltu a1, a3, 5b
+6:
+ ret
+END(__memcpy)
diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S
new file mode 100644
index 000000000000..07d1d2152ba5
--- /dev/null
+++ b/arch/riscv/lib/memmove.S
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+ENTRY(__memmove)
+WEAK(memmove)
+ move t0, a0
+ move t1, a1
+
+ beq a0, a1, exit_memcpy
+ beqz a2, exit_memcpy
+ srli t2, a2, 0x2
+
+ slt t3, a0, a1
+ beqz t3, do_reverse
+
+ andi a2, a2, 0x3
+ li t4, 1
+ beqz t2, byte_copy
+
+word_copy:
+ lw t3, 0(a1)
+ addi t2, t2, -1
+ addi a1, a1, 4
+ sw t3, 0(a0)
+ addi a0, a0, 4
+ bnez t2, word_copy
+ beqz a2, exit_memcpy
+ j byte_copy
+
+do_reverse:
+ add a0, a0, a2
+ add a1, a1, a2
+ andi a2, a2, 0x3
+ li t4, -1
+ beqz t2, reverse_byte_copy
+
+reverse_word_copy:
+ addi a1, a1, -4
+ addi t2, t2, -1
+ lw t3, 0(a1)
+ addi a0, a0, -4
+ sw t3, 0(a0)
+ bnez t2, reverse_word_copy
+ beqz a2, exit_memcpy
+
+reverse_byte_copy:
+ addi a0, a0, -1
+ addi a1, a1, -1
+
+byte_copy:
+ lb t3, 0(a1)
+ addi a2, a2, -1
+ sb t3, 0(a0)
+ add a1, a1, t4
+ add a0, a0, t4
+ bnez a2, byte_copy
+
+exit_memcpy:
+ move a0, t0
+ move a1, t1
+ ret
+END(__memmove)
diff --git a/arch/riscv/lib/memset.S b/arch/riscv/lib/memset.S
new file mode 100644
index 000000000000..34c5360c6705
--- /dev/null
+++ b/arch/riscv/lib/memset.S
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2013 Regents of the University of California
+ */
+
+
+#include <linux/linkage.h>
+#include <asm/asm.h>
+
+/* void *memset(void *, int, size_t) */
+ENTRY(__memset)
+WEAK(memset)
+ move t0, a0 /* Preserve return value */
+
+ /* Defer to byte-oriented fill for small sizes */
+ sltiu a3, a2, 16
+ bnez a3, 4f
+
+ /*
+ * Round to nearest XLEN-aligned address
+ * greater than or equal to start address
+ */
+ addi a3, t0, SZREG-1
+ andi a3, a3, ~(SZREG-1)
+ beq a3, t0, 2f /* Skip if already aligned */
+ /* Handle initial misalignment */
+ sub a4, a3, t0
+1:
+ sb a1, 0(t0)
+ addi t0, t0, 1
+ bltu t0, a3, 1b
+ sub a2, a2, a4 /* Update count */
+
+2: /* Duff's device with 32 XLEN stores per iteration */
+ /* Broadcast value into all bytes */
+ andi a1, a1, 0xff
+ slli a3, a1, 8
+ or a1, a3, a1
+ slli a3, a1, 16
+ or a1, a3, a1
+#ifdef CONFIG_64BIT
+ slli a3, a1, 32
+ or a1, a3, a1
+#endif
+
+ /* Calculate end address */
+ andi a4, a2, ~(SZREG-1)
+ add a3, t0, a4
+
+ andi a4, a4, 31*SZREG /* Calculate remainder */
+ beqz a4, 3f /* Shortcut if no remainder */
+ neg a4, a4
+ addi a4, a4, 32*SZREG /* Calculate initial offset */
+
+ /* Adjust start address with offset */
+ sub t0, t0, a4
+
+ /* Jump into loop body */
+ /* Assumes 32-bit instruction lengths */
+ la a5, 3f
+#ifdef CONFIG_64BIT
+ srli a4, a4, 1
+#endif
+ add a5, a5, a4
+ jr a5
+3:
+ REG_S a1, 0(t0)
+ REG_S a1, SZREG(t0)
+ REG_S a1, 2*SZREG(t0)
+ REG_S a1, 3*SZREG(t0)
+ REG_S a1, 4*SZREG(t0)
+ REG_S a1, 5*SZREG(t0)
+ REG_S a1, 6*SZREG(t0)
+ REG_S a1, 7*SZREG(t0)
+ REG_S a1, 8*SZREG(t0)
+ REG_S a1, 9*SZREG(t0)
+ REG_S a1, 10*SZREG(t0)
+ REG_S a1, 11*SZREG(t0)
+ REG_S a1, 12*SZREG(t0)
+ REG_S a1, 13*SZREG(t0)
+ REG_S a1, 14*SZREG(t0)
+ REG_S a1, 15*SZREG(t0)
+ REG_S a1, 16*SZREG(t0)
+ REG_S a1, 17*SZREG(t0)
+ REG_S a1, 18*SZREG(t0)
+ REG_S a1, 19*SZREG(t0)
+ REG_S a1, 20*SZREG(t0)
+ REG_S a1, 21*SZREG(t0)
+ REG_S a1, 22*SZREG(t0)
+ REG_S a1, 23*SZREG(t0)
+ REG_S a1, 24*SZREG(t0)
+ REG_S a1, 25*SZREG(t0)
+ REG_S a1, 26*SZREG(t0)
+ REG_S a1, 27*SZREG(t0)
+ REG_S a1, 28*SZREG(t0)
+ REG_S a1, 29*SZREG(t0)
+ REG_S a1, 30*SZREG(t0)
+ REG_S a1, 31*SZREG(t0)
+ addi t0, t0, 32*SZREG
+ bltu t0, a3, 3b
+ andi a2, a2, SZREG-1 /* Update count */
+
+4:
+ /* Handle trailing misalignment */
+ beqz a2, 6f
+ add a3, t0, a2
+5:
+ sb a1, 0(t0)
+ addi t0, t0, 1
+ bltu t0, a3, 5b
+6:
+ ret
+END(__memset)
--
2.29.2
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barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 13/20] RISC-V: implement PBL and relocation support
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (11 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 12/20] RISC-V: import Linux' optimized string functions Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-15 7:43 ` Ahmad Fatoum
2021-03-14 12:27 ` [PATCH 14/20] RISC-V: erizo: migrate to PBL Ahmad Fatoum
` (7 subsequent siblings)
20 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Masahiro Yamada, Ahmad Fatoum, rcz
Given that we only support a single RISC-V board, this puts us in
a good position to make this a multi-image-only architecture.
This commit adds the necessary bits. It's highly inspired by the ARM PBL
support. Notable difference is that for relocations to be generated, it
was necessary to compile with -fpic. The relocation code assumes the
relocation entries to preprocessed. This is done at build-time by
means of the prelink-riscv script imported from U-Boot.
Actual migration to -fpic and prelinking is done along with porting
erizo in a follow-up commit.
Cc: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
Hello Masahiro,
Do you know if Kernel Kbuild has a similiar prelink stage somewhere,
i.e. an optional architecture-specific rule that processes the ELF file
before continuing normally? I'd like for arch/risc/Makefile to define
PRELINK as a command that takes the ELF as an argument and for the
Makefiles to have no knowledge about PRELINK's content or architecture,
but I don't know how to best go about this.
Thanks
---
arch/riscv/Makefile | 1 +
arch/riscv/boot/Makefile | 3 +
arch/riscv/boot/entry.c | 33 +++++
arch/riscv/boot/entry.h | 15 ++
arch/riscv/boot/entry_ll.S | 15 ++
arch/riscv/boot/start.c | 197 +++++++++++++++++++++++++
arch/riscv/boot/uncompress.c | 74 ++++++++++
arch/riscv/include/asm/barebox-riscv.h | 101 +++++++++++++
arch/riscv/include/asm/common.h | 10 +-
arch/riscv/include/asm/elf.h | 7 +
arch/riscv/include/asm/linkage.h | 4 +
arch/riscv/include/asm/sections.h | 15 ++
arch/riscv/lib/Makefile | 3 +
arch/riscv/lib/barebox.lds.S | 14 +-
arch/riscv/lib/pbl.lds.S | 83 +++++++++++
arch/riscv/lib/reloc.c | 64 ++++++++
arch/riscv/lib/runtime-offset.S | 12 ++
arch/riscv/lib/sections.c | 9 ++
arch/riscv/lib/setupc.S | 55 +++++++
scripts/.gitignore | 1 +
scripts/Makefile | 1 +
scripts/Makefile.lib | 11 ++
scripts/prelink-riscv.c | 122 +++++++++++++++
scripts/prelink-riscv.inc | 123 +++++++++++++++
24 files changed, 969 insertions(+), 4 deletions(-)
create mode 100644 arch/riscv/boot/Makefile
create mode 100644 arch/riscv/boot/entry.c
create mode 100644 arch/riscv/boot/entry.h
create mode 100644 arch/riscv/boot/entry_ll.S
create mode 100644 arch/riscv/boot/start.c
create mode 100644 arch/riscv/boot/uncompress.c
create mode 100644 arch/riscv/include/asm/barebox-riscv.h
create mode 100644 arch/riscv/lib/pbl.lds.S
create mode 100644 arch/riscv/lib/reloc.c
create mode 100644 arch/riscv/lib/runtime-offset.S
create mode 100644 arch/riscv/lib/sections.c
create mode 100644 arch/riscv/lib/setupc.S
create mode 100644 scripts/prelink-riscv.c
create mode 100644 scripts/prelink-riscv.inc
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index d9cefe32c057..df2b5bb681a4 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -43,6 +43,7 @@ endif
common-y += $(MACH)
common-y += arch/riscv/boards/
common-y += arch/riscv/lib/
+common-y += arch/riscv/boot/
common-$(CONFIG_OFTREE) += arch/riscv/dts/
diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
new file mode 100644
index 000000000000..954e9b602287
--- /dev/null
+++ b/arch/riscv/boot/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-y += start.o
+obj-pbl-y += entry.o entry_ll.o uncompress.o
diff --git a/arch/riscv/boot/entry.c b/arch/riscv/boot/entry.c
new file mode 100644
index 000000000000..ec506acfa3b2
--- /dev/null
+++ b/arch/riscv/boot/entry.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <types.h>
+
+#include <asm/barebox-riscv.h>
+
+#include "entry.h"
+#include <debug_ll.h>
+
+/*
+ * Main RISC-V entry point. Call this with the memory region you can
+ * spare for barebox. This doesn't necessarily have to be the full
+ * SDRAM. The currently running binary can be inside or outside of
+ * this region. The PBL can be running inside or outside of this
+ * region.
+ *
+ * -> membase + memsize
+ * STACK_SIZE - stack
+ * 128KiB - early memory space
+ * -> maximum end of barebox binary
+ */
+
+void __noreturn __barebox_riscv_entry(unsigned long membase,
+ unsigned long memsize,
+ void *boarddata,
+ unsigned long sp);
+
+void __noreturn barebox_riscv_entry(unsigned long membase,
+ unsigned long memsize, void *boarddata)
+{
+ __barebox_riscv_entry(membase, memsize, boarddata,
+ riscv_mem_stack_top(membase, membase + memsize));
+}
+
diff --git a/arch/riscv/boot/entry.h b/arch/riscv/boot/entry.h
new file mode 100644
index 000000000000..b3a24d2783f7
--- /dev/null
+++ b/arch/riscv/boot/entry.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ENTRY_H__
+#define __ENTRY_H__
+
+#include <common.h>
+
+void __noreturn barebox_non_pbl_start(unsigned long membase,
+ unsigned long memsize,
+ void *boarddata);
+
+void __noreturn barebox_pbl_start(unsigned long membase,
+ unsigned long memsize,
+ void *boarddata);
+
+#endif
diff --git a/arch/riscv/boot/entry_ll.S b/arch/riscv/boot/entry_ll.S
new file mode 100644
index 000000000000..7011fefad865
--- /dev/null
+++ b/arch/riscv/boot/entry_ll.S
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <linux/linkage.h>
+#include <asm/sections.h>
+
+/*
+ * a0: memory base
+ * a1: memory size
+ * a2: board data
+ * a3: new value for SP
+ */
+.section .text.__barebox_riscv_entry
+ENTRY(__barebox_riscv_entry)
+ move sp, a3
+ j barebox_pbl_start
+ENDPROC(__barebox_riscv_entry)
diff --git a/arch/riscv/boot/start.c b/arch/riscv/boot/start.c
new file mode 100644
index 000000000000..7fcbafcc0758
--- /dev/null
+++ b/arch/riscv/boot/start.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2010 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+
+#define pr_fmt(fmt) "start.c: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <linux/sizes.h>
+#include <of.h>
+#include <asm/barebox-riscv.h>
+#include <asm-generic/memory_layout.h>
+#include <asm/sections.h>
+#include <asm/unaligned.h>
+#include <linux/kasan.h>
+#include <memory.h>
+#include <uncompress.h>
+#include <malloc.h>
+
+#include <debug_ll.h>
+
+#include "entry.h"
+
+unsigned long riscv_stack_top;
+static unsigned long riscv_barebox_size;
+static unsigned long riscv_endmem;
+static void *barebox_boarddata;
+static unsigned long barebox_boarddata_size;
+
+static bool blob_is_fdt(const void *blob)
+{
+ return get_unaligned_be32(blob) == FDT_MAGIC;
+}
+
+static bool blob_is_compressed_fdt(const void *blob)
+{
+ const struct barebox_riscv_boarddata_compressed_dtb *dtb = blob;
+
+ return dtb->magic == BAREBOX_RISCV_BOARDDATA_COMPRESSED_DTB_MAGIC;
+}
+
+void *barebox_riscv_boot_dtb(void)
+{
+ void *dtb;
+ void *data;
+ int ret;
+ struct barebox_riscv_boarddata_compressed_dtb *compressed_dtb;
+ static void *boot_dtb;
+
+ if (boot_dtb)
+ return boot_dtb;
+
+ if (barebox_boarddata && blob_is_fdt(barebox_boarddata)) {
+ pr_debug("%s: using barebox_boarddata\n", __func__);
+ return barebox_boarddata;
+ }
+
+ if (!IS_ENABLED(CONFIG_USE_COMPRESSED_DTB) || !barebox_boarddata
+ || !blob_is_compressed_fdt(barebox_boarddata))
+ return NULL;
+
+ compressed_dtb = barebox_boarddata;
+
+ pr_debug("%s: using compressed_dtb\n", __func__);
+
+ dtb = malloc(compressed_dtb->datalen_uncompressed);
+ if (!dtb)
+ return NULL;
+
+ data = compressed_dtb + 1;
+
+ ret = uncompress(data, compressed_dtb->datalen, NULL, NULL, dtb, NULL, NULL);
+ if (ret) {
+ pr_err("uncompressing dtb failed\n");
+ free(dtb);
+ return NULL;
+ }
+
+ boot_dtb = dtb;
+
+ return boot_dtb;
+}
+
+static inline unsigned long riscv_mem_boarddata(unsigned long membase,
+ unsigned long endmem,
+ unsigned long size)
+{
+ unsigned long mem;
+
+ mem = riscv_mem_barebox_image(membase, endmem, riscv_barebox_size);
+ mem -= ALIGN(size, 64);
+
+ return mem;
+}
+
+unsigned long riscv_mem_ramoops_get(void)
+{
+ return riscv_mem_ramoops(0, riscv_stack_top);
+}
+EXPORT_SYMBOL_GPL(riscv_mem_ramoops_get);
+
+unsigned long riscv_mem_endmem_get(void)
+{
+ return riscv_endmem;
+}
+EXPORT_SYMBOL_GPL(riscv_mem_endmem_get);
+
+static int barebox_memory_areas_init(void)
+{
+ if(barebox_boarddata)
+ request_sdram_region("board data", (unsigned long)barebox_boarddata,
+ barebox_boarddata_size);
+
+ return 0;
+}
+device_initcall(barebox_memory_areas_init);
+
+/*
+ * First function in the uncompressed image. We get here from
+ * the pbl. The stack already has been set up by the pbl.
+ */
+__noreturn __no_sanitize_address __section(.text_entry)
+void barebox_non_pbl_start(unsigned long membase, unsigned long memsize, void *boarddata)
+{
+ unsigned long endmem = membase + memsize;
+ unsigned long malloc_start, malloc_end;
+ unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE;
+ unsigned long barebox_base = riscv_mem_barebox_image(membase, endmem, barebox_size);
+
+ relocate_to_current_adr();
+
+ setup_c();
+
+ barrier();
+
+ pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize);
+
+ riscv_endmem = endmem;
+ riscv_stack_top = riscv_mem_stack_top(membase, endmem);
+ riscv_barebox_size = barebox_size;
+ malloc_end = barebox_base;
+
+ if (boarddata) {
+ uint32_t totalsize = 0;
+ const char *name;
+
+ if (blob_is_fdt(boarddata)) {
+ totalsize = get_unaligned_be32(boarddata + 4);
+ name = "DTB";
+ } else if (blob_is_compressed_fdt(boarddata)) {
+ struct barebox_riscv_boarddata_compressed_dtb *bd = boarddata;
+ totalsize = bd->datalen + sizeof(*bd);
+ name = "Compressed DTB";
+ }
+
+ if (totalsize) {
+ unsigned long mem = riscv_mem_boarddata(membase, endmem, totalsize);
+ pr_debug("found %s in boarddata, copying to 0x%08lx\n", name, mem);
+ barebox_boarddata = memcpy((void *)mem, boarddata, totalsize);
+ barebox_boarddata_size = totalsize;
+ malloc_end = mem;
+ }
+ }
+
+ /*
+ * Maximum malloc space is the Kconfig value if given
+ * or 1GB.
+ */
+ if (MALLOC_SIZE > 0) {
+ malloc_start = malloc_end - MALLOC_SIZE;
+ if (malloc_start < membase)
+ malloc_start = membase;
+ } else {
+ malloc_start = malloc_end - (malloc_end - membase) / 2;
+ if (malloc_end - malloc_start > SZ_1G)
+ malloc_start = malloc_end - SZ_1G;
+ }
+
+ pr_debug("initializing malloc pool at 0x%08lx (size 0x%08lx)\n",
+ malloc_start, malloc_end - malloc_start);
+
+ mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1);
+
+ pr_debug("starting barebox...\n");
+
+ start_barebox();
+}
+
+void start(unsigned long membase, unsigned long memsize, void *boarddata);
+/*
+ * First function in the uncompressed image. We get here from
+ * the pbl. The stack already has been set up by the pbl.
+ */
+void __no_sanitize_address __section(.text_entry) start(unsigned long membase,
+ unsigned long memsize, void *boarddata)
+{
+ barebox_non_pbl_start(membase, memsize, boarddata);
+}
diff --git a/arch/riscv/boot/uncompress.c b/arch/riscv/boot/uncompress.c
new file mode 100644
index 000000000000..cf268bece1bf
--- /dev/null
+++ b/arch/riscv/boot/uncompress.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2010-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+/* uncompress.c - uncompressor code for self extracing pbl image */
+
+#define pr_fmt(fmt) "uncompress.c: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <linux/sizes.h>
+#include <pbl.h>
+#include <asm/barebox-riscv.h>
+#include <asm-generic/memory_layout.h>
+#include <asm/sections.h>
+#include <asm/unaligned.h>
+
+#include <debug_ll.h>
+
+#include "entry.h"
+
+unsigned long free_mem_ptr;
+unsigned long free_mem_end_ptr;
+
+extern unsigned char input_data[];
+extern unsigned char input_data_end[];
+
+void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
+ void *fdt)
+{
+ uint32_t pg_len, uncompressed_len;
+ void __noreturn (*barebox)(unsigned long, unsigned long, void *);
+ unsigned long endmem = membase + memsize;
+ unsigned long barebox_base;
+ void *pg_start, *pg_end;
+ unsigned long pc = get_pc();
+
+ pg_start = input_data + get_runtime_offset();
+ pg_end = input_data_end + get_runtime_offset();
+
+ /*
+ * If we run from inside the memory just relocate the binary
+ * to the current address. Otherwise it may be a readonly location.
+ * Copy and relocate to the start of the memory in this case.
+ */
+ if (pc > membase && pc - membase < memsize)
+ relocate_to_current_adr();
+ else
+ relocate_to_adr(membase);
+
+ pg_len = pg_end - pg_start;
+ uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4));
+
+ barebox_base = riscv_mem_barebox_image(membase, endmem,
+ uncompressed_len + MAX_BSS_SIZE);
+
+ setup_c();
+
+ pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize);
+
+ free_mem_ptr = riscv_mem_early_malloc(membase, endmem);
+ free_mem_end_ptr = riscv_mem_early_malloc_end(membase, endmem);
+
+ pr_debug("uncompressing barebox binary at 0x%p (size 0x%08x) to 0x%08lx (uncompressed size: 0x%08x)\n",
+ pg_start, pg_len, barebox_base, uncompressed_len);
+
+ pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len);
+
+ barebox = (void *)barebox_base;
+
+ pr_debug("jumping to uncompressed image at 0x%p. dtb=0x%p\n", barebox, fdt);
+
+ barebox(membase, memsize, fdt);
+}
diff --git a/arch/riscv/include/asm/barebox-riscv.h b/arch/riscv/include/asm/barebox-riscv.h
new file mode 100644
index 000000000000..05e076c4868b
--- /dev/null
+++ b/arch/riscv/include/asm/barebox-riscv.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ */
+
+#ifndef _BAREBOX_RISCV_H_
+#define _BAREBOX_RISCV_H_
+
+#include <linux/sizes.h>
+#include <asm-generic/memory_layout.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
+#include <asm/sections.h>
+
+unsigned long get_runtime_offset(void);
+
+void setup_c(void);
+void relocate_to_current_adr(void);
+void relocate_to_adr(unsigned long target);
+void __noreturn barebox_riscv_entry(unsigned long membase, unsigned long memsize, void *boarddata);
+
+unsigned long riscv_mem_ramoops_get(void);
+unsigned long riscv_mem_endmem_get(void);
+
+struct barebox_riscv_boarddata_compressed_dtb {
+#define BAREBOX_RISCV_BOARDDATA_COMPRESSED_DTB_MAGIC 0x7b66bcbd
+ u32 magic;
+ u32 datalen;
+ u32 datalen_uncompressed;
+};
+
+void *barebox_riscv_boot_dtb(void);
+
+static inline unsigned long riscv_mem_stack_top(unsigned long membase,
+ unsigned long endmem)
+{
+ return endmem - SZ_2M;
+}
+
+static inline unsigned long riscv_mem_stack(unsigned long membase,
+ unsigned long endmem)
+{
+ return riscv_mem_stack_top(membase, endmem) - STACK_SIZE;
+}
+
+static inline unsigned long riscv_mem_early_malloc(unsigned long membase,
+ unsigned long endmem)
+{
+ return riscv_mem_stack(membase, endmem) - SZ_128K;
+}
+
+static inline unsigned long riscv_mem_early_malloc_end(unsigned long membase,
+ unsigned long endmem)
+{
+ return riscv_mem_stack(membase, endmem);
+}
+
+static inline unsigned long riscv_mem_ramoops(unsigned long membase,
+ unsigned long endmem)
+{
+ endmem = riscv_mem_stack(membase, endmem);
+#ifdef CONFIG_FS_PSTORE_RAMOOPS
+ endmem -= CONFIG_FS_PSTORE_RAMOOPS_SIZE;
+ endmem = ALIGN_DOWN(endmem, SZ_4K);
+#endif
+
+ return endmem;
+}
+
+static inline unsigned long riscv_mem_barebox_image(unsigned long membase,
+ unsigned long endmem,
+ unsigned long size)
+{
+ endmem = riscv_mem_ramoops(membase, endmem);
+
+ return ALIGN_DOWN(endmem - size, SZ_1M);
+}
+
+#define ENTRY_FUNCTION(name, arg0, arg1, arg2) \
+ void name (ulong a0, ulong a1, ulong a2); \
+ void __section(.text_head_entry_##name) name (ulong a0, ulong a1, ulong a2)
+
+/*
+ * When using compressed images in conjunction with relocatable images
+ * the PBL code must pick a suitable place where to uncompress the barebox
+ * image. For doing this the PBL code must know the size of the final
+ * image including the BSS segment. The BSS size is unknown to the PBL
+ * code, so define a maximum BSS size here.
+ */
+#define MAX_BSS_SIZE SZ_1M
+
+#define barebox_image_size (__image_end - __image_start)
+
+#endif /* _BAREBOX_RISCV_H_ */
diff --git a/arch/riscv/include/asm/common.h b/arch/riscv/include/asm/common.h
index bc8a17e30bc5..a0982c548fe1 100644
--- a/arch/riscv/include/asm/common.h
+++ b/arch/riscv/include/asm/common.h
@@ -1,6 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-FileCopyrightText: Copyright (c) 2021 Ahmad Fatoum, Pengutronix */
#ifndef ASM_RISCV_COMMON_H
#define ASM_RISCV_COMMON_H
-/* nothing special yet */
+#include <linux/compiler.h>
+
+static __always_inline unsigned long get_pc(void)
+{
+label:
+ return (unsigned long)&&label;
+}
#endif /* ASM_RISCV_COMMON_H */
diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index 7134fa05820a..adb8ec8f6ece 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_RISCV_ELF_H__
#define __ASM_RISCV_ELF_H__
@@ -8,4 +9,10 @@
#define ELF_CLASS ELFCLASS32
#endif
+/* Relocation types used by the dynamic linker */
+#define R_RISCV_NONE 0
+#define R_RISCV_32 1
+#define R_RISCV_64 2
+#define R_RISCV_RELATIVE 3
+
#endif /* __ASM_RISCV_ELF_H__ */
diff --git a/arch/riscv/include/asm/linkage.h b/arch/riscv/include/asm/linkage.h
index 9e88ba23cd2b..c6801294f388 100644
--- a/arch/riscv/include/asm/linkage.h
+++ b/arch/riscv/include/asm/linkage.h
@@ -9,4 +9,8 @@
#define __ALIGN .balign 4
#define __ALIGN_STR ".balign 4"
+#define ENDPROC(name) \
+ .type name, %function; \
+ END(name)
+
#endif /* _ASM_RISCV_LINKAGE_H */
diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h
index 2b8c5160388f..b5fbba8f165a 100644
--- a/arch/riscv/include/asm/sections.h
+++ b/arch/riscv/include/asm/sections.h
@@ -1 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __ASM_SECTIONS_H
+#define __ASM_SECTIONS_H
+
+#ifndef __ASSEMBLY__
#include <asm-generic/sections.h>
+#include <linux/types.h>
+
+extern char __rel_dyn_start[];
+extern char __rel_dyn_end[];
+extern char __dynsym_start[];
+extern char __dynsym_end[];
+
+#endif
+
+#endif /* __ASM_SECTIONS_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index b983ca8cdca0..5f57d9fcd2e2 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -1,5 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+
extra-y += barebox.lds
obj-y += riscv_timer.o
+obj-pbl-y += sections.o setupc.o reloc.o sections.o runtime-offset.o
obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o longjmp.o
obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o
diff --git a/arch/riscv/lib/barebox.lds.S b/arch/riscv/lib/barebox.lds.S
index 342769890bb0..c8a331c577cf 100644
--- a/arch/riscv/lib/barebox.lds.S
+++ b/arch/riscv/lib/barebox.lds.S
@@ -43,10 +43,18 @@ SECTIONS
.barebox_imd : { BAREBOX_IMD }
- . = ALIGN(8);
- .got : { *(.got*) }
+ /DISCARD/ : { *(.rela.plt*) }
+ .rela.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
- .rela.dyn : { *(.rela*) }
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ __dynsym_end = .;
+ }
_edata = .;
. = ALIGN(8);
diff --git a/arch/riscv/lib/pbl.lds.S b/arch/riscv/lib/pbl.lds.S
new file mode 100644
index 000000000000..33caab7b1024
--- /dev/null
+++ b/arch/riscv/lib/pbl.lds.S
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */
+
+#include <linux/sizes.h>
+#include <asm-generic/barebox.lds.h>
+#include <asm-generic/memory_layout.h>
+
+OUTPUT_ARCH(riscv)
+SECTIONS
+{
+ . = 0x0;
+
+ .image_start : { *(.__image_start) }
+
+ . = ALIGN(4);
+ ._text : { *(._text) }
+ .text :
+ {
+ _stext = .;
+ *(.text_head_entry*)
+ __bare_init_start = .;
+ *(.text_bare_init*)
+ __bare_init_end = .;
+ *(.text*)
+ }
+
+ /* Discard unwind if enable in barebox */
+ /DISCARD/ : { *(.ARM.ex*) }
+
+ BAREBOX_BARE_INIT_SIZE
+ BAREBOX_PBL_SIZE
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata*) }
+
+ .barebox_imd : { BAREBOX_IMD }
+
+ _etext = .; /* End of text and rodata section */
+
+ .data : { *(.data*) }
+
+ __shasum_start = .;
+ .shasum : {
+ KEEP(*(.shasum))
+ }
+ __shasum_end = .;
+
+ /DISCARD/ : { *(.rela.plt*) }
+ .rela.dyn : {
+ __rel_dyn_start = .;
+ *(.rela*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ __dynsym_end = .;
+ }
+
+ pbl_code_size = .;
+
+ .__bss_start : { *(.__bss_start) }
+ .bss : { *(.bss*) }
+ .__bss_stop : { *(.__bss_stop) }
+ _end = .;
+
+ pbl_memory_size = .;
+
+ . = ALIGN(4);
+ __piggydata_start = .;
+ .piggydata : {
+ *(.piggydata)
+ }
+ __piggydata_end = .;
+
+ .image_end : { KEEP(*(.__image_end)) }
+
+ pbl_image_size = .;
+
+ _barebox_image_size = __image_end;
+ _barebox_pbl_size = __bss_start;
+}
diff --git a/arch/riscv/lib/reloc.c b/arch/riscv/lib/reloc.c
new file mode 100644
index 000000000000..5e26c0be9c1c
--- /dev/null
+++ b/arch/riscv/lib/reloc.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+// SPDX-FileCopyrightText: Copyright (c) 2021 Ahmad Fatoum, Pengutronix
+
+#include <common.h>
+#include <linux/linkage.h>
+#include <asm/sections.h>
+#include <asm/barebox-riscv.h>
+#include <debug_ll.h>
+#include <asm-generic/module.h>
+
+#include <elf.h>
+
+#if __riscv_xlen == 64
+#define Elf_Rela Elf64_Rela
+#define R_RISCV_ABSOLUTE R_RISCV_64
+#define DYNSYM_ENTRY(dynsym, rela) dynsym[ELF_R_SYM(rela->r_info) * 3 + 1]
+#elif __riscv_xlen == 32
+#define Elf_Rela Elf32_Rela
+#define R_RISCV_ABSOLUTE R_RISCV_32
+#define DYNSYM_ENTRY(dynsym, rela) dynsym[ELF_R_SYM(rela->r_info) * 4 + 1]
+#else
+#error unknown riscv target
+#endif
+
+#define RISC_R_TYPE(x) ((x) & 0xFF)
+
+void relocate_to_current_adr(void)
+{
+ unsigned long offset;
+ unsigned long *dynsym;
+ void *dstart, *dend;
+ Elf_Rela *rela;
+
+ /* Get offset between linked address and runtime address */
+ offset = get_runtime_offset();
+
+ dstart = __rel_dyn_start + offset;
+ dend = __rel_dyn_end + offset;
+ dynsym = (void *)__dynsym_start + offset;
+
+ for (rela = dstart; (void *)rela < dend; rela++) {
+ unsigned long *fixup;
+
+ fixup = (unsigned long *)(rela->r_offset + offset);
+
+ switch (RISC_R_TYPE(rela->r_info)) {
+ case R_RISCV_RELATIVE:
+ *fixup = rela->r_addend + offset;
+ break;
+ case R_RISCV_ABSOLUTE:
+ *fixup = DYNSYM_ENTRY(dynsym, rela) + rela->r_addend + offset;
+ break;
+ default:
+ putc_ll('>');
+ puthex_ll(rela->r_info);
+ putc_ll(' ');
+ puthex_ll(rela->r_offset);
+ putc_ll(' ');
+ puthex_ll(rela->r_addend);
+ putc_ll('\n');
+ panic("");
+ }
+ }
+}
diff --git a/arch/riscv/lib/runtime-offset.S b/arch/riscv/lib/runtime-offset.S
new file mode 100644
index 000000000000..f6a040628963
--- /dev/null
+++ b/arch/riscv/lib/runtime-offset.S
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-FileCopyrightText: Copyright (c) 2021 Ahmad Fatoum, Pengutronix */
+#include <linux/linkage.h>
+#include <asm/sections.h>
+
+.section ".text_bare_init","ax"
+ENTRY(get_runtime_offset)
+ lla a0, _text /* load addr */
+ la a1, _text /* link addr */
+ sub a0, a0, a1
+ ret
+ENDPROC(get_runtime_offset)
diff --git a/arch/riscv/lib/sections.c b/arch/riscv/lib/sections.c
new file mode 100644
index 000000000000..e23a41dcf5d4
--- /dev/null
+++ b/arch/riscv/lib/sections.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#include <asm/sections.h>
+#include <linux/types.h>
+
+char _text[0] __attribute__((section("._text")));
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_stop[0] __attribute__((section(".__bss_stop")));
+char __image_start[0] __attribute__((section(".__image_start")));
+char __image_end[0] __attribute__((section(".__image_end")));
diff --git a/arch/riscv/lib/setupc.S b/arch/riscv/lib/setupc.S
new file mode 100644
index 000000000000..6d824d00f7e0
--- /dev/null
+++ b/arch/riscv/lib/setupc.S
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-FileCopyrightText: Copyright (c) 2021 Ahmad Fatoum, Pengutronix */
+
+#include <linux/linkage.h>
+#include <asm/sections.h>
+#include <asm/asm.h>
+
+/*
+ * setup_c: clear bss
+ */
+.section .text.setup_c
+ENTRY(setup_c)
+ lla a0, __bss_start
+ li a1, 0
+ lla a2, __bss_stop
+ sub a2, a2, a0
+ j __memset
+ENDPROC(setup_c)
+
+/*
+ * void relocate_to_adr(unsigned long targetadr)
+ *
+ * Copy binary to targetadr, relocate code and continue
+ * executing at new address.
+ */
+.section .text.relocate_to_adr
+ENTRY(relocate_to_adr)
+ /* a0: target address */
+ addi sp, sp, -SZREG * 2
+ lla a1, _text /* a1: source address */
+
+ beq a0, a1, copied /* skip if already at new address */
+
+ lla a2, copied
+ sub a2, a2, a1
+ add a2, a2, a0
+ REG_S a2, (SZREG * 1)(sp)
+
+ /* adjust return address */
+ sub ra, ra, a1 /* sub address where we are actually running */
+ add ra, ra, a0 /* add address where we are going to run */
+ REG_S ra, (SZREG * 2)(sp)
+
+ lla a2, __bss_start
+ sub a2, a2, a1 /* a2: size */
+
+ jal __memcpy
+
+ REG_L a0, (SZREG * 1)(sp)
+ jr a0 /* jump to relocated address */
+copied:
+ REG_L ra, (SZREG * 2)(sp)
+ addi sp, sp, SZREG * 2
+ j relocate_to_current_adr /* relocate binary */
+ENDPROC(relocate_to_adr)
diff --git a/scripts/.gitignore b/scripts/.gitignore
index 7c9a3f55715f..9577d568edd0 100644
--- a/scripts/.gitignore
+++ b/scripts/.gitignore
@@ -32,3 +32,4 @@ mips-relocs
rsatoc
stm32image
mvebuimg
+prelink-riscv
diff --git a/scripts/Makefile b/scripts/Makefile
index 744f4dd0e7e6..4dc70815b7e6 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -24,6 +24,7 @@ hostprogs-always-$(CONFIG_ARCH_SOCFPGA) += socfpga_mkimage
hostprogs-always-$(CONFIG_ARCH_MXS) += mxsimage mxsboot
hostprogs-always-$(CONFIG_ARCH_LAYERSCAPE) += pblimage
hostprogs-always-$(CONFIG_ARCH_STM32MP) += stm32image
+hostprogs-always-$(CONFIG_RISCV) += prelink-riscv
KBUILD_HOSTCFLAGS += -I$(srctree)/scripts/include/
HOSTLDLIBS_mxsimage = `pkg-config --libs openssl`
HOSTCFLAGS_omap3-usb-loader.o = `pkg-config --cflags libusb-1.0`
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 2844d29be600..319ac19975ed 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -247,6 +247,17 @@ $(obj)/%:: $(src)/%_shipped
# and add target to extra-y so that we know we have to
# read in the saved command line
+# Prelinking
+# ---------------------------------------------------------------------------
+
+ifneq ($(CONFIG_RISCV),)
+quiet_cmd_prelink__ = PRELINK $@
+ cmd_prelink__ = $(objtree)/scripts/prelink-riscv $@
+endif
+
+quiet_cmd_prelink__ ?=
+ cmd_prelink__ ?=
+
# Linking
# ---------------------------------------------------------------------------
diff --git a/scripts/prelink-riscv.c b/scripts/prelink-riscv.c
new file mode 100644
index 000000000000..c185d3981ca1
--- /dev/null
+++ b/scripts/prelink-riscv.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology
+ * Chih-Mao Chen <cmchen@andestech.com>
+ *
+ * Statically process runtime relocations on RISC-V ELF images
+ * so that it can be directly executed when loaded at LMA
+ * without fixup. Both RV32 and RV64 are supported.
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <elf.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+#include "compiler.h"
+
+#ifndef EM_RISCV
+#define EM_RISCV 243
+#endif
+
+#ifndef R_RISCV_32
+#define R_RISCV_32 1
+#endif
+
+#ifndef R_RISCV_64
+#define R_RISCV_64 2
+#endif
+
+#ifndef R_RISCV_RELATIVE
+#define R_RISCV_RELATIVE 3
+#endif
+
+const char *argv0;
+
+#define die(fmt, ...) \
+ do { \
+ fprintf(stderr, "%s: " fmt "\n", argv0, ## __VA_ARGS__); \
+ exit(EXIT_FAILURE); \
+ } while (0)
+
+#define PRELINK_BYTEORDER le
+#define PRELINK_INC_BITS 32
+#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
+#undef PRELINK_INC_BITS
+
+#define PRELINK_BYTEORDER le
+#define PRELINK_INC_BITS 64
+#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
+#undef PRELINK_INC_BITS
+
+#define PRELINK_BYTEORDER be
+#define PRELINK_INC_BITS 32
+#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
+#undef PRELINK_INC_BITS
+
+#define PRELINK_BYTEORDER be
+#define PRELINK_INC_BITS 64
+#include "prelink-riscv.inc"
+#undef PRELINK_BYTEORDER
+#undef PRELINK_INC_BITS
+
+int main(int argc, const char *const *argv)
+{
+ argv0 = argv[0];
+
+ if (argc < 2) {
+ fprintf(stderr, "Usage: %s <u-boot>\n", argv0);
+ exit(EXIT_FAILURE);
+ }
+
+ int fd = open(argv[1], O_RDWR, 0);
+
+ if (fd < 0)
+ die("Cannot open %s: %s", argv[1], strerror(errno));
+
+ struct stat st;
+
+ if (fstat(fd, &st) < 0)
+ die("Cannot stat %s: %s", argv[1], strerror(errno));
+
+ void *data =
+ mmap(0, st.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+
+ if (data == MAP_FAILED)
+ die("Cannot mmap %s: %s", argv[1], strerror(errno));
+
+ close(fd);
+
+ unsigned char *e_ident = (unsigned char *)data;
+
+ if (memcmp(e_ident, ELFMAG, SELFMAG) != 0)
+ die("Invalid ELF file %s", argv[1]);
+
+ bool is64 = e_ident[EI_CLASS] == ELFCLASS64;
+ bool isbe = e_ident[EI_DATA] == ELFDATA2MSB;
+
+ if (is64) {
+ if (isbe)
+ prelink_be64(data);
+ else
+ prelink_le64(data);
+ } else {
+ if (isbe)
+ prelink_be32(data);
+ else
+ prelink_le32(data);
+ }
+
+ return 0;
+}
diff --git a/scripts/prelink-riscv.inc b/scripts/prelink-riscv.inc
new file mode 100644
index 000000000000..f2b5467f5b3c
--- /dev/null
+++ b/scripts/prelink-riscv.inc
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Andes Technology
+ * Chih-Mao Chen <cmchen@andestech.com>
+ *
+ * Statically process runtime relocations on RISC-V ELF images
+ * so that it can be directly executed when loaded at LMA
+ * without fixup. Both RV32 and RV64 are supported.
+ */
+
+#define CONCAT_IMPL(x, y) x##y
+#define CONCAT(x, y) CONCAT_IMPL(x, y)
+#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
+
+#define prelink_bonn CONCAT3(prelink_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
+#define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t)
+#define get_offset_bonn CONCAT3(get_offset_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
+#define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
+#define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
+#define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
+#define Elf_Sym CONCAT3(Elf, PRELINK_INC_BITS, _Sym)
+#define Elf_Dyn CONCAT3(Elf, PRELINK_INC_BITS, _Dyn)
+#define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
+#define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
+#define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
+#define target16_to_cpu CONCAT(PRELINK_BYTEORDER, 16_to_cpu)
+#define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
+#define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
+#define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
+#define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
+#define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)
+
+static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
+{
+ Elf_Phdr *p;
+
+ for (p = phdrs; p < phdrs + phnum; ++p)
+ if (targetnn_to_cpu(p->p_vaddr) <= addr && targetnn_to_cpu(p->p_vaddr) + targetnn_to_cpu(p->p_memsz) > addr)
+ return data + targetnn_to_cpu(p->p_offset) + (addr - targetnn_to_cpu(p->p_vaddr));
+
+ return NULL;
+}
+
+static void prelink_bonn(void *data)
+{
+ Elf_Ehdr *ehdr = data;
+ Elf_Phdr *p;
+ Elf_Dyn *dyn;
+ Elf_Rela *r;
+
+ if (target16_to_cpu(ehdr->e_machine) != EM_RISCV)
+ die("Machine type is not RISC-V");
+
+ Elf_Phdr *phdrs = data + targetnn_to_cpu(ehdr->e_phoff);
+
+ Elf_Dyn *dyns = NULL;
+ for (p = phdrs; p < phdrs + target16_to_cpu(ehdr->e_phnum); ++p) {
+ if (target32_to_cpu(p->p_type) == PT_DYNAMIC) {
+ dyns = data + targetnn_to_cpu(p->p_offset);
+ break;
+ }
+ }
+
+ if (dyns == NULL)
+ die("No dynamic section found");
+
+ Elf_Rela *rela_dyn = NULL;
+ size_t rela_count = 0;
+ Elf_Sym *dynsym = NULL;
+ for (dyn = dyns;; ++dyn) {
+ if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
+ break;
+ else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
+ rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
+ else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
+ rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
+ else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
+ dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
+
+ }
+
+ if (rela_dyn == NULL)
+ die("No .rela.dyn found");
+
+ if (dynsym == NULL)
+ die("No .dynsym found");
+
+ for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
+ void* buf = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), targetnn_to_cpu(r->r_offset));
+
+ if (buf == NULL)
+ continue;
+
+ if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
+ *((uintnn_t*) buf) = r->r_addend;
+ else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
+ *((uint32_t*) buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
+ else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
+ *((uint64_t*) buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
+ }
+}
+
+#undef prelink_bonn
+#undef uintnn_t
+#undef get_offset_bonn
+#undef Elf_Ehdr
+#undef Elf_Phdr
+#undef Elf_Rela
+#undef Elf_Sym
+#undef Elf_Dyn
+#undef Elf_Addr
+#undef ELF_R_TYPE
+#undef ELF_R_SYM
+#undef target16_to_cpu
+#undef target32_to_cpu
+#undef target64_to_cpu
+#undef targetnn_to_cpu
+#undef cpu_to_target32
+#undef cpu_to_target64
+
+#undef CONCAT_IMPL
+#undef CONCAT
+#undef CONCAT3
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 13/20] RISC-V: implement PBL and relocation support
2021-03-14 12:27 ` [PATCH 13/20] RISC-V: implement PBL and relocation support Ahmad Fatoum
@ 2021-03-15 7:43 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-15 7:43 UTC (permalink / raw)
To: barebox; +Cc: Masahiro Yamada, rcz
On 14.03.21 13:27, Ahmad Fatoum wrote:
> Given that we only support a single RISC-V board, this puts us in
> a good position to make this a multi-image-only architecture.
>
> This commit adds the necessary bits. It's highly inspired by the ARM PBL
> support. Notable difference is that for relocations to be generated, it
> was necessary to compile with -fpic. The relocation code assumes the
> relocation entries to preprocessed. This is done at build-time by
> means of the prelink-riscv script imported from U-Boot.
>
> Actual migration to -fpic and prelinking is done along with porting
> erizo in a follow-up commit.
>
> Cc: Masahiro Yamada <masahiroy@kernel.org>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>
> ---
> Hello Masahiro,
>
> Do you know if Kernel Kbuild has a similiar prelink stage somewhere,
> i.e. an optional architecture-specific rule that processes the ELF file
> before continuing normally? I'd like for arch/risc/Makefile to define
> PRELINK as a command that takes the ELF as an argument and for the
> Makefiles to have no knowledge about PRELINK's content or architecture,
> but I don't know how to best go about this.
>
> Thanks
> ---
> arch/riscv/Makefile | 1 +
> arch/riscv/boot/Makefile | 3 +
> arch/riscv/boot/entry.c | 33 +++++
> arch/riscv/boot/entry.h | 15 ++
> arch/riscv/boot/entry_ll.S | 15 ++
> arch/riscv/boot/start.c | 197 +++++++++++++++++++++++++
> arch/riscv/boot/uncompress.c | 74 ++++++++++
> arch/riscv/include/asm/barebox-riscv.h | 101 +++++++++++++
> arch/riscv/include/asm/common.h | 10 +-
> arch/riscv/include/asm/elf.h | 7 +
> arch/riscv/include/asm/linkage.h | 4 +
> arch/riscv/include/asm/sections.h | 15 ++
> arch/riscv/lib/Makefile | 3 +
> arch/riscv/lib/barebox.lds.S | 14 +-
> arch/riscv/lib/pbl.lds.S | 83 +++++++++++
> arch/riscv/lib/reloc.c | 64 ++++++++
> arch/riscv/lib/runtime-offset.S | 12 ++
> arch/riscv/lib/sections.c | 9 ++
> arch/riscv/lib/setupc.S | 55 +++++++
> scripts/.gitignore | 1 +
> scripts/Makefile | 1 +
> scripts/Makefile.lib | 11 ++
> scripts/prelink-riscv.c | 122 +++++++++++++++
> scripts/prelink-riscv.inc | 123 +++++++++++++++
> 24 files changed, 969 insertions(+), 4 deletions(-)
> create mode 100644 arch/riscv/boot/Makefile
> create mode 100644 arch/riscv/boot/entry.c
> create mode 100644 arch/riscv/boot/entry.h
> create mode 100644 arch/riscv/boot/entry_ll.S
> create mode 100644 arch/riscv/boot/start.c
> create mode 100644 arch/riscv/boot/uncompress.c
> create mode 100644 arch/riscv/include/asm/barebox-riscv.h
> create mode 100644 arch/riscv/lib/pbl.lds.S
> create mode 100644 arch/riscv/lib/reloc.c
> create mode 100644 arch/riscv/lib/runtime-offset.S
> create mode 100644 arch/riscv/lib/sections.c
> create mode 100644 arch/riscv/lib/setupc.S
> create mode 100644 scripts/prelink-riscv.c
> create mode 100644 scripts/prelink-riscv.inc
>
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index d9cefe32c057..df2b5bb681a4 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -43,6 +43,7 @@ endif
> common-y += $(MACH)
> common-y += arch/riscv/boards/
> common-y += arch/riscv/lib/
> +common-y += arch/riscv/boot/
>
> common-$(CONFIG_OFTREE) += arch/riscv/dts/
>
> diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
> new file mode 100644
> index 000000000000..954e9b602287
> --- /dev/null
> +++ b/arch/riscv/boot/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +obj-y += start.o
> +obj-pbl-y += entry.o entry_ll.o uncompress.o
> diff --git a/arch/riscv/boot/entry.c b/arch/riscv/boot/entry.c
> new file mode 100644
> index 000000000000..ec506acfa3b2
> --- /dev/null
> +++ b/arch/riscv/boot/entry.c
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#include <types.h>
> +
> +#include <asm/barebox-riscv.h>
> +
> +#include "entry.h"
> +#include <debug_ll.h>
> +
> +/*
> + * Main RISC-V entry point. Call this with the memory region you can
> + * spare for barebox. This doesn't necessarily have to be the full
> + * SDRAM. The currently running binary can be inside or outside of
> + * this region. The PBL can be running inside or outside of this
> + * region.
> + *
> + * -> membase + memsize
> + * STACK_SIZE - stack
> + * 128KiB - early memory space
> + * -> maximum end of barebox binary
> + */
> +
> +void __noreturn __barebox_riscv_entry(unsigned long membase,
> + unsigned long memsize,
> + void *boarddata,
> + unsigned long sp);
> +
> +void __noreturn barebox_riscv_entry(unsigned long membase,
> + unsigned long memsize, void *boarddata)
> +{
> + __barebox_riscv_entry(membase, memsize, boarddata,
> + riscv_mem_stack_top(membase, membase + memsize));
> +}
> +
> diff --git a/arch/riscv/boot/entry.h b/arch/riscv/boot/entry.h
> new file mode 100644
> index 000000000000..b3a24d2783f7
> --- /dev/null
> +++ b/arch/riscv/boot/entry.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __ENTRY_H__
> +#define __ENTRY_H__
> +
> +#include <common.h>
> +
> +void __noreturn barebox_non_pbl_start(unsigned long membase,
> + unsigned long memsize,
> + void *boarddata);
> +
> +void __noreturn barebox_pbl_start(unsigned long membase,
> + unsigned long memsize,
> + void *boarddata);
> +
> +#endif
> diff --git a/arch/riscv/boot/entry_ll.S b/arch/riscv/boot/entry_ll.S
> new file mode 100644
> index 000000000000..7011fefad865
> --- /dev/null
> +++ b/arch/riscv/boot/entry_ll.S
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#include <linux/linkage.h>
> +#include <asm/sections.h>
> +
> +/*
> + * a0: memory base
> + * a1: memory size
> + * a2: board data
> + * a3: new value for SP
> + */
> +.section .text.__barebox_riscv_entry
> +ENTRY(__barebox_riscv_entry)
> + move sp, a3
> + j barebox_pbl_start
> +ENDPROC(__barebox_riscv_entry)
> diff --git a/arch/riscv/boot/start.c b/arch/riscv/boot/start.c
> new file mode 100644
> index 000000000000..7fcbafcc0758
> --- /dev/null
> +++ b/arch/riscv/boot/start.c
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +// SPDX-FileCopyrightText: 2010 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
> +
> +#define pr_fmt(fmt) "start.c: " fmt
> +
> +#include <common.h>
> +#include <init.h>
> +#include <linux/sizes.h>
> +#include <of.h>
> +#include <asm/barebox-riscv.h>
> +#include <asm-generic/memory_layout.h>
> +#include <asm/sections.h>
> +#include <asm/unaligned.h>
> +#include <linux/kasan.h>
> +#include <memory.h>
> +#include <uncompress.h>
> +#include <malloc.h>
> +
> +#include <debug_ll.h>
> +
> +#include "entry.h"
> +
> +unsigned long riscv_stack_top;
> +static unsigned long riscv_barebox_size;
> +static unsigned long riscv_endmem;
> +static void *barebox_boarddata;
> +static unsigned long barebox_boarddata_size;
> +
> +static bool blob_is_fdt(const void *blob)
> +{
> + return get_unaligned_be32(blob) == FDT_MAGIC;
> +}
> +
> +static bool blob_is_compressed_fdt(const void *blob)
> +{
> + const struct barebox_riscv_boarddata_compressed_dtb *dtb = blob;
> +
> + return dtb->magic == BAREBOX_RISCV_BOARDDATA_COMPRESSED_DTB_MAGIC;
> +}
> +
> +void *barebox_riscv_boot_dtb(void)
> +{
> + void *dtb;
> + void *data;
> + int ret;
> + struct barebox_riscv_boarddata_compressed_dtb *compressed_dtb;
> + static void *boot_dtb;
> +
> + if (boot_dtb)
> + return boot_dtb;
> +
> + if (barebox_boarddata && blob_is_fdt(barebox_boarddata)) {
> + pr_debug("%s: using barebox_boarddata\n", __func__);
> + return barebox_boarddata;
> + }
> +
> + if (!IS_ENABLED(CONFIG_USE_COMPRESSED_DTB) || !barebox_boarddata
> + || !blob_is_compressed_fdt(barebox_boarddata))
> + return NULL;
> +
> + compressed_dtb = barebox_boarddata;
> +
> + pr_debug("%s: using compressed_dtb\n", __func__);
> +
> + dtb = malloc(compressed_dtb->datalen_uncompressed);
> + if (!dtb)
> + return NULL;
> +
> + data = compressed_dtb + 1;
> +
> + ret = uncompress(data, compressed_dtb->datalen, NULL, NULL, dtb, NULL, NULL);
> + if (ret) {
> + pr_err("uncompressing dtb failed\n");
> + free(dtb);
> + return NULL;
> + }
> +
> + boot_dtb = dtb;
> +
> + return boot_dtb;
> +}
> +
> +static inline unsigned long riscv_mem_boarddata(unsigned long membase,
> + unsigned long endmem,
> + unsigned long size)
> +{
> + unsigned long mem;
> +
> + mem = riscv_mem_barebox_image(membase, endmem, riscv_barebox_size);
> + mem -= ALIGN(size, 64);
> +
> + return mem;
> +}
> +
> +unsigned long riscv_mem_ramoops_get(void)
> +{
> + return riscv_mem_ramoops(0, riscv_stack_top);
> +}
> +EXPORT_SYMBOL_GPL(riscv_mem_ramoops_get);
> +
> +unsigned long riscv_mem_endmem_get(void)
> +{
> + return riscv_endmem;
> +}
> +EXPORT_SYMBOL_GPL(riscv_mem_endmem_get);
> +
> +static int barebox_memory_areas_init(void)
> +{
> + if(barebox_boarddata)
> + request_sdram_region("board data", (unsigned long)barebox_boarddata,
> + barebox_boarddata_size);
> +
> + return 0;
> +}
> +device_initcall(barebox_memory_areas_init);
> +
> +/*
> + * First function in the uncompressed image. We get here from
> + * the pbl. The stack already has been set up by the pbl.
> + */
> +__noreturn __no_sanitize_address __section(.text_entry)
> +void barebox_non_pbl_start(unsigned long membase, unsigned long memsize, void *boarddata)
> +{
> + unsigned long endmem = membase + memsize;
> + unsigned long malloc_start, malloc_end;
> + unsigned long barebox_size = barebox_image_size + MAX_BSS_SIZE;
> + unsigned long barebox_base = riscv_mem_barebox_image(membase, endmem, barebox_size);
> +
> + relocate_to_current_adr();
> +
> + setup_c();
> +
> + barrier();
> +
> + pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize);
> +
> + riscv_endmem = endmem;
> + riscv_stack_top = riscv_mem_stack_top(membase, endmem);
> + riscv_barebox_size = barebox_size;
> + malloc_end = barebox_base;
> +
> + if (boarddata) {
> + uint32_t totalsize = 0;
> + const char *name;
> +
> + if (blob_is_fdt(boarddata)) {
> + totalsize = get_unaligned_be32(boarddata + 4);
> + name = "DTB";
> + } else if (blob_is_compressed_fdt(boarddata)) {
> + struct barebox_riscv_boarddata_compressed_dtb *bd = boarddata;
> + totalsize = bd->datalen + sizeof(*bd);
> + name = "Compressed DTB";
> + }
> +
> + if (totalsize) {
> + unsigned long mem = riscv_mem_boarddata(membase, endmem, totalsize);
> + pr_debug("found %s in boarddata, copying to 0x%08lx\n", name, mem);
> + barebox_boarddata = memcpy((void *)mem, boarddata, totalsize);
> + barebox_boarddata_size = totalsize;
> + malloc_end = mem;
> + }
> + }
> +
> + /*
> + * Maximum malloc space is the Kconfig value if given
> + * or 1GB.
> + */
> + if (MALLOC_SIZE > 0) {
> + malloc_start = malloc_end - MALLOC_SIZE;
> + if (malloc_start < membase)
> + malloc_start = membase;
> + } else {
> + malloc_start = malloc_end - (malloc_end - membase) / 2;
> + if (malloc_end - malloc_start > SZ_1G)
> + malloc_start = malloc_end - SZ_1G;
> + }
> +
> + pr_debug("initializing malloc pool at 0x%08lx (size 0x%08lx)\n",
> + malloc_start, malloc_end - malloc_start);
> +
> + mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1);
> +
> + pr_debug("starting barebox...\n");
> +
> + start_barebox();
> +}
> +
> +void start(unsigned long membase, unsigned long memsize, void *boarddata);
> +/*
> + * First function in the uncompressed image. We get here from
> + * the pbl. The stack already has been set up by the pbl.
> + */
> +void __no_sanitize_address __section(.text_entry) start(unsigned long membase,
> + unsigned long memsize, void *boarddata)
> +{
> + barebox_non_pbl_start(membase, memsize, boarddata);
> +}
> diff --git a/arch/riscv/boot/uncompress.c b/arch/riscv/boot/uncompress.c
> new file mode 100644
> index 000000000000..cf268bece1bf
> --- /dev/null
> +++ b/arch/riscv/boot/uncompress.c
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +// SPDX-FileCopyrightText: 2010-2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
> +// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> +
> +/* uncompress.c - uncompressor code for self extracing pbl image */
> +
> +#define pr_fmt(fmt) "uncompress.c: " fmt
> +
> +#include <common.h>
> +#include <init.h>
> +#include <linux/sizes.h>
> +#include <pbl.h>
> +#include <asm/barebox-riscv.h>
> +#include <asm-generic/memory_layout.h>
> +#include <asm/sections.h>
> +#include <asm/unaligned.h>
> +
> +#include <debug_ll.h>
> +
> +#include "entry.h"
> +
> +unsigned long free_mem_ptr;
> +unsigned long free_mem_end_ptr;
> +
> +extern unsigned char input_data[];
> +extern unsigned char input_data_end[];
> +
> +void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
> + void *fdt)
> +{
> + uint32_t pg_len, uncompressed_len;
> + void __noreturn (*barebox)(unsigned long, unsigned long, void *);
> + unsigned long endmem = membase + memsize;
> + unsigned long barebox_base;
> + void *pg_start, *pg_end;
> + unsigned long pc = get_pc();
> +
> + pg_start = input_data + get_runtime_offset();
> + pg_end = input_data_end + get_runtime_offset();
> +
> + /*
> + * If we run from inside the memory just relocate the binary
> + * to the current address. Otherwise it may be a readonly location.
> + * Copy and relocate to the start of the memory in this case.
> + */
> + if (pc > membase && pc - membase < memsize)
> + relocate_to_current_adr();
> + else
> + relocate_to_adr(membase);
> +
> + pg_len = pg_end - pg_start;
> + uncompressed_len = get_unaligned((const u32 *)(pg_start + pg_len - 4));
> +
> + barebox_base = riscv_mem_barebox_image(membase, endmem,
> + uncompressed_len + MAX_BSS_SIZE);
> +
> + setup_c();
> +
> + pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize);
> +
> + free_mem_ptr = riscv_mem_early_malloc(membase, endmem);
> + free_mem_end_ptr = riscv_mem_early_malloc_end(membase, endmem);
> +
> + pr_debug("uncompressing barebox binary at 0x%p (size 0x%08x) to 0x%08lx (uncompressed size: 0x%08x)\n",
> + pg_start, pg_len, barebox_base, uncompressed_len);
> +
> + pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len);
> +
> + barebox = (void *)barebox_base;
> +
> + pr_debug("jumping to uncompressed image at 0x%p. dtb=0x%p\n", barebox, fdt);
> +
> + barebox(membase, memsize, fdt);
> +}
> diff --git a/arch/riscv/include/asm/barebox-riscv.h b/arch/riscv/include/asm/barebox-riscv.h
> new file mode 100644
> index 000000000000..05e076c4868b
> --- /dev/null
> +++ b/arch/riscv/include/asm/barebox-riscv.h
> @@ -0,0 +1,101 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Marius Groeger <mgroeger@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
> + * Alex Zuepke <azu@sysgo.de>
> + */
> +
> +#ifndef _BAREBOX_RISCV_H_
> +#define _BAREBOX_RISCV_H_
> +
> +#include <linux/sizes.h>
> +#include <asm-generic/memory_layout.h>
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/compiler.h>
> +#include <asm/sections.h>
> +
> +unsigned long get_runtime_offset(void);
> +
> +void setup_c(void);
> +void relocate_to_current_adr(void);
> +void relocate_to_adr(unsigned long target);
> +void __noreturn barebox_riscv_entry(unsigned long membase, unsigned long memsize, void *boarddata);
> +
> +unsigned long riscv_mem_ramoops_get(void);
> +unsigned long riscv_mem_endmem_get(void);
> +
> +struct barebox_riscv_boarddata_compressed_dtb {
> +#define BAREBOX_RISCV_BOARDDATA_COMPRESSED_DTB_MAGIC 0x7b66bcbd
> + u32 magic;
> + u32 datalen;
> + u32 datalen_uncompressed;
> +};
> +
> +void *barebox_riscv_boot_dtb(void);
> +
> +static inline unsigned long riscv_mem_stack_top(unsigned long membase,
> + unsigned long endmem)
> +{
> + return endmem - SZ_2M;
> +}
> +
> +static inline unsigned long riscv_mem_stack(unsigned long membase,
> + unsigned long endmem)
> +{
> + return riscv_mem_stack_top(membase, endmem) - STACK_SIZE;
> +}
> +
> +static inline unsigned long riscv_mem_early_malloc(unsigned long membase,
> + unsigned long endmem)
> +{
> + return riscv_mem_stack(membase, endmem) - SZ_128K;
> +}
> +
> +static inline unsigned long riscv_mem_early_malloc_end(unsigned long membase,
> + unsigned long endmem)
> +{
> + return riscv_mem_stack(membase, endmem);
> +}
> +
> +static inline unsigned long riscv_mem_ramoops(unsigned long membase,
> + unsigned long endmem)
> +{
> + endmem = riscv_mem_stack(membase, endmem);
> +#ifdef CONFIG_FS_PSTORE_RAMOOPS
> + endmem -= CONFIG_FS_PSTORE_RAMOOPS_SIZE;
> + endmem = ALIGN_DOWN(endmem, SZ_4K);
> +#endif
> +
> + return endmem;
> +}
> +
> +static inline unsigned long riscv_mem_barebox_image(unsigned long membase,
> + unsigned long endmem,
> + unsigned long size)
> +{
> + endmem = riscv_mem_ramoops(membase, endmem);
> +
> + return ALIGN_DOWN(endmem - size, SZ_1M);
> +}
> +
> +#define ENTRY_FUNCTION(name, arg0, arg1, arg2) \
> + void name (ulong a0, ulong a1, ulong a2); \
> + void __section(.text_head_entry_##name) name (ulong a0, ulong a1, ulong a2)
> +
> +/*
> + * When using compressed images in conjunction with relocatable images
> + * the PBL code must pick a suitable place where to uncompress the barebox
> + * image. For doing this the PBL code must know the size of the final
> + * image including the BSS segment. The BSS size is unknown to the PBL
> + * code, so define a maximum BSS size here.
> + */
> +#define MAX_BSS_SIZE SZ_1M
> +
> +#define barebox_image_size (__image_end - __image_start)
> +
> +#endif /* _BAREBOX_RISCV_H_ */
> diff --git a/arch/riscv/include/asm/common.h b/arch/riscv/include/asm/common.h
> index bc8a17e30bc5..a0982c548fe1 100644
> --- a/arch/riscv/include/asm/common.h
> +++ b/arch/riscv/include/asm/common.h
> @@ -1,6 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/* SPDX-FileCopyrightText: Copyright (c) 2021 Ahmad Fatoum, Pengutronix */
> #ifndef ASM_RISCV_COMMON_H
> #define ASM_RISCV_COMMON_H
>
> -/* nothing special yet */
> +#include <linux/compiler.h>
> +
> +static __always_inline unsigned long get_pc(void)
> +{
> +label:
> + return (unsigned long)&&label;
> +}
>
> #endif /* ASM_RISCV_COMMON_H */
> diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
> index 7134fa05820a..adb8ec8f6ece 100644
> --- a/arch/riscv/include/asm/elf.h
> +++ b/arch/riscv/include/asm/elf.h
> @@ -1,3 +1,4 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> #ifndef __ASM_RISCV_ELF_H__
> #define __ASM_RISCV_ELF_H__
>
> @@ -8,4 +9,10 @@
> #define ELF_CLASS ELFCLASS32
> #endif
>
> +/* Relocation types used by the dynamic linker */
> +#define R_RISCV_NONE 0
> +#define R_RISCV_32 1
> +#define R_RISCV_64 2
> +#define R_RISCV_RELATIVE 3
> +
> #endif /* __ASM_RISCV_ELF_H__ */
> diff --git a/arch/riscv/include/asm/linkage.h b/arch/riscv/include/asm/linkage.h
> index 9e88ba23cd2b..c6801294f388 100644
> --- a/arch/riscv/include/asm/linkage.h
> +++ b/arch/riscv/include/asm/linkage.h
> @@ -9,4 +9,8 @@
> #define __ALIGN .balign 4
> #define __ALIGN_STR ".balign 4"
>
> +#define ENDPROC(name) \
> + .type name, %function; \
> + END(name)
> +
> #endif /* _ASM_RISCV_LINKAGE_H */
> diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h
> index 2b8c5160388f..b5fbba8f165a 100644
> --- a/arch/riscv/include/asm/sections.h
> +++ b/arch/riscv/include/asm/sections.h
> @@ -1 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +#ifndef __ASM_SECTIONS_H
> +#define __ASM_SECTIONS_H
> +
> +#ifndef __ASSEMBLY__
> #include <asm-generic/sections.h>
> +#include <linux/types.h>
> +
> +extern char __rel_dyn_start[];
> +extern char __rel_dyn_end[];
> +extern char __dynsym_start[];
> +extern char __dynsym_end[];
> +
> +#endif
> +
> +#endif /* __ASM_SECTIONS_H */
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index b983ca8cdca0..5f57d9fcd2e2 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -1,5 +1,8 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> extra-y += barebox.lds
>
> obj-y += riscv_timer.o
> +obj-pbl-y += sections.o setupc.o reloc.o sections.o runtime-offset.o
> obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o longjmp.o
> obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o
> diff --git a/arch/riscv/lib/barebox.lds.S b/arch/riscv/lib/barebox.lds.S
> index 342769890bb0..c8a331c577cf 100644
> --- a/arch/riscv/lib/barebox.lds.S
> +++ b/arch/riscv/lib/barebox.lds.S
> @@ -43,10 +43,18 @@ SECTIONS
>
> .barebox_imd : { BAREBOX_IMD }
>
> - . = ALIGN(8);
> - .got : { *(.got*) }
> + /DISCARD/ : { *(.rela.plt*) }
> + .rela.dyn : {
> + __rel_dyn_start = .;
> + *(.rel*)
> + __rel_dyn_end = .;
> + }
>
> - .rela.dyn : { *(.rela*) }
> + .dynsym : {
> + __dynsym_start = .;
> + *(.dynsym)
> + __dynsym_end = .;
> + }
>
> _edata = .;
> . = ALIGN(8);
> diff --git a/arch/riscv/lib/pbl.lds.S b/arch/riscv/lib/pbl.lds.S
> new file mode 100644
> index 000000000000..33caab7b1024
> --- /dev/null
> +++ b/arch/riscv/lib/pbl.lds.S
> @@ -0,0 +1,83 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/* SPDX-FileCopyrightText: 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix */
> +
> +#include <linux/sizes.h>
> +#include <asm-generic/barebox.lds.h>
> +#include <asm-generic/memory_layout.h>
> +
> +OUTPUT_ARCH(riscv)
> +SECTIONS
> +{
> + . = 0x0;
> +
> + .image_start : { *(.__image_start) }
> +
> + . = ALIGN(4);
> + ._text : { *(._text) }
> + .text :
> + {
> + _stext = .;
> + *(.text_head_entry*)
> + __bare_init_start = .;
> + *(.text_bare_init*)
> + __bare_init_end = .;
> + *(.text*)
> + }
> +
> + /* Discard unwind if enable in barebox */
> + /DISCARD/ : { *(.ARM.ex*) }
> +
> + BAREBOX_BARE_INIT_SIZE
> + BAREBOX_PBL_SIZE
> +
> + . = ALIGN(4);
> + .rodata : { *(.rodata*) }
> +
> + .barebox_imd : { BAREBOX_IMD }
> +
> + _etext = .; /* End of text and rodata section */
> +
> + .data : { *(.data*) }
> +
> + __shasum_start = .;
> + .shasum : {
> + KEEP(*(.shasum))
> + }
> + __shasum_end = .;
> +
> + /DISCARD/ : { *(.rela.plt*) }
> + .rela.dyn : {
> + __rel_dyn_start = .;
> + *(.rela*)
> + __rel_dyn_end = .;
> + }
> +
> + .dynsym : {
> + __dynsym_start = .;
> + *(.dynsym)
> + __dynsym_end = .;
> + }
> +
> + pbl_code_size = .;
> +
> + .__bss_start : { *(.__bss_start) }
> + .bss : { *(.bss*) }
> + .__bss_stop : { *(.__bss_stop) }
> + _end = .;
> +
> + pbl_memory_size = .;
> +
> + . = ALIGN(4);
> + __piggydata_start = .;
> + .piggydata : {
> + *(.piggydata)
> + }
> + __piggydata_end = .;
> +
> + .image_end : { KEEP(*(.__image_end)) }
> +
> + pbl_image_size = .;
> +
> + _barebox_image_size = __image_end;
> + _barebox_pbl_size = __bss_start;
> +}
> diff --git a/arch/riscv/lib/reloc.c b/arch/riscv/lib/reloc.c
> new file mode 100644
> index 000000000000..5e26c0be9c1c
> --- /dev/null
> +++ b/arch/riscv/lib/reloc.c
> @@ -0,0 +1,64 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +// SPDX-FileCopyrightText: Copyright (c) 2021 Ahmad Fatoum, Pengutronix
> +
> +#include <common.h>
> +#include <linux/linkage.h>
> +#include <asm/sections.h>
> +#include <asm/barebox-riscv.h>
> +#include <debug_ll.h>
> +#include <asm-generic/module.h>
> +
> +#include <elf.h>
> +
> +#if __riscv_xlen == 64
> +#define Elf_Rela Elf64_Rela
> +#define R_RISCV_ABSOLUTE R_RISCV_64
> +#define DYNSYM_ENTRY(dynsym, rela) dynsym[ELF_R_SYM(rela->r_info) * 3 + 1]
> +#elif __riscv_xlen == 32
> +#define Elf_Rela Elf32_Rela
> +#define R_RISCV_ABSOLUTE R_RISCV_32
> +#define DYNSYM_ENTRY(dynsym, rela) dynsym[ELF_R_SYM(rela->r_info) * 4 + 1]
> +#else
> +#error unknown riscv target
> +#endif
> +
> +#define RISC_R_TYPE(x) ((x) & 0xFF)
> +
> +void relocate_to_current_adr(void)
> +{
> + unsigned long offset;
> + unsigned long *dynsym;
> + void *dstart, *dend;
> + Elf_Rela *rela;
> +
> + /* Get offset between linked address and runtime address */
> + offset = get_runtime_offset();
> +
> + dstart = __rel_dyn_start + offset;
> + dend = __rel_dyn_end + offset;
> + dynsym = (void *)__dynsym_start + offset;
> +
> + for (rela = dstart; (void *)rela < dend; rela++) {
> + unsigned long *fixup;
> +
> + fixup = (unsigned long *)(rela->r_offset + offset);
> +
> + switch (RISC_R_TYPE(rela->r_info)) {
> + case R_RISCV_RELATIVE:
> + *fixup = rela->r_addend + offset;
> + break;
> + case R_RISCV_ABSOLUTE:
> + *fixup = DYNSYM_ENTRY(dynsym, rela) + rela->r_addend + offset;
> + break;
> + default:
> + putc_ll('>');
> + puthex_ll(rela->r_info);
> + putc_ll(' ');
> + puthex_ll(rela->r_offset);
> + putc_ll(' ');
> + puthex_ll(rela->r_addend);
> + putc_ll('\n');
> + panic("");
> + }
> + }
> +}
> diff --git a/arch/riscv/lib/runtime-offset.S b/arch/riscv/lib/runtime-offset.S
> new file mode 100644
> index 000000000000..f6a040628963
> --- /dev/null
> +++ b/arch/riscv/lib/runtime-offset.S
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/* SPDX-FileCopyrightText: Copyright (c) 2021 Ahmad Fatoum, Pengutronix */
> +#include <linux/linkage.h>
> +#include <asm/sections.h>
> +
> +.section ".text_bare_init","ax"
> +ENTRY(get_runtime_offset)
> + lla a0, _text /* load addr */
> + la a1, _text /* link addr */
> + sub a0, a0, a1
> + ret
> +ENDPROC(get_runtime_offset)
> diff --git a/arch/riscv/lib/sections.c b/arch/riscv/lib/sections.c
> new file mode 100644
> index 000000000000..e23a41dcf5d4
> --- /dev/null
> +++ b/arch/riscv/lib/sections.c
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#include <asm/sections.h>
> +#include <linux/types.h>
> +
> +char _text[0] __attribute__((section("._text")));
> +char __bss_start[0] __attribute__((section(".__bss_start")));
> +char __bss_stop[0] __attribute__((section(".__bss_stop")));
> +char __image_start[0] __attribute__((section(".__image_start")));
> +char __image_end[0] __attribute__((section(".__image_end")));
> diff --git a/arch/riscv/lib/setupc.S b/arch/riscv/lib/setupc.S
> new file mode 100644
> index 000000000000..6d824d00f7e0
> --- /dev/null
> +++ b/arch/riscv/lib/setupc.S
> @@ -0,0 +1,55 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/* SPDX-FileCopyrightText: Copyright (c) 2021 Ahmad Fatoum, Pengutronix */
> +
> +#include <linux/linkage.h>
> +#include <asm/sections.h>
> +#include <asm/asm.h>
> +
> +/*
> + * setup_c: clear bss
> + */
> +.section .text.setup_c
> +ENTRY(setup_c)
> + lla a0, __bss_start
> + li a1, 0
> + lla a2, __bss_stop
> + sub a2, a2, a0
> + j __memset
> +ENDPROC(setup_c)
> +
> +/*
> + * void relocate_to_adr(unsigned long targetadr)
> + *
> + * Copy binary to targetadr, relocate code and continue
> + * executing at new address.
> + */
> +.section .text.relocate_to_adr
> +ENTRY(relocate_to_adr)
> + /* a0: target address */
> + addi sp, sp, -SZREG * 2
> + lla a1, _text /* a1: source address */
> +
> + beq a0, a1, copied /* skip if already at new address */
This needs to be moved after spilling ra onto stack. Will fix in v2.
> +
> + lla a2, copied
> + sub a2, a2, a1
> + add a2, a2, a0
> + REG_S a2, (SZREG * 1)(sp)
> +
> + /* adjust return address */
> + sub ra, ra, a1 /* sub address where we are actually running */
> + add ra, ra, a0 /* add address where we are going to run */
> + REG_S ra, (SZREG * 2)(sp)
> +
> + lla a2, __bss_start
> + sub a2, a2, a1 /* a2: size */
> +
> + jal __memcpy
> +
> + REG_L a0, (SZREG * 1)(sp)
> + jr a0 /* jump to relocated address */
> +copied:
> + REG_L ra, (SZREG * 2)(sp)
> + addi sp, sp, SZREG * 2
> + j relocate_to_current_adr /* relocate binary */
> +ENDPROC(relocate_to_adr)
> diff --git a/scripts/.gitignore b/scripts/.gitignore
> index 7c9a3f55715f..9577d568edd0 100644
> --- a/scripts/.gitignore
> +++ b/scripts/.gitignore
> @@ -32,3 +32,4 @@ mips-relocs
> rsatoc
> stm32image
> mvebuimg
> +prelink-riscv
> diff --git a/scripts/Makefile b/scripts/Makefile
> index 744f4dd0e7e6..4dc70815b7e6 100644
> --- a/scripts/Makefile
> +++ b/scripts/Makefile
> @@ -24,6 +24,7 @@ hostprogs-always-$(CONFIG_ARCH_SOCFPGA) += socfpga_mkimage
> hostprogs-always-$(CONFIG_ARCH_MXS) += mxsimage mxsboot
> hostprogs-always-$(CONFIG_ARCH_LAYERSCAPE) += pblimage
> hostprogs-always-$(CONFIG_ARCH_STM32MP) += stm32image
> +hostprogs-always-$(CONFIG_RISCV) += prelink-riscv
> KBUILD_HOSTCFLAGS += -I$(srctree)/scripts/include/
> HOSTLDLIBS_mxsimage = `pkg-config --libs openssl`
> HOSTCFLAGS_omap3-usb-loader.o = `pkg-config --cflags libusb-1.0`
> diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
> index 2844d29be600..319ac19975ed 100644
> --- a/scripts/Makefile.lib
> +++ b/scripts/Makefile.lib
> @@ -247,6 +247,17 @@ $(obj)/%:: $(src)/%_shipped
> # and add target to extra-y so that we know we have to
> # read in the saved command line
>
> +# Prelinking
> +# ---------------------------------------------------------------------------
> +
> +ifneq ($(CONFIG_RISCV),)
> +quiet_cmd_prelink__ = PRELINK $@
> + cmd_prelink__ = $(objtree)/scripts/prelink-riscv $@
> +endif
> +
> +quiet_cmd_prelink__ ?=
> + cmd_prelink__ ?=
> +
> # Linking
> # ---------------------------------------------------------------------------
>
> diff --git a/scripts/prelink-riscv.c b/scripts/prelink-riscv.c
> new file mode 100644
> index 000000000000..c185d3981ca1
> --- /dev/null
> +++ b/scripts/prelink-riscv.c
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017 Andes Technology
> + * Chih-Mao Chen <cmchen@andestech.com>
> + *
> + * Statically process runtime relocations on RISC-V ELF images
> + * so that it can be directly executed when loaded at LMA
> + * without fixup. Both RV32 and RV64 are supported.
> + */
> +
> +#include <errno.h>
> +#include <stdbool.h>
> +#include <stdint.h>
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include <string.h>
> +
> +#include <elf.h>
> +#include <fcntl.h>
> +#include <sys/mman.h>
> +#include <sys/stat.h>
> +#include <sys/types.h>
> +#include <unistd.h>
> +#include "compiler.h"
> +
> +#ifndef EM_RISCV
> +#define EM_RISCV 243
> +#endif
> +
> +#ifndef R_RISCV_32
> +#define R_RISCV_32 1
> +#endif
> +
> +#ifndef R_RISCV_64
> +#define R_RISCV_64 2
> +#endif
> +
> +#ifndef R_RISCV_RELATIVE
> +#define R_RISCV_RELATIVE 3
> +#endif
> +
> +const char *argv0;
> +
> +#define die(fmt, ...) \
> + do { \
> + fprintf(stderr, "%s: " fmt "\n", argv0, ## __VA_ARGS__); \
> + exit(EXIT_FAILURE); \
> + } while (0)
> +
> +#define PRELINK_BYTEORDER le
> +#define PRELINK_INC_BITS 32
> +#include "prelink-riscv.inc"
> +#undef PRELINK_BYTEORDER
> +#undef PRELINK_INC_BITS
> +
> +#define PRELINK_BYTEORDER le
> +#define PRELINK_INC_BITS 64
> +#include "prelink-riscv.inc"
> +#undef PRELINK_BYTEORDER
> +#undef PRELINK_INC_BITS
> +
> +#define PRELINK_BYTEORDER be
> +#define PRELINK_INC_BITS 32
> +#include "prelink-riscv.inc"
> +#undef PRELINK_BYTEORDER
> +#undef PRELINK_INC_BITS
> +
> +#define PRELINK_BYTEORDER be
> +#define PRELINK_INC_BITS 64
> +#include "prelink-riscv.inc"
> +#undef PRELINK_BYTEORDER
> +#undef PRELINK_INC_BITS
> +
> +int main(int argc, const char *const *argv)
> +{
> + argv0 = argv[0];
> +
> + if (argc < 2) {
> + fprintf(stderr, "Usage: %s <u-boot>\n", argv0);
> + exit(EXIT_FAILURE);
> + }
> +
> + int fd = open(argv[1], O_RDWR, 0);
> +
> + if (fd < 0)
> + die("Cannot open %s: %s", argv[1], strerror(errno));
> +
> + struct stat st;
> +
> + if (fstat(fd, &st) < 0)
> + die("Cannot stat %s: %s", argv[1], strerror(errno));
> +
> + void *data =
> + mmap(0, st.st_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
> +
> + if (data == MAP_FAILED)
> + die("Cannot mmap %s: %s", argv[1], strerror(errno));
> +
> + close(fd);
> +
> + unsigned char *e_ident = (unsigned char *)data;
> +
> + if (memcmp(e_ident, ELFMAG, SELFMAG) != 0)
> + die("Invalid ELF file %s", argv[1]);
> +
> + bool is64 = e_ident[EI_CLASS] == ELFCLASS64;
> + bool isbe = e_ident[EI_DATA] == ELFDATA2MSB;
> +
> + if (is64) {
> + if (isbe)
> + prelink_be64(data);
> + else
> + prelink_le64(data);
> + } else {
> + if (isbe)
> + prelink_be32(data);
> + else
> + prelink_le32(data);
> + }
> +
> + return 0;
> +}
> diff --git a/scripts/prelink-riscv.inc b/scripts/prelink-riscv.inc
> new file mode 100644
> index 000000000000..f2b5467f5b3c
> --- /dev/null
> +++ b/scripts/prelink-riscv.inc
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017 Andes Technology
> + * Chih-Mao Chen <cmchen@andestech.com>
> + *
> + * Statically process runtime relocations on RISC-V ELF images
> + * so that it can be directly executed when loaded at LMA
> + * without fixup. Both RV32 and RV64 are supported.
> + */
> +
> +#define CONCAT_IMPL(x, y) x##y
> +#define CONCAT(x, y) CONCAT_IMPL(x, y)
> +#define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
> +
> +#define prelink_bonn CONCAT3(prelink_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
> +#define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t)
> +#define get_offset_bonn CONCAT3(get_offset_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
> +#define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
> +#define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
> +#define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
> +#define Elf_Sym CONCAT3(Elf, PRELINK_INC_BITS, _Sym)
> +#define Elf_Dyn CONCAT3(Elf, PRELINK_INC_BITS, _Dyn)
> +#define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
> +#define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
> +#define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
> +#define target16_to_cpu CONCAT(PRELINK_BYTEORDER, 16_to_cpu)
> +#define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
> +#define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
> +#define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
> +#define cpu_to_target32 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 32)
> +#define cpu_to_target64 CONCAT3(cpu_to_, PRELINK_BYTEORDER, 64)
> +
> +static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
> +{
> + Elf_Phdr *p;
> +
> + for (p = phdrs; p < phdrs + phnum; ++p)
> + if (targetnn_to_cpu(p->p_vaddr) <= addr && targetnn_to_cpu(p->p_vaddr) + targetnn_to_cpu(p->p_memsz) > addr)
> + return data + targetnn_to_cpu(p->p_offset) + (addr - targetnn_to_cpu(p->p_vaddr));
> +
> + return NULL;
> +}
> +
> +static void prelink_bonn(void *data)
> +{
> + Elf_Ehdr *ehdr = data;
> + Elf_Phdr *p;
> + Elf_Dyn *dyn;
> + Elf_Rela *r;
> +
> + if (target16_to_cpu(ehdr->e_machine) != EM_RISCV)
> + die("Machine type is not RISC-V");
> +
> + Elf_Phdr *phdrs = data + targetnn_to_cpu(ehdr->e_phoff);
> +
> + Elf_Dyn *dyns = NULL;
> + for (p = phdrs; p < phdrs + target16_to_cpu(ehdr->e_phnum); ++p) {
> + if (target32_to_cpu(p->p_type) == PT_DYNAMIC) {
> + dyns = data + targetnn_to_cpu(p->p_offset);
> + break;
> + }
> + }
> +
> + if (dyns == NULL)
> + die("No dynamic section found");
> +
> + Elf_Rela *rela_dyn = NULL;
> + size_t rela_count = 0;
> + Elf_Sym *dynsym = NULL;
> + for (dyn = dyns;; ++dyn) {
> + if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
> + break;
> + else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
> + rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
> + else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
> + rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
> + else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
> + dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
> +
> + }
> +
> + if (rela_dyn == NULL)
> + die("No .rela.dyn found");
> +
> + if (dynsym == NULL)
> + die("No .dynsym found");
> +
> + for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
> + void* buf = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), targetnn_to_cpu(r->r_offset));
> +
> + if (buf == NULL)
> + continue;
> +
> + if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
> + *((uintnn_t*) buf) = r->r_addend;
> + else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
> + *((uint32_t*) buf) = cpu_to_target32(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
> + else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
> + *((uint64_t*) buf) = cpu_to_target64(targetnn_to_cpu(dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value) + targetnn_to_cpu(r->r_addend));
> + }
> +}
> +
> +#undef prelink_bonn
> +#undef uintnn_t
> +#undef get_offset_bonn
> +#undef Elf_Ehdr
> +#undef Elf_Phdr
> +#undef Elf_Rela
> +#undef Elf_Sym
> +#undef Elf_Dyn
> +#undef Elf_Addr
> +#undef ELF_R_TYPE
> +#undef ELF_R_SYM
> +#undef target16_to_cpu
> +#undef target32_to_cpu
> +#undef target64_to_cpu
> +#undef targetnn_to_cpu
> +#undef cpu_to_target32
> +#undef cpu_to_target64
> +
> +#undef CONCAT_IMPL
> +#undef CONCAT
> +#undef CONCAT3
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 14/20] RISC-V: erizo: migrate to PBL
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (12 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 13/20] RISC-V: implement PBL and relocation support Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-15 8:43 ` MIPS RELOCATABLE: " Antony Pavlov
2021-03-14 12:27 ` [PATCH 15/20] RISC-V: support symbol names in barebox image Ahmad Fatoum
` (6 subsequent siblings)
20 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
We now have everything in place to migrate erizo to PBL.
As currently, this is the only board, we can drop all non-PBL support
in the same go.
The board still throws TLSF errors on startup, but that was the case
before the rework as well. Tested with qemu as described in the docs.
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
I assume some memory corruption is happening due to the minimal malloc
area size? It doesn't happen with dlmalloc. It doesn't happen on riscv
virt added later on, so I will likely not pursue this further.
---
Documentation/boards/riscv.rst | 13 +++--
Makefile | 1 +
arch/riscv/Kconfig | 15 ++---
arch/riscv/Makefile | 25 +++-----
arch/riscv/boards/erizo/Makefile | 4 +-
arch/riscv/boards/erizo/board.c | 25 --------
arch/riscv/boards/erizo/lowlevel.c | 37 ++++--------
arch/riscv/boards/erizo/start.S | 68 ----------------------
arch/riscv/configs/erizo_generic_defconfig | 5 --
arch/riscv/dts/Makefile | 9 +--
arch/riscv/lib/Makefile | 2 +-
arch/riscv/lib/barebox.lds.S | 36 ++++++++----
arch/riscv/lib/dtb.c | 26 +++++++++
common/Kconfig | 4 +-
images/Makefile | 4 ++
images/Makefile.erizo | 12 ++++
pbl/Kconfig | 2 +-
17 files changed, 107 insertions(+), 181 deletions(-)
delete mode 100644 arch/riscv/boards/erizo/board.c
delete mode 100644 arch/riscv/boards/erizo/start.S
create mode 100644 arch/riscv/lib/dtb.c
create mode 100644 images/Makefile.erizo
diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst
index c7fa52aadbee..a1f7e30531ee 100644
--- a/Documentation/boards/riscv.rst
+++ b/Documentation/boards/riscv.rst
@@ -1,8 +1,11 @@
RISC-V
======
-Running RISC-V barebox on qemu
-------------------------------
+Erizo
+-----
+
+Running on qemu
+~~~~~~~~~~~~~~~
Obtain RISC-V GCC/Newlib Toolchain,
see https://github.com/riscv/riscv-tools/blob/master/README.md
@@ -44,7 +47,7 @@ Next compile barebox::
Run barebox::
$ <path to riscv-qemu source>/riscv32-softmmu/qemu-system-riscv32 \
- -nographic -M erizo -bios <path to barebox sources >/barebox.bin \
+ -nographic -M erizo -bios ./images/barebox-erizo-generic.img \
-serial stdio -monitor none -trace file=/dev/null
Switch to console [cs0]
@@ -59,8 +62,8 @@ Run barebox::
barebox:/
-Running RISC-V barebox on DE0-Nano FPGA board
----------------------------------------------
+Running on DE0-Nano FPGA board
+------------------------------
See https://github.com/open-design/riscv-soc-cores/ for instructions
on DE0-Nano bitstream generation and loading.
diff --git a/Makefile b/Makefile
index 6d44314f0a7e..4cc7bef2bd42 100644
--- a/Makefile
+++ b/Makefile
@@ -776,6 +776,7 @@ define rule_barebox__
$(if $(CONFIG_KALLSYMS),,+$(call cmd,barebox_version))
$(call cmd,barebox__)
$(Q)echo 'cmd_$@ := $(cmd_barebox__)' > $(@D)/.$(@F).cmd
+ $(call cmd,prelink__)
$(call cmd,sysmap)
endef
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b1b24f2e5764..4a2a547a7b35 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -1,14 +1,16 @@
config RISCV
def_bool y
select GENERIC_FIND_NEXT_BIT
- select HAVE_CONFIGURABLE_MEMORY_LAYOUT
- select HAVE_CONFIGURABLE_TEXT_BASE
select GPIOLIB
select OFTREE
+ select OFDEVICE
select COMMON_CLK
select COMMON_CLK_OF_PROVIDER
select CLKDEV_LOOKUP
select HAS_DMA
+ select HAVE_PBL_IMAGE
+ select HAVE_PBL_MULTI_IMAGES
+ select HAVE_IMAGE_COMPRESSION
config ARCH_TEXT_BASE
hex
@@ -24,6 +26,7 @@ config MACH_ERIZO
bool "erizo family"
select HAS_DEBUG_LL
select HAS_NMON
+ select USE_COMPRESSED_DTB
endchoice
@@ -56,14 +59,6 @@ config 32BIT
endchoice
-config BUILTIN_DTB
- bool "link a DTB into the barebox image"
- depends on OFTREE
-
-config BUILTIN_DTB_NAME
- string "DTB to build into the barebox image"
- depends on BUILTIN_DTB
-
source "arch/riscv/mach-erizo/Kconfig"
endmenu
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index df2b5bb681a4..f59e8b39a572 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -3,21 +3,23 @@ KBUILD_DEFCONFIG := erizo_generic_defconfig
KBUILD_CPPFLAGS += -fno-strict-aliasing
ifeq ($(CONFIG_ARCH_RV32I),y)
- cflags-y += -march=rv32im -mabi=ilp32
- riscv-ldflags-y += -melf32lriscv
+ riscv-cflags-y := -march=rv32im -mabi=ilp32
+ riscv-ldflags-y := -melf32lriscv
endif
-cflags-y += -fno-pic -Wstrict-prototypes -mcmodel=medany
+riscv-cflags-y += -Wstrict-prototypes -mcmodel=medany -fpic
+riscv-ldflags-y += -pie -static
+PBL_CPPFLAGS += $(riscv-cflags-y)
+LDFLAGS_pbl += $(riscv-ldflags-y)
+
+cflags-y += $(riscv-cflags-y)
LDFLAGS_barebox += -nostdlib
machine-$(CONFIG_MACH_ERIZO) := erizo
LDFLAGS_barebox += $(riscv-ldflags-y)
-TEXT_BASE = $(CONFIG_TEXT_BASE)
-KBUILD_CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
-
ifndef CONFIG_MODULES
# Add cleanup flags
KBUILD_CPPFLAGS += -fdata-sections -ffunction-sections
@@ -54,13 +56,4 @@ lds-y := arch/riscv/lib/barebox.lds
CLEAN_FILES += arch/riscv/lib/barebox.lds
-ifeq ($(CONFIG_MACH_ERIZO),y)
-KBUILD_IMAGE := barebox.erizo.nmon
-endif
-
-quiet_cmd_erizo_nmon_image = MKIMAGE $@
- cmd_erizo_nmon_image = $(srctree)/scripts/erizo-nmon-image $< $@ || \
- echo "WARNING: Couldn't create erizo nmon image due to previous errors."
-
-barebox.erizo.nmon: $(KBUILD_BINARY) FORCE
- $(call if_changed,erizo_nmon_image)
+KBUILD_IMAGE := $(KBUILD_BINARY)
diff --git a/arch/riscv/boards/erizo/Makefile b/arch/riscv/boards/erizo/Makefile
index 72b9a13ba73f..3d217ffe0b93 100644
--- a/arch/riscv/boards/erizo/Makefile
+++ b/arch/riscv/boards/erizo/Makefile
@@ -1,5 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-obj-y += lowlevel.o
-obj-y += start.o
-obj-y += board.o
+pbl-y += lowlevel.o
diff --git a/arch/riscv/boards/erizo/board.c b/arch/riscv/boards/erizo/board.c
deleted file mode 100644
index b9b68fc7f254..000000000000
--- a/arch/riscv/boards/erizo/board.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2016, 2018 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <common.h>
-#include <init.h>
-#include <of.h>
-
-extern char __dtb_start[];
-
-static int of_riscv_init(void)
-{
- barebox_register_fdt(__dtb_start);
-
- return 0;
-}
-core_initcall(of_riscv_init);
diff --git a/arch/riscv/boards/erizo/lowlevel.c b/arch/riscv/boards/erizo/lowlevel.c
index f9c640c1123f..d9edb530b746 100644
--- a/arch/riscv/boards/erizo/lowlevel.c
+++ b/arch/riscv/boards/erizo/lowlevel.c
@@ -1,35 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * This file is part of barebox.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
#include <common.h>
-#include <memory.h>
-#include <asm-generic/memory_layout.h>
-#include <asm/sections.h>
+#include <asm/barebox-riscv.h>
+#include <debug_ll.h>
-void main_entry(void);
-
-/**
- * Called plainly from assembler code
- *
- * @note The C environment isn't initialized yet
- */
-void main_entry(void)
+ENTRY_FUNCTION(start_erizo_generic, a0, a1, a2)
{
- /* clear the BSS first */
- memset(__bss_start, 0x00, __bss_stop - __bss_start);
+ extern char __dtb_z_erizo_generic_start[];
+
+ debug_ll_ns16550_init();
+ putc_ll('>');
- mem_malloc_init((void *)MALLOC_BASE,
- (void *)(MALLOC_BASE + MALLOC_SIZE - 1));
+ /* On POR, we are running from read-only memory here. */
- start_barebox();
+ barebox_riscv_entry(0x80000000, SZ_8M,
+ __dtb_z_erizo_generic_start + get_runtime_offset());
}
diff --git a/arch/riscv/boards/erizo/start.S b/arch/riscv/boards/erizo/start.S
deleted file mode 100644
index d1dbe48b7bd6..000000000000
--- a/arch/riscv/boards/erizo/start.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Startup Code for RISC-V CPU
- *
- * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
- *
- * based on coreboot/src/arch/riscv/bootblock.S
- * and barebox/arch/mips/boot/start.S
- *
- * This file is part of barebox.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <asm-generic/memory_layout.h>
-
-#include "mach/debug_ll.h"
-
-#include "asm/riscv_nmon.h"
-
- .text
- .section ".text_entry"
- .align 2
-
-.globl _start
-_start:
- debug_ll_ns16550_init
-
- riscv_nmon
-
- li sp, STACK_BASE + STACK_SIZE
-
- /* copy barebox to link location */
-
- la a0, _start /* a0 <- _start actual address */
- li a1, CONFIG_TEXT_BASE /* a1 <- _start link address */
-
- beq a0, a1, main_entry
-
- la a2, __bss_start
-
-#define LONGSIZE 4
-
-copy_loop:
- /* copy from source address [a0] */
- lw t0, LONGSIZE * 0(a0)
- lw t1, LONGSIZE * 1(a0)
- lw t2, LONGSIZE * 2(a0)
- lw t3, LONGSIZE * 3(a0)
- /* copy to target address [a1] */
- sw t0, LONGSIZE * 0(a1)
- sw t1, LONGSIZE * 1(a1)
- sw t2, LONGSIZE * 2(a1)
- sw t3, LONGSIZE * 3(a1)
- addi a0, a0, LONGSIZE * 4
- addi a1, a1, LONGSIZE * 4
- bgeu a2, a0, copy_loop
-
- /* Alas! At the moment I can't load main_entry __link__ address
- into a0 with la. Use CONFIG_TEXT_BASE instead. This solution
- leads to extra cycles for repeat sp initialization. */
-
- li a0, CONFIG_TEXT_BASE
- jalr a0
diff --git a/arch/riscv/configs/erizo_generic_defconfig b/arch/riscv/configs/erizo_generic_defconfig
index 2ea1e46cc960..839b652ab53d 100644
--- a/arch/riscv/configs/erizo_generic_defconfig
+++ b/arch/riscv/configs/erizo_generic_defconfig
@@ -1,9 +1,5 @@
# CONFIG_GLOBALVAR is not set
-CONFIG_TEXT_BASE=0x80000000
-CONFIG_MEMORY_LAYOUT_FIXED=y
-CONFIG_STACK_BASE=0x800e0000
CONFIG_STACK_SIZE=0x20000
-CONFIG_MALLOC_BASE=0x80100000
CONFIG_MALLOC_SIZE=0x100000
CONFIG_MALLOC_TLSF=y
CONFIG_PANIC_HANG=y
@@ -36,7 +32,6 @@ CONFIG_CMD_SPI=y
CONFIG_CMD_OF_DUMP=y
CONFIG_CMD_TIME=y
CONFIG_CMD_DHRYSTONE=y
-CONFIG_OFDEVICE=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SPI_GPIO=y
CONFIG_I2C=y
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 6bd4e5a9250c..4041c34e0c45 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,12 +1,9 @@
-BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
-ifneq ($(BUILTIN_DTB),)
-obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
-endif
-
-obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o
+# SPDX-License-Identifier: GPL-2.0
# just to build a built-in.o. Otherwise compilation fails when no devicetree is
# created.
obj- += dummy.o
+pbl-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o
+
clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 5f57d9fcd2e2..a9bf68bca597 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -2,7 +2,7 @@
extra-y += barebox.lds
-obj-y += riscv_timer.o
+obj-y += riscv_timer.o dtb.o
obj-pbl-y += sections.o setupc.o reloc.o sections.o runtime-offset.o
obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o longjmp.o
obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o
diff --git a/arch/riscv/lib/barebox.lds.S b/arch/riscv/lib/barebox.lds.S
index c8a331c577cf..562ad5dc6662 100644
--- a/arch/riscv/lib/barebox.lds.S
+++ b/arch/riscv/lib/barebox.lds.S
@@ -14,22 +14,30 @@
#include <asm-generic/barebox.lds.h>
OUTPUT_ARCH(riscv)
-ENTRY(_start)
+ENTRY(start)
SECTIONS
{
- . = TEXT_BASE;
+ . = 0x0;
- . = ALIGN(8);
+ .image_start : { *(.__image_start) }
+
+ . = ALIGN(4);
+ ._text : { *(._text) }
.text :
{
_stext = .;
- _start = .;
- KEEP(*(.text_entry*))
- _text = .;
+ *(.text_entry*)
+ __bare_init_start = .;
+ *(.text_bare_init*)
+ __bare_init_end = .;
+ __exceptions_start = .;
+ KEEP(*(.text_exceptions*))
+ __exceptions_stop = .;
*(.text*)
}
+ BAREBOX_BARE_INIT_SIZE
- . = ALIGN(8);
+ . = ALIGN(4);
.rodata : {
*(.rodata*)
RO_DATA_SECTION
@@ -38,7 +46,7 @@ SECTIONS
_etext = .; /* End of text and rodata section */
_sdata = .;
- . = ALIGN(8);
+ . = ALIGN(4);
.data : { *(.data*) }
.barebox_imd : { BAREBOX_IMD }
@@ -57,9 +65,13 @@ SECTIONS
}
_edata = .;
- . = ALIGN(8);
- __bss_start = .;
- .bss : { *(.bss*) *(.sbss*) }
- __bss_stop = .;
+
+ .image_end : { *(.__image_end) }
+
+ . = ALIGN(4);
+ .__bss_start : { *(.__bss_start) }
+ .bss : { *(.bss*) }
+ .__bss_stop : { *(.__bss_stop) }
_end = .;
+ _barebox_image_size = __bss_start;
}
diff --git a/arch/riscv/lib/dtb.c b/arch/riscv/lib/dtb.c
new file mode 100644
index 000000000000..3a906a4f9f78
--- /dev/null
+++ b/arch/riscv/lib/dtb.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+#include <common.h>
+#include <init.h>
+#include <of.h>
+#include <asm/barebox-riscv.h>
+
+static int of_riscv_init(void)
+{
+ void *fdt;
+
+ /* See if we are provided a dtb in boarddata */
+ fdt = barebox_riscv_boot_dtb();
+ if (fdt)
+ pr_debug("using boarddata provided DTB\n");
+
+ if (!fdt) {
+ pr_debug("No DTB found\n");
+ return 0;
+ }
+
+ barebox_register_fdt(fdt);
+
+ return 0;
+}
+core_initcall(of_riscv_init);
diff --git a/common/Kconfig b/common/Kconfig
index 36207274f07f..37204fb40a44 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -44,7 +44,7 @@ config BLOCK_WRITE
config USE_COMPRESSED_DTB
bool
- depends on ARM
+ depends on ARM || RISCV
select UNCOMPRESS
select LZO_DECOMPRESS
@@ -358,7 +358,7 @@ config KALLSYMS
This is useful to print a nice backtrace when an exception occurs.
config RELOCATABLE
- depends on PPC || ARM
+ depends on PPC || ARM || RISCV
bool "generate relocatable barebox binary"
help
A non relocatable barebox binary will run at it's compiled in
diff --git a/images/Makefile b/images/Makefile
index 84492a154d16..8070531c54e3 100644
--- a/images/Makefile
+++ b/images/Makefile
@@ -42,6 +42,8 @@
# both as entrypoint and as filename
#
+include scripts/Makefile.lib
+
quiet_cmd_objcopy_bin = OBJCOPYB $@
cmd_objcopy_bin = \
$(OBJCOPY) -O binary $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@ && \
@@ -64,6 +66,7 @@ PBL_CPPFLAGS += -fdata-sections -ffunction-sections
$(obj)/%.pbl: $(pbl-lds) $(BAREBOX_PBL_OBJS) $(obj)/piggy.o $(obj)/sha_sum.o FORCE
$(call if_changed,elf__,$(*F))
+ $(call cmd,prelink__)
$(obj)/%.pblb: $(obj)/%.pbl FORCE
$(call if_changed,objcopy_bin,$(*F))
@@ -164,6 +167,7 @@ include $(srctree)/images/Makefile.at91
include $(srctree)/images/Makefile.zynq
include $(srctree)/images/Makefile.zynqmp
include $(srctree)/images/Makefile.layerscape
+include $(srctree)/images/Makefile.erizo
pblb-$(CONFIG_BOARD_GENERIC_DT) += start_dt_2nd
diff --git a/images/Makefile.erizo b/images/Makefile.erizo
new file mode 100644
index 000000000000..463c6ce4400d
--- /dev/null
+++ b/images/Makefile.erizo
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+quiet_cmd_erizo_nmon_image = MKIMAGE $@
+ cmd_erizo_nmon_image = $(srctree)/scripts/erizo-nmon-image $< $@ || \
+ echo "WARNING: Couldn't create erizo nmon image due to previous errors."
+
+$(obj)/%.nmon: $(obj)/%.img FORCE
+ $(call if_changed,erizo_nmon_image)
+
+pblb-$(CONFIG_BOARD_ERIZO_GENERIC) += start_erizo_generic
+FILE_barebox-erizo-generic.img = start_erizo_generic.pblb
+image-$(CONFIG_BOARD_ERIZO_GENERIC) += barebox-erizo-generic.img barebox-erizo-generic.nmon
diff --git a/pbl/Kconfig b/pbl/Kconfig
index 2eea5aef7a30..451a278c4088 100644
--- a/pbl/Kconfig
+++ b/pbl/Kconfig
@@ -27,7 +27,7 @@ config PBL_SINGLE_IMAGE
if PBL_IMAGE
config PBL_RELOCATABLE
- depends on ARM || MIPS
+ depends on ARM || MIPS || RISCV
bool "relocatable pbl image"
help
Generate a pbl binary which can relocate itself during startup to run
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* Re: MIPS RELOCATABLE: [PATCH 14/20] RISC-V: erizo: migrate to PBL
2021-03-14 12:27 ` [PATCH 14/20] RISC-V: erizo: migrate to PBL Ahmad Fatoum
@ 2021-03-15 8:43 ` Antony Pavlov
2021-03-15 11:45 ` Oleksij Rempel
0 siblings, 1 reply; 36+ messages in thread
From: Antony Pavlov @ 2021-03-15 8:43 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: barebox
On Sun, 14 Mar 2021 13:27:58 +0100
Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
Hi!
> diff --git a/common/Kconfig b/common/Kconfig
> index 36207274f07f..37204fb40a44 100644
> --- a/common/Kconfig
> +++ b/common/Kconfig
> @@ -44,7 +44,7 @@ config BLOCK_WRITE
>
> config USE_COMPRESSED_DTB
> bool
> - depends on ARM
> + depends on ARM || RISCV
> select UNCOMPRESS
> select LZO_DECOMPRESS
>
> @@ -358,7 +358,7 @@ config KALLSYMS
> This is useful to print a nice backtrace when an exception occurs.
>
> config RELOCATABLE
> - depends on PPC || ARM
> + depends on PPC || ARM || RISCV
> bool "generate relocatable barebox binary"
> help
> A non relocatable barebox binary will run at it's compiled in
Hmmm. AFAIR MIPS barebox is relocatable. Why CONFIG_RELOCATABLE does not depend on MIPS?
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: MIPS RELOCATABLE: [PATCH 14/20] RISC-V: erizo: migrate to PBL
2021-03-15 8:43 ` MIPS RELOCATABLE: " Antony Pavlov
@ 2021-03-15 11:45 ` Oleksij Rempel
2021-03-15 12:08 ` Antony Pavlov
0 siblings, 1 reply; 36+ messages in thread
From: Oleksij Rempel @ 2021-03-15 11:45 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
On Mon, Mar 15, 2021 at 11:43:53AM +0300, Antony Pavlov wrote:
> On Sun, 14 Mar 2021 13:27:58 +0100
> Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>
> Hi!
>
> > diff --git a/common/Kconfig b/common/Kconfig
> > index 36207274f07f..37204fb40a44 100644
> > --- a/common/Kconfig
> > +++ b/common/Kconfig
> > @@ -44,7 +44,7 @@ config BLOCK_WRITE
> >
> > config USE_COMPRESSED_DTB
> > bool
> > - depends on ARM
> > + depends on ARM || RISCV
> > select UNCOMPRESS
> > select LZO_DECOMPRESS
> >
> > @@ -358,7 +358,7 @@ config KALLSYMS
> > This is useful to print a nice backtrace when an exception occurs.
> >
> > config RELOCATABLE
> > - depends on PPC || ARM
> > + depends on PPC || ARM || RISCV
> > bool "generate relocatable barebox binary"
> > help
> > A non relocatable barebox binary will run at it's compiled in
>
> Hmmm. AFAIR MIPS barebox is relocatable. Why CONFIG_RELOCATABLE does not depend on MIPS?
>
good point, I'll need to test it
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: MIPS RELOCATABLE: [PATCH 14/20] RISC-V: erizo: migrate to PBL
2021-03-15 11:45 ` Oleksij Rempel
@ 2021-03-15 12:08 ` Antony Pavlov
2021-03-15 12:40 ` Ahmad Fatoum
0 siblings, 1 reply; 36+ messages in thread
From: Antony Pavlov @ 2021-03-15 12:08 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: barebox
On Mon, 15 Mar 2021 12:45:15 +0100
Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> On Mon, Mar 15, 2021 at 11:43:53AM +0300, Antony Pavlov wrote:
> > On Sun, 14 Mar 2021 13:27:58 +0100
> > Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
> >
> > Hi!
> >
> > > diff --git a/common/Kconfig b/common/Kconfig
> > > index 36207274f07f..37204fb40a44 100644
> > > --- a/common/Kconfig
> > > +++ b/common/Kconfig
> > > @@ -44,7 +44,7 @@ config BLOCK_WRITE
> > >
> > > config USE_COMPRESSED_DTB
> > > bool
> > > - depends on ARM
> > > + depends on ARM || RISCV
> > > select UNCOMPRESS
> > > select LZO_DECOMPRESS
> > >
> > > @@ -358,7 +358,7 @@ config KALLSYMS
> > > This is useful to print a nice backtrace when an exception occurs.
> > >
> > > config RELOCATABLE
> > > - depends on PPC || ARM
> > > + depends on PPC || ARM || RISCV
> > > bool "generate relocatable barebox binary"
> > > help
> > > A non relocatable barebox binary will run at it's compiled in
> >
> > Hmmm. AFAIR MIPS barebox is relocatable. Why CONFIG_RELOCATABLE does not depend on MIPS?
> >
> good point, I'll need to test it
At the first glance the only point to enable CONFIG_RELOCATABLE is to enable FS_PSTORE.
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: MIPS RELOCATABLE: [PATCH 14/20] RISC-V: erizo: migrate to PBL
2021-03-15 12:08 ` Antony Pavlov
@ 2021-03-15 12:40 ` Ahmad Fatoum
2021-03-15 15:37 ` Antony Pavlov
0 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-15 12:40 UTC (permalink / raw)
To: Antony Pavlov, Oleksij Rempel; +Cc: barebox
Hello,
On 15.03.21 13:08, Antony Pavlov wrote:
> On Mon, 15 Mar 2021 12:45:15 +0100
> Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>
>> On Mon, Mar 15, 2021 at 11:43:53AM +0300, Antony Pavlov wrote:
>>> On Sun, 14 Mar 2021 13:27:58 +0100
>>> Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>>>
>>> Hi!
>>>
>>>> diff --git a/common/Kconfig b/common/Kconfig
>>>> index 36207274f07f..37204fb40a44 100644
>>>> --- a/common/Kconfig
>>>> +++ b/common/Kconfig
>>>> @@ -44,7 +44,7 @@ config BLOCK_WRITE
>>>>
>>>> config USE_COMPRESSED_DTB
>>>> bool
>>>> - depends on ARM
>>>> + depends on ARM || RISCV
>>>> select UNCOMPRESS
>>>> select LZO_DECOMPRESS
>>>>
>>>> @@ -358,7 +358,7 @@ config KALLSYMS
>>>> This is useful to print a nice backtrace when an exception occurs.
>>>>
>>>> config RELOCATABLE
>>>> - depends on PPC || ARM
>>>> + depends on PPC || ARM || RISCV
>>>> bool "generate relocatable barebox binary"
>>>> help
>>>> A non relocatable barebox binary will run at it's compiled in
>>>
>>> Hmmm. AFAIR MIPS barebox is relocatable. Why CONFIG_RELOCATABLE does not depend on MIPS?
>>>
>> good point, I'll need to test it
>
> At the first glance the only point to enable CONFIG_RELOCATABLE is to enable FS_PSTORE.
Without having dug into the MIPS code, the main point of CONFIG_RELOCATABLE
is that PBL can check for it to decide where to copy barebox proper to.
This is very relevant if there's no TEXT_BASE that works for all boards
that you need to support with your multi-image barebox.
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
_______________________________________________
barebox mailing list
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http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: MIPS RELOCATABLE: [PATCH 14/20] RISC-V: erizo: migrate to PBL
2021-03-15 12:40 ` Ahmad Fatoum
@ 2021-03-15 15:37 ` Antony Pavlov
2021-03-15 15:46 ` Ahmad Fatoum
0 siblings, 1 reply; 36+ messages in thread
From: Antony Pavlov @ 2021-03-15 15:37 UTC (permalink / raw)
To: Oleksij Rempel; +Cc: Ahmad Fatoum, barebox
On Mon, 15 Mar 2021 13:40:10 +0100
Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
Hi!
> Hello,
>
> On 15.03.21 13:08, Antony Pavlov wrote:
> > On Mon, 15 Mar 2021 12:45:15 +0100
> > Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> >
> >> On Mon, Mar 15, 2021 at 11:43:53AM +0300, Antony Pavlov wrote:
> >>> On Sun, 14 Mar 2021 13:27:58 +0100
> >>> Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
> >>>
> >>> Hi!
> >>>
> >>>> diff --git a/common/Kconfig b/common/Kconfig
> >>>> index 36207274f07f..37204fb40a44 100644
> >>>> --- a/common/Kconfig
> >>>> +++ b/common/Kconfig
> >>>> @@ -44,7 +44,7 @@ config BLOCK_WRITE
> >>>>
> >>>> config USE_COMPRESSED_DTB
> >>>> bool
> >>>> - depends on ARM
> >>>> + depends on ARM || RISCV
> >>>> select UNCOMPRESS
> >>>> select LZO_DECOMPRESS
> >>>>
> >>>> @@ -358,7 +358,7 @@ config KALLSYMS
> >>>> This is useful to print a nice backtrace when an exception occurs.
> >>>>
> >>>> config RELOCATABLE
> >>>> - depends on PPC || ARM
> >>>> + depends on PPC || ARM || RISCV
> >>>> bool "generate relocatable barebox binary"
> >>>> help
> >>>> A non relocatable barebox binary will run at it's compiled in
> >>>
> >>> Hmmm. AFAIR MIPS barebox is relocatable. Why CONFIG_RELOCATABLE does not depend on MIPS?
> >>>
> >> good point, I'll need to test it
> >
> > At the first glance the only point to enable CONFIG_RELOCATABLE is to enable FS_PSTORE.
>
> Without having dug into the MIPS code, the main point of CONFIG_RELOCATABLE
> is that PBL can check for it to decide where to copy barebox proper to.
>
> This is very relevant if there's no TEXT_BASE that works for all boards
> that you need to support with your multi-image barebox.
So CONFIG_RELOCATABLE can be very helpful.
At the moment MIPS barebox is always relocatable.
Sometimes it's useful to run barebox from fixed TEXT_BASE (e.g. during gdb debug session),
so this fixed TEXT_BASE behaviour can be introduced for CONFIG_RELOCATABLE=n case.
--
Best regards,
Antony Pavlov
_______________________________________________
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: MIPS RELOCATABLE: [PATCH 14/20] RISC-V: erizo: migrate to PBL
2021-03-15 15:37 ` Antony Pavlov
@ 2021-03-15 15:46 ` Ahmad Fatoum
2021-03-15 17:03 ` Oleksij Rempel
0 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-15 15:46 UTC (permalink / raw)
To: Antony Pavlov, Oleksij Rempel, Michael Grzeschik; +Cc: barebox
Hi,
On 15.03.21 16:37, Antony Pavlov wrote:
> On Mon, 15 Mar 2021 13:40:10 +0100
> Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>> Without having dug into the MIPS code, the main point of CONFIG_RELOCATABLE
>> is that PBL can check for it to decide where to copy barebox proper to.
>>
>> This is very relevant if there's no TEXT_BASE that works for all boards
>> that you need to support with your multi-image barebox.
>
> So CONFIG_RELOCATABLE can be very helpful.
>
> At the moment MIPS barebox is always relocatable.
> Sometimes it's useful to run barebox from fixed TEXT_BASE (e.g. during gdb debug session),
> so this fixed TEXT_BASE behaviour can be introduced for CONFIG_RELOCATABLE=n case.
With the pbl break stuff, you could in theory already flip a config option
and have a gdb script that computes your load address from the address of
your breakpoint. That would be nice to have as a ready-to-use script.
I recall Oleksij and Michael did something in that regard.
Benefit is that the break is an actual machine code nop when inactive,
so binary size/layout shouldn't change, unlike with flipping CONFIG_RELOCATABLE.
For RISC-V, I see no good reason to allow CONFIG_RELOCATABLE=n right now.
Cheers,
Ahmad
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: MIPS RELOCATABLE: [PATCH 14/20] RISC-V: erizo: migrate to PBL
2021-03-15 15:46 ` Ahmad Fatoum
@ 2021-03-15 17:03 ` Oleksij Rempel
0 siblings, 0 replies; 36+ messages in thread
From: Oleksij Rempel @ 2021-03-15 17:03 UTC (permalink / raw)
To: Ahmad Fatoum, Antony Pavlov, Oleksij Rempel, Michael Grzeschik; +Cc: barebox
Am 15.03.21 um 16:46 schrieb Ahmad Fatoum:
> Hi,
>
> On 15.03.21 16:37, Antony Pavlov wrote:
>> On Mon, 15 Mar 2021 13:40:10 +0100
>> Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
>>> Without having dug into the MIPS code, the main point of CONFIG_RELOCATABLE
>>> is that PBL can check for it to decide where to copy barebox proper to.
>>>
>>> This is very relevant if there's no TEXT_BASE that works for all boards
>>> that you need to support with your multi-image barebox.
>>
>> So CONFIG_RELOCATABLE can be very helpful.
>>
>> At the moment MIPS barebox is always relocatable.
>> Sometimes it's useful to run barebox from fixed TEXT_BASE (e.g. during gdb debug session),
>> so this fixed TEXT_BASE behaviour can be introduced for CONFIG_RELOCATABLE=n case.
>
> With the pbl break stuff, you could in theory already flip a config option
> and have a gdb script that computes your load address from the address of
> your breakpoint. That would be nice to have as a ready-to-use script.
>
> I recall Oleksij and Michael did something in that regard.
>
> Benefit is that the break is an actual machine code nop when inactive,
> so binary size/layout shouldn't change, unlike with flipping CONFIG_RELOCATABLE.
> For RISC-V, I see no good reason to allow CONFIG_RELOCATABLE=n right now.
>
> Cheers,
> Ahmad
>
If i remember it correctly, this two patches are needed, to make
relocatable barebox debugable with openocd and gdb
https://git.pengutronix.de/cgit/barebox/commit/?id=c37cc2d725a496551113f4ebb1d116823eb0dbd1
https://git.pengutronix.de/cgit/barebox/commit/?id=d71573a006a2fc2b83c076c556b88166f4e3dec3
For the MIPS and RISC-V we would need similar helpers.
Regards,
Oleksij
--
Regards,
Oleksij
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 15/20] RISC-V: support symbol names in barebox image
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (13 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 14/20] RISC-V: erizo: migrate to PBL Ahmad Fatoum
@ 2021-03-14 12:27 ` Ahmad Fatoum
2021-03-14 12:28 ` [PATCH 16/20] RISC-V: add 64-bit support Ahmad Fatoum
` (5 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:27 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
Make debugging a bit more convenient by providing users the option to
include symbol names.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4a2a547a7b35..91e8546f9624 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,7 @@ config RISCV
select HAVE_PBL_IMAGE
select HAVE_PBL_MULTI_IMAGES
select HAVE_IMAGE_COMPRESSION
+ select HAS_KALLSYMS
config ARCH_TEXT_BASE
hex
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 16/20] RISC-V: add 64-bit support
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (14 preceding siblings ...)
2021-03-14 12:27 ` [PATCH 15/20] RISC-V: support symbol names in barebox image Ahmad Fatoum
@ 2021-03-14 12:28 ` Ahmad Fatoum
2021-03-14 12:51 ` Rouven Czerwinski
2021-03-14 13:03 ` [PATCH 1/2] fixup! " Ahmad Fatoum
2021-03-14 12:28 ` [PATCH 17/20] RISC-V: add generic DT image Ahmad Fatoum
` (4 subsequent siblings)
20 siblings, 2 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:28 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
From: Rouven Czerwinski <r.czerwinski@pengutronix.de>
As our assembly routines are now written to work correctly on 32-bit as
well as 64-bit, nothing is holding us back from adding 64-bit support.
Signed-off-by: Rouven Czerwinski <r.czerwinksi@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/Kconfig | 25 ++++++++++++++++++-------
arch/riscv/Makefile | 7 +++++--
arch/riscv/include/asm/elf.h | 1 -
arch/riscv/include/asm/types.h | 8 +-------
arch/riscv/lib/barebox.lds.S | 5 +++++
arch/riscv/lib/pbl.lds.S | 5 +++++
6 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 91e8546f9624..29ac95aa0f4d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -25,6 +25,7 @@ choice
config MACH_ERIZO
bool "erizo family"
+ select ARCH_RV32I
select HAS_DEBUG_LL
select HAS_NMON
select USE_COMPRESSED_DTB
@@ -42,23 +43,33 @@ config ARCH_RV32I
select GENERIC_LIB_ASHRDI3
select GENERIC_LIB_LSHRDI3
select HAS_ARCH_SJLJ
+ select 32BIT
+
+config ARCH_RV64I
+ bool "RV64I"
+ select CPU_SUPPORTS_64BIT_KERNEL
+ select 64BIT
endchoice
config CPU_SUPPORTS_32BIT_KERNEL
bool
-choice
- prompt "barebox code model"
- default 32BIT
+config CPU_SUPPORTS_64BIT_KERNEL
+ bool
+
+config PHYS_ADDR_T_64BIT
+ bool
config 32BIT
- bool "32-bit barebox"
+ bool
depends on CPU_SUPPORTS_32BIT_KERNEL
- help
- Select this option to build a 32-bit barebox.
-endchoice
+config 64BIT
+ bool
+ depends on CPU_SUPPORTS_64BIT_KERNEL
+ select ARCH_DMA_ADDR_T_64BIT
+ select PHYS_ADDR_T_64BIT
source "arch/riscv/mach-erizo/Kconfig"
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index f59e8b39a572..f60239fd253b 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -3,8 +3,11 @@ KBUILD_DEFCONFIG := erizo_generic_defconfig
KBUILD_CPPFLAGS += -fno-strict-aliasing
ifeq ($(CONFIG_ARCH_RV32I),y)
- riscv-cflags-y := -march=rv32im -mabi=ilp32
- riscv-ldflags-y := -melf32lriscv
+ riscv-cflags-y += -march=rv32im -mabi=ilp32
+ riscv-ldflags-y += -melf32lriscv
+else
+ riscv-cflags-y += -march=rv64imafd -mabi=lp64
+ riscv-ldflags-y += -melf64lriscv
endif
riscv-cflags-y += -Wstrict-prototypes -mcmodel=medany -fpic
diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index adb8ec8f6ece..0cd27724da60 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -4,7 +4,6 @@
#if __SIZEOF_POINTER__ == 8
#define ELF_CLASS ELFCLASS64
-#define CONFIG_PHYS_ADDR_T_64BIT
#else
#define ELF_CLASS ELFCLASS32
#endif
diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h
index af37d7738c65..1ad5904f9178 100644
--- a/arch/riscv/include/asm/types.h
+++ b/arch/riscv/include/asm/types.h
@@ -3,18 +3,12 @@
#include <asm-generic/int-ll64.h>
-#ifdef __riscv64
+#if __riscv_xlen == 64
/*
* This is used in dlmalloc. On RISCV64 we need it to be 64 bit
*/
#define INTERNAL_SIZE_T unsigned long
-/*
- * This is a Kconfig variable in the Kernel, but we want to detect
- * this during compile time, so we set it here.
- */
-#define CONFIG_PHYS_ADDR_T_64BIT
-
#endif
#endif /* __ASM_RISCV_TYPES_H */
diff --git a/arch/riscv/lib/barebox.lds.S b/arch/riscv/lib/barebox.lds.S
index 562ad5dc6662..7856b57a5220 100644
--- a/arch/riscv/lib/barebox.lds.S
+++ b/arch/riscv/lib/barebox.lds.S
@@ -15,6 +15,11 @@
OUTPUT_ARCH(riscv)
ENTRY(start)
+#ifdef CONFIG_64BIT
+OUTPUT_FORMAT("elf64-littleriscv")
+#else
+OUTPUT_FORMAT("elf32-littleriscv")
+#endif
SECTIONS
{
. = 0x0;
diff --git a/arch/riscv/lib/pbl.lds.S b/arch/riscv/lib/pbl.lds.S
index 33caab7b1024..f1dd9aeabacc 100644
--- a/arch/riscv/lib/pbl.lds.S
+++ b/arch/riscv/lib/pbl.lds.S
@@ -6,6 +6,11 @@
#include <asm-generic/memory_layout.h>
OUTPUT_ARCH(riscv)
+#ifdef CONFIG_64BIT
+OUTPUT_FORMAT("elf64-littleriscv")
+#else
+OUTPUT_FORMAT("elf32-littleriscv")
+#endif
SECTIONS
{
. = 0x0;
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 16/20] RISC-V: add 64-bit support
2021-03-14 12:28 ` [PATCH 16/20] RISC-V: add 64-bit support Ahmad Fatoum
@ 2021-03-14 12:51 ` Rouven Czerwinski
2021-03-14 13:03 ` [PATCH 1/2] fixup! " Ahmad Fatoum
1 sibling, 0 replies; 36+ messages in thread
From: Rouven Czerwinski @ 2021-03-14 12:51 UTC (permalink / raw)
To: Ahmad Fatoum, barebox
Hi Ahmad,
On Sun, 2021-03-14 at 13:28 +0100, Ahmad Fatoum wrote:
> From: Rouven Czerwinski <r.czerwinski@pengutronix.de>
> […]
> ifeq ($(CONFIG_ARCH_RV32I),y)
> - riscv-cflags-y := -march=rv32im -mabi=ilp32
> - riscv-ldflags-y := -melf32lriscv
> + riscv-cflags-y += -march=rv32im -mabi=ilp32
> + riscv-ldflags-y += -melf32lriscv
> +else
> + riscv-cflags-y += -march=rv64imafd -mabi=lp64
This should also work with -march=rv64im, we are not using atomics or
floating ops anywhere and should not require this until needed.
> + riscv-ldflags-y += -melf64lriscv
> endif
>
Regards,
Rouven
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 1/2] fixup! RISC-V: add 64-bit support
2021-03-14 12:28 ` [PATCH 16/20] RISC-V: add 64-bit support Ahmad Fatoum
2021-03-14 12:51 ` Rouven Czerwinski
@ 2021-03-14 13:03 ` Ahmad Fatoum
2021-03-14 13:03 ` [PATCH 2/2] " Ahmad Fatoum
1 sibling, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 13:03 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
The sjlj implementation is actually written so that it works fine on
both 32- and 64- bit RISC-V. We can thus select it from CONFIG_RISCV
directly.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
arch/riscv/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a53ac4d12031..788bf36cfe42 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,7 @@ config RISCV
select HAVE_PBL_IMAGE
select HAVE_PBL_MULTI_IMAGES
select HAVE_IMAGE_COMPRESSION
+ select HAS_ARCH_SJLJ
select HAS_KALLSYMS
config ARCH_TEXT_BASE
@@ -50,7 +51,6 @@ config ARCH_RV32I
select GENERIC_LIB_ASHLDI3
select GENERIC_LIB_ASHRDI3
select GENERIC_LIB_LSHRDI3
- select HAS_ARCH_SJLJ
select 32BIT
config ARCH_RV64I
--
2.30.0
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 2/2] fixup! RISC-V: add 64-bit support
2021-03-14 13:03 ` [PATCH 1/2] fixup! " Ahmad Fatoum
@ 2021-03-14 13:03 ` Ahmad Fatoum
2021-03-15 8:38 ` Antony Pavlov
0 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 13:03 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, Rouven Czerwinski
We don't yet require support for float and atomic ops, so remove
their letter.
Suggested-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
arch/riscv/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 133e43af41bf..6df7d9d9eeac 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -6,7 +6,7 @@ ifeq ($(CONFIG_ARCH_RV32I),y)
riscv-cflags-y += -march=rv32im -mabi=ilp32
riscv-ldflags-y += -melf32lriscv
else
- riscv-cflags-y += -march=rv64imafd -mabi=lp64
+ riscv-cflags-y += -march=rv64im -mabi=lp64
riscv-ldflags-y += -melf64lriscv
endif
--
2.30.0
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/2] fixup! RISC-V: add 64-bit support
2021-03-14 13:03 ` [PATCH 2/2] " Ahmad Fatoum
@ 2021-03-15 8:38 ` Antony Pavlov
0 siblings, 0 replies; 36+ messages in thread
From: Antony Pavlov @ 2021-03-15 8:38 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, Rouven Czerwinski
On Sun, 14 Mar 2021 14:03:01 +0100
Ahmad Fatoum <ahmad@a3f.at> wrote:
Hi!
> We don't yet require support for float and atomic ops, so remove
> their letter.
>
> Suggested-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
> ---
> arch/riscv/Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 133e43af41bf..6df7d9d9eeac 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -6,7 +6,7 @@ ifeq ($(CONFIG_ARCH_RV32I),y)
> riscv-cflags-y += -march=rv32im -mabi=ilp32
> riscv-ldflags-y += -melf32lriscv
> else
> - riscv-cflags-y += -march=rv64imafd -mabi=lp64
> + riscv-cflags-y += -march=rv64im -mabi=lp64
^^^^^
Can you drop extra whitespace here, please?
> riscv-ldflags-y += -melf64lriscv
> endif
>
> --
> 2.30.0
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
--
Best regards,
Antony Pavlov
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 17/20] RISC-V: add generic DT image
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (15 preceding siblings ...)
2021-03-14 12:28 ` [PATCH 16/20] RISC-V: add 64-bit support Ahmad Fatoum
@ 2021-03-14 12:28 ` Ahmad Fatoum
2021-03-14 12:28 ` [PATCH 18/20] clocksource: add driver for RISC-V CLINT timer Ahmad Fatoum
` (3 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:28 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
This barebox image implements the same header as Linux and receives
the device tree in the same register. It can be booted from barebox
or loaded by Qemu -kernel option.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/Kconfig | 9 ++++
arch/riscv/boot/Makefile | 1 +
arch/riscv/boot/board-dt-2nd-entry.S | 26 +++++++++++
arch/riscv/boot/board-dt-2nd.c | 29 +++++++++++++
arch/riscv/include/asm/image.h | 65 ++++++++++++++++++++++++++++
5 files changed, 130 insertions(+)
create mode 100644 arch/riscv/boot/board-dt-2nd-entry.S
create mode 100644 arch/riscv/boot/board-dt-2nd.c
create mode 100644 arch/riscv/include/asm/image.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 29ac95aa0f4d..7a47bd90135a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -73,6 +73,15 @@ config 64BIT
source "arch/riscv/mach-erizo/Kconfig"
+config BOARD_RISCV_GENERIC_DT
+ select BOARD_GENERIC_DT
+ bool "Build generic RISC-V device tree 2nd stage image"
+ help
+ This enables compilation of a generic image that can be started 2nd
+ stage from barebox or from qemu. It picks up a device tree passed
+ in a1 like the Kernel does, so it could be used anywhere where a Kernel
+ image could be used. The image will be called images/barebox-dt-2nd.img
+
endmenu
menu "RISC-V specific settings"
diff --git a/arch/riscv/boot/Makefile b/arch/riscv/boot/Makefile
index 954e9b602287..d32322875979 100644
--- a/arch/riscv/boot/Makefile
+++ b/arch/riscv/boot/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += start.o
obj-pbl-y += entry.o entry_ll.o uncompress.o
+pbl-$(CONFIG_BOARD_GENERIC_DT) += board-dt-2nd.o board-dt-2nd-entry.o
diff --git a/arch/riscv/boot/board-dt-2nd-entry.S b/arch/riscv/boot/board-dt-2nd-entry.S
new file mode 100644
index 000000000000..520c40589356
--- /dev/null
+++ b/arch/riscv/boot/board-dt-2nd-entry.S
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-FileCopyrightText: Copyright (c) 2021 Ahmad Fatoum, Pengutronix */
+#include <linux/linkage.h>
+#include <asm/image.h>
+
+.section .text_head_entry_start_dt_2nd
+ENTRY(start_dt_2nd)
+ auipc sp, 0 /* code0 */
+ j dt_2nd_riscv
+ .balign 8
+#if __riscv_xlen == 64
+ .dword 0x200000 /* Image load offset(2MB) from start of RAM */
+#else
+ .dword 0x400000 /* Image load offset(4MB) from start of RAM */
+#endif
+ .dword _barebox_image_size /* Effective Image size */
+ .dword 0 /* Kernel flags */
+ .word RISCV_HEADER_VERSION /* version */
+ .word 0 /* reserved */
+ .dword 0 /* reserved */
+ .ascii RISCV_IMAGE_MAGIC /* magic1 */
+ .balign 4
+ .ascii RISCV_IMAGE_MAGIC2 /* magic2 */
+ .word 0 /* reserved (PE-COFF offset) */
+ .asciz "barebox" /* unused for now */
+END(start_dt_2nd)
diff --git a/arch/riscv/boot/board-dt-2nd.c b/arch/riscv/boot/board-dt-2nd.c
new file mode 100644
index 000000000000..8eaddd80b1f3
--- /dev/null
+++ b/arch/riscv/boot/board-dt-2nd.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <asm/barebox-riscv.h>
+#include <debug_ll.h>
+#include <pbl.h>
+
+static noinline void dt_2nd_continue(void *fdt)
+{
+ unsigned long membase, memsize;
+
+ if (!fdt)
+ hang();
+
+ fdt_find_mem(fdt, &membase, &memsize);
+
+ barebox_riscv_entry(membase, memsize, fdt);
+}
+
+/* called from assembly */
+void dt_2nd_riscv(unsigned long a0, void *fdt);
+
+void dt_2nd_riscv(unsigned long a0, void *fdt)
+{
+ relocate_to_current_adr();
+ setup_c();
+
+ dt_2nd_continue(fdt);
+}
diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h
new file mode 100644
index 000000000000..e0b319af3681
--- /dev/null
+++ b/arch/riscv/include/asm/image.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _ASM_RISCV_IMAGE_H
+#define _ASM_RISCV_IMAGE_H
+
+#define RISCV_IMAGE_MAGIC "RISCV\0\0\0"
+#define RISCV_IMAGE_MAGIC2 "RSC\x05"
+
+#define RISCV_IMAGE_FLAG_BE_SHIFT 0
+#define RISCV_IMAGE_FLAG_BE_MASK 0x1
+
+#define RISCV_IMAGE_FLAG_LE 0
+#define RISCV_IMAGE_FLAG_BE 1
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#error conversion of header fields to LE not yet implemented
+#else
+#define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE
+#endif
+
+#define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \
+ RISCV_IMAGE_FLAG_##field##_SHIFT)
+
+#define __HEAD_FLAGS (__HEAD_FLAG(BE))
+
+#define RISCV_HEADER_VERSION_MAJOR 0
+#define RISCV_HEADER_VERSION_MINOR 2
+
+#define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \
+ RISCV_HEADER_VERSION_MINOR)
+
+#ifndef __ASSEMBLY__
+/**
+ * struct riscv_image_header - riscv kernel image header
+ * @code0: Executable code
+ * @code1: Executable code
+ * @text_offset: Image load offset (little endian)
+ * @image_size: Effective Image size (little endian)
+ * @flags: kernel flags (little endian)
+ * @version: version
+ * @res1: reserved
+ * @res2: reserved
+ * @magic: Magic number (RISC-V specific; deprecated)
+ * @magic2: Magic number 2 (to match the ARM64 'magic' field pos)
+ * @res3: reserved (will be used for PE COFF offset)
+ *
+ * The intention is for this header format to be shared between multiple
+ * architectures to avoid a proliferation of image header formats.
+ */
+
+struct riscv_image_header {
+ u32 code0;
+ u32 code1;
+ u64 text_offset;
+ u64 image_size;
+ u64 flags;
+ u32 version;
+ u32 res1;
+ u64 res2;
+ u64 magic;
+ u32 magic2;
+ u32 res3;
+};
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_RISCV_IMAGE_H */
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 18/20] clocksource: add driver for RISC-V CLINT timer
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (16 preceding siblings ...)
2021-03-14 12:28 ` [PATCH 17/20] RISC-V: add generic DT image Ahmad Fatoum
@ 2021-03-14 12:28 ` Ahmad Fatoum
2021-03-14 12:28 ` [PATCH 19/20] power: reset: add drivers for generic syscon reset and poweroff Ahmad Fatoum
` (2 subsequent siblings)
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:28 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
Linux selects this on nommu RISC-V machines. It's also used on the Virt
machine added in a follow-up commit.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clocksource/Kconfig | 7 +++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-clint.c | 98 +++++++++++++++++++++++++++++++
3 files changed, 106 insertions(+)
create mode 100644 drivers/clocksource/timer-clint.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 6dfe6151ac98..7f829490e108 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -99,4 +99,11 @@ config CLOCKSOURCE_TI_DM
config CLOCKSOURCE_TI_32K
bool
+config CLINT_TIMER
+ bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
+ depends on OFDEVICE
+ help
+ This option enables the CLINT timer for RISC-V systems. The CLINT
+ driver is usually used for NoMMU RISC-V systems.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index b4607f787fcf..268ce16800a7 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_CLOCKSOURCE_IMX_GPT) += timer-imx-gpt.o
obj-$(CONFIG_CLOCKSOURCE_DW_APB_TIMER) += dw_apb_timer.o
obj-$(CONFIG_CLOCKSOURCE_TI_DM) += timer-ti-dm.o
obj-$(CONFIG_CLOCKSOURCE_TI_32K) += timer-ti-32k.o
+obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
new file mode 100644
index 000000000000..620222b51226
--- /dev/null
+++ b/drivers/clocksource/timer-clint.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
+ * CLINT MMIO timer device.
+ */
+
+#define pr_fmt(fmt) "clint: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <errno.h>
+#include <of.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <notifier.h>
+#include <io.h>
+
+#define CLINT_TIMER_VAL_OFF 0xbff8
+
+#ifdef CONFIG_64BIT
+#define clint_get_cycles() readq(clint_timer_val)
+#else
+#define clint_get_cycles() readl(clint_timer_val)
+#define clint_get_cycles_hi() readl(((u32 *)clint_timer_val) + 1)
+#endif
+
+static void __iomem *clint_timer_val;
+
+#ifdef CONFIG_64BIT
+static u64 notrace clint_get_cycles64(void)
+{
+ return clint_get_cycles();
+}
+#else /* CONFIG_64BIT */
+static u64 notrace clint_get_cycles64(void)
+{
+ u32 hi, lo;
+
+ do {
+ hi = clint_get_cycles_hi();
+ lo = clint_get_cycles();
+ } while (hi != clint_get_cycles_hi());
+
+ return ((u64)hi << 32) | lo;
+}
+#endif /* CONFIG_64BIT */
+
+static u64 clint_rdtime(void)
+{
+ return clint_get_cycles64();
+}
+
+static struct clocksource clint_clocksource = {
+ .read = clint_rdtime,
+ .mask = CLOCKSOURCE_MASK(64),
+};
+
+static int clint_timer_init_dt(struct device_d* dev)
+{
+ struct device_node *cpu;
+ struct resource *iores;
+ u32 riscv_timebase;
+
+ /* one timer is enough */
+ if (clint_timer_val)
+ return 0;
+
+ iores = dev_request_mem_resource(dev, 0);
+ if (IS_ERR(iores))
+ return PTR_ERR(iores);
+ clint_timer_val = IOMEM(iores->start) + CLINT_TIMER_VAL_OFF;
+
+ cpu = of_find_node_by_path("/cpus");
+ if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &riscv_timebase))
+ panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n");
+
+ dev_info(dev, "running at %u Hz\n", riscv_timebase);
+
+ clint_clocksource.mult = clocksource_hz2mult(riscv_timebase, clint_clocksource.shift);
+
+ return init_clock(&clint_clocksource);
+}
+
+static struct of_device_id time_clint_dt_ids[] = {
+ { .compatible = "riscv,clint0", },
+ { .compatible = "sifive,clint0" },
+ { /* sentinel */ },
+};
+
+static struct driver_d clint_timer_driver = {
+ .name = "clint-timer",
+ .probe = clint_timer_init_dt,
+ .of_compatible = time_clint_dt_ids,
+};
+postcore_platform_driver(clint_timer_driver);
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 19/20] power: reset: add drivers for generic syscon reset and poweroff
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (17 preceding siblings ...)
2021-03-14 12:28 ` [PATCH 18/20] clocksource: add driver for RISC-V CLINT timer Ahmad Fatoum
@ 2021-03-14 12:28 ` Ahmad Fatoum
2021-03-14 12:28 ` [PATCH 20/20] RISC-V: add Qemu virt support Ahmad Fatoum
2021-03-15 8:22 ` [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Antony Pavlov
20 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:28 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
Many SoC reset/poweroff mechanisms can be represented using this generic
binding. Of the boards we support, at least the virt machines can
be rebooted and powered off by it. Import the Linux v5.11 state
of the driver to support this.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/power/reset/Kconfig | 14 ++++
drivers/power/reset/Makefile | 2 +
drivers/power/reset/syscon-poweroff.c | 76 ++++++++++++++++++++++
drivers/power/reset/syscon-reboot.c | 92 +++++++++++++++++++++++++++
4 files changed, 184 insertions(+)
create mode 100644 drivers/power/reset/syscon-poweroff.c
create mode 100644 drivers/power/reset/syscon-reboot.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index f65e1f67fd59..e60037a6e637 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -14,3 +14,17 @@ config SYSCON_REBOOT_MODE
get reboot mode arguments and store it in SYSCON mapped
register, then the bootloader can read it to take different
action according to the mode.
+
+config POWER_RESET_SYSCON
+ bool "Generic SYSCON regmap reset driver"
+ depends on OFDEVICE
+ select MFD_SYSCON
+ help
+ Reboot support for generic SYSCON mapped register reset.
+
+config POWER_RESET_SYSCON_POWEROFF
+ bool "Generic SYSCON regmap poweroff driver"
+ depends on OFDEVICE
+ select MFD_SYSCON
+ help
+ Poweroff support for generic SYSCON mapped register poweroff.
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 56feec78cf26..a490dce87333 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_REBOOT_MODE) += reboot-mode.o
obj-$(CONFIG_SYSCON_REBOOT_MODE) += syscon-reboot-mode.o
+obj-$(CONFIG_POWER_RESET_SYSCON) += syscon-reboot.o
+obj-$(CONFIG_POWER_RESET_SYSCON_POWEROFF) += syscon-poweroff.o
diff --git a/drivers/power/reset/syscon-poweroff.c b/drivers/power/reset/syscon-poweroff.c
new file mode 100644
index 000000000000..3664c4d8bd08
--- /dev/null
+++ b/drivers/power/reset/syscon-poweroff.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Generic Syscon Poweroff Driver
+ *
+ * Copyright (c) 2015, National Instruments Corp.
+ * Author: Moritz Fischer <moritz.fischer@ettus.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <poweroff.h>
+#include <mfd/syscon.h>
+
+static struct regmap *map;
+static u32 offset;
+static u32 value;
+static u32 mask;
+
+static void syscon_poweroff(struct poweroff_handler *handler)
+{
+ /* Issue the poweroff */
+ regmap_update_bits(map, offset, mask, value);
+
+ mdelay(1000);
+
+ pr_emerg("Unable to poweroff system\n");
+}
+
+static int syscon_poweroff_probe(struct device_d *dev)
+{
+ int mask_err, value_err;
+
+ map = syscon_regmap_lookup_by_phandle(dev->device_node, "regmap");
+ if (IS_ERR(map)) {
+ dev_err(dev, "unable to get syscon");
+ return PTR_ERR(map);
+ }
+
+ if (of_property_read_u32(dev->device_node, "offset", &offset)) {
+ dev_err(dev, "unable to read 'offset'");
+ return -EINVAL;
+ }
+
+ value_err = of_property_read_u32(dev->device_node, "value", &value);
+ mask_err = of_property_read_u32(dev->device_node, "mask", &mask);
+ if (value_err && mask_err) {
+ dev_err(dev, "unable to read 'value' and 'mask'");
+ return -EINVAL;
+ }
+
+ if (value_err) {
+ /* support old binding */
+ value = mask;
+ mask = 0xFFFFFFFF;
+ } else if (mask_err) {
+ /* support value without mask*/
+ mask = 0xFFFFFFFF;
+ }
+
+ poweroff_handler_register_fn(syscon_poweroff);
+
+ return 0;
+}
+
+static const struct of_device_id syscon_poweroff_of_match[] = {
+ { .compatible = "syscon-poweroff" },
+ {}
+};
+
+static struct driver_d syscon_poweroff_driver = {
+ .name = "syscon-poweroff",
+ .of_compatible = syscon_poweroff_of_match,
+ .probe = syscon_poweroff_probe,
+};
+
+coredevice_platform_driver(syscon_poweroff_driver);
diff --git a/drivers/power/reset/syscon-reboot.c b/drivers/power/reset/syscon-reboot.c
new file mode 100644
index 000000000000..2dbb6c1ddcb8
--- /dev/null
+++ b/drivers/power/reset/syscon-reboot.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Generic Syscon Reboot Driver
+ *
+ * Copyright (c) 2013, Applied Micro Circuits Corporation
+ * Author: Feng Kan <fkan@apm.com>
+ */
+#include <common.h>
+#include <init.h>
+#include <restart.h>
+#include <mfd/syscon.h>
+
+struct syscon_reboot_context {
+ struct regmap *map;
+ u32 offset;
+ u32 value;
+ u32 mask;
+ struct restart_handler restart_handler;
+};
+
+static void __noreturn syscon_restart_handle(struct restart_handler *this)
+{
+ struct syscon_reboot_context *ctx =
+ container_of(this, struct syscon_reboot_context,
+ restart_handler);
+
+ /* Issue the reboot */
+ regmap_update_bits(ctx->map, ctx->offset, ctx->mask, ctx->value);
+
+ mdelay(1000);
+
+ panic("Unable to restart system\n");
+}
+
+static int syscon_reboot_probe(struct device_d *dev)
+{
+ struct syscon_reboot_context *ctx;
+ int mask_err, value_err;
+ int err;
+
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ ctx->map = syscon_regmap_lookup_by_phandle(dev->device_node, "regmap");
+ if (IS_ERR(ctx->map)) {
+ ctx->map = syscon_node_to_regmap(dev->parent->device_node);
+ if (IS_ERR(ctx->map))
+ return PTR_ERR(ctx->map);
+ }
+
+ if (of_property_read_u32(dev->device_node, "offset", &ctx->offset))
+ return -EINVAL;
+
+ value_err = of_property_read_u32(dev->device_node, "value", &ctx->value);
+ mask_err = of_property_read_u32(dev->device_node, "mask", &ctx->mask);
+ if (value_err && mask_err) {
+ dev_err(dev, "unable to read 'value' and 'mask'");
+ return -EINVAL;
+ }
+
+ if (value_err) {
+ /* support old binding */
+ ctx->value = ctx->mask;
+ ctx->mask = 0xFFFFFFFF;
+ } else if (mask_err) {
+ /* support value without mask*/
+ ctx->mask = 0xFFFFFFFF;
+ }
+
+ ctx->restart_handler.name = "syscon-reboot";
+ ctx->restart_handler.restart = syscon_restart_handle;
+ ctx->restart_handler.priority = 192;
+
+ err = restart_handler_register(&ctx->restart_handler);
+ if (err)
+ dev_err(dev, "can't register restart notifier\n");
+
+ return err;
+}
+
+static const struct of_device_id syscon_reboot_of_match[] = {
+ { .compatible = "syscon-reboot" },
+ {}
+};
+
+static struct driver_d syscon_reboot_driver = {
+ .probe = syscon_reboot_probe,
+ .name = "syscon-reboot",
+ .of_compatible = syscon_reboot_of_match,
+};
+coredevice_platform_driver(syscon_reboot_driver);
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH 20/20] RISC-V: add Qemu virt support
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (18 preceding siblings ...)
2021-03-14 12:28 ` [PATCH 19/20] power: reset: add drivers for generic syscon reset and poweroff Ahmad Fatoum
@ 2021-03-14 12:28 ` Ahmad Fatoum
2021-03-14 16:30 ` [PATCH] fixup! " Ahmad Fatoum
2021-03-15 8:22 ` [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Antony Pavlov
20 siblings, 1 reply; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 12:28 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum, rcz
From: Rouven Czerwinski <r.czerwinski@pengutronix.de>
The generic dt board added in a previous commit can be booted on RISC-V
qemu -M virt. Add defconfigs for both 32- and 64-bit machines.
We could in theory drop the mach directory altogether like it's done on
arm64, but for now it's left in as it provides <mach/debug_ll.h>.
It's expected that we can drop it in future in favor of generic earlycon
support (which also wouldn't require manual adjustment of the shared entry
point like with debug_ll).
Signed-off-by: Rouven Czerwinski <r.czerwinksi@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
Documentation/boards/riscv.rst | 59 ++++++++++
arch/riscv/Kconfig | 8 ++
arch/riscv/Makefile | 3 +-
arch/riscv/configs/virt32_defconfig | 117 ++++++++++++++++++
arch/riscv/configs/virt64_defconfig | 118 +++++++++++++++++++
arch/riscv/mach-virt/Makefile | 3 +
arch/riscv/mach-virt/include/mach/debug_ll.h | 25 ++++
7 files changed, 332 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/configs/virt32_defconfig
create mode 100644 arch/riscv/configs/virt64_defconfig
create mode 100644 arch/riscv/mach-virt/Makefile
create mode 100644 arch/riscv/mach-virt/include/mach/debug_ll.h
diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst
index a1f7e30531ee..049029b4f23d 100644
--- a/Documentation/boards/riscv.rst
+++ b/Documentation/boards/riscv.rst
@@ -1,6 +1,65 @@
RISC-V
======
+QEMU Virt
+---------
+
+barebox supports both the qemu riscv32 and riscv64 ``-M virt`` boards::
+
+ make ARCH=riscv virt64_defconfig
+ qemu-system-riscv64 -M virt -serial stdio -kernel build/images/barebox-dt-2nd.img
+
+Replace ``64`` by ``32`` for 32-bit build. :ref:`virtio` over MMIO is supported and
+can be used for e.g. an extra console or to pass in a virtio-blk device::
+
+ qemu-system-riscv64 -M virt -serial stdio \
+ -kernel ./images/barebox-dt-2nd.img \
+ -device virtio-rng-device \
+ -drive if=none,file=./images/barebox-dt-2nd.img,format=raw,id=hd0 \
+ -device virtio-blk-device,drive=hd0 \
+ -device virtio-serial-device \
+ -chardev socket,path=/tmp/foo,server,nowait,id=foo \
+ -device virtconsole,chardev=foo,name=console.foo
+
+ barebox 2021.02.0 #27 Sun Mar 14 10:08:09 CET 2021
+
+
+ Board: riscv-virtio,qemu
+ malloc space: 0x83dff820 -> 0x87bff03f (size 62 MiB)
+
+ barebox@riscv-virtio,qemu:/ filetype /dev/virtioblk0
+ /dev/virtioblk0: RISC-V Linux image (riscv-linux)
+
+Note that the ``board-dt-2nd.img`` uses the Linux RISC-V kernel image
+format and boot protocol. It thus requires the device tree to be passed
+from outside in ``a1`` and must be loaded at an offset as indicated in
+the header for the initial stack to work. Using the ``-kernel`` option
+in Qemu or booting from bootloaders that can properly boot Linux will
+take care of this.
+
+TinyEMU
+-------
+
+TinyEMU can emulate a qemu-virt like machine with a RISC-V 32-, 64-
+and 128-bit CPU. It can run barebox with this sample configuration::
+
+ /* temu barebox-virt64.cfg */
+ {
+ version: 1,
+ machine: "riscv64",
+ memory_size: 256,
+ bios: "bbl64.bin",
+ kernel: "./images/barebox-dt-2nd.img",
+ }
+
+``barebox-dt-2nd.img`` can be generated like with Qemu. Graphical
+output is also supported, but virtio input support is still missing.
+To activate add::
+
+ display0: { device: "simplefb", width: 800, height: 600 },
+
+into the config file.
+
Erizo
-----
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7a47bd90135a..a53ac4d12031 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -30,6 +30,14 @@ config MACH_ERIZO
select HAS_NMON
select USE_COMPRESSED_DTB
+config MACH_VIRT
+ bool "virt family"
+ select BOARD_RISCV_GENERIC_DT
+ select CLINT_TIMER
+ help
+ Generates an image tht can be be booted by QEMU. The image is called
+ barebox-dt-2nd.img
+
endchoice
choice
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index f60239fd253b..133e43af41bf 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -1,4 +1,4 @@
-KBUILD_DEFCONFIG := erizo_generic_defconfig
+KBUILD_DEFCONFIG := virt64_defconfig
KBUILD_CPPFLAGS += -fno-strict-aliasing
@@ -20,6 +20,7 @@ cflags-y += $(riscv-cflags-y)
LDFLAGS_barebox += -nostdlib
machine-$(CONFIG_MACH_ERIZO) := erizo
+machine-$(CONFIG_MACH_VIRT) := virt
LDFLAGS_barebox += $(riscv-ldflags-y)
diff --git a/arch/riscv/configs/virt32_defconfig b/arch/riscv/configs/virt32_defconfig
new file mode 100644
index 000000000000..2c6ecd7005c4
--- /dev/null
+++ b/arch/riscv/configs/virt32_defconfig
@@ -0,0 +1,117 @@
+CONFIG_MACH_VIRT=y
+CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_STACK_SIZE=0x20000
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_PANIC_HANG=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_IMD_TARGET=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_PBL_CONSOLE=y
+CONFIG_PARTITION_DISK_EFI=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_BAREBOXENV_TARGET=y
+CONFIG_BAREBOXCRC32_TARGET=y
+CONFIG_POLLER=y
+CONFIG_STATE=y
+CONFIG_STATE_CRYPTO=y
+CONFIG_BOOTCHOOSER=y
+CONFIG_RESET_SOURCE=y
+CONFIG_MACHINE_ID=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_POLLER=y
+CONFIG_CMD_SLICE=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_BOOTCHOOSER=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_CMP=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SPLASH=y
+CONFIG_CMD_FBTEST=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_2048=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_OF_DIFF=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_DISPLAY_TIMINGS=y
+CONFIG_CMD_OF_FIXUP_STATUS=y
+CONFIG_CMD_OF_OVERLAY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_DRIVER_SPI_GPIO=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
+CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_M25P80=y
+CONFIG_DRIVER_CFI=y
+CONFIG_DRIVER_CFI_BANK_WIDTH_8=y
+CONFIG_DISK=y
+CONFIG_DISK_WRITE=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIDEO=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y
+CONFIG_CLOCKSOURCE_DUMMY_RATE=60000
+CONFIG_EEPROM_AT24=y
+CONFIG_HWRNG=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_PINCTRL is not set
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_FS_UIMAGEFS=y
+CONFIG_FS_PSTORE=y
+CONFIG_FS_SQUASHFS=y
+CONFIG_ZLIB=y
+CONFIG_BZLIB=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_XZ_DECOMPRESS=y
+CONFIG_BASE64=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DIGEST_CRC32_GENERIC=y
diff --git a/arch/riscv/configs/virt64_defconfig b/arch/riscv/configs/virt64_defconfig
new file mode 100644
index 000000000000..adfa6c3613b8
--- /dev/null
+++ b/arch/riscv/configs/virt64_defconfig
@@ -0,0 +1,118 @@
+CONFIG_MACH_VIRT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_STACK_SIZE=0x20000
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_PANIC_HANG=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_IMD_TARGET=y
+CONFIG_CONSOLE_ACTIVATE_NONE=y
+CONFIG_CONSOLE_ALLOW_COLOR=y
+CONFIG_PBL_CONSOLE=y
+CONFIG_PARTITION_DISK_EFI=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_BAREBOXENV_TARGET=y
+CONFIG_BAREBOXCRC32_TARGET=y
+CONFIG_POLLER=y
+CONFIG_STATE=y
+CONFIG_STATE_CRYPTO=y
+CONFIG_BOOTCHOOSER=y
+CONFIG_RESET_SOURCE=y
+CONFIG_MACHINE_ID=y
+CONFIG_CMD_DMESG=y
+CONFIG_LONGHELP=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_IMD=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_POLLER=y
+CONFIG_CMD_SLICE=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_BOOTCHOOSER=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_CMP=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SPLASH=y
+CONFIG_CMD_FBTEST=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_2048=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_OF_DIFF=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_DISPLAY_TIMINGS=y
+CONFIG_CMD_OF_FIXUP_STATUS=y
+CONFIG_CMD_OF_OVERLAY=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_DRIVER_SPI_GPIO=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
+CONFIG_MTD=y
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_M25P80=y
+CONFIG_DRIVER_CFI=y
+CONFIG_DRIVER_CFI_BANK_WIDTH_8=y
+CONFIG_DISK=y
+CONFIG_DISK_WRITE=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIDEO=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y
+CONFIG_CLOCKSOURCE_DUMMY_RATE=60000
+CONFIG_EEPROM_AT24=y
+CONFIG_HWRNG=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_PINCTRL is not set
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_FS_UIMAGEFS=y
+CONFIG_FS_PSTORE=y
+CONFIG_FS_SQUASHFS=y
+CONFIG_ZLIB=y
+CONFIG_BZLIB=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+CONFIG_XZ_DECOMPRESS=y
+CONFIG_BASE64=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DIGEST_CRC32_GENERIC=y
diff --git a/arch/riscv/mach-virt/Makefile b/arch/riscv/mach-virt/Makefile
new file mode 100644
index 000000000000..d9c51e74c379
--- /dev/null
+++ b/arch/riscv/mach-virt/Makefile
@@ -0,0 +1,3 @@
+# just to build a built-in.o. Otherwise compilation fails when no o-files is
+# created.
+obj- += dummy.o
diff --git a/arch/riscv/mach-virt/include/mach/debug_ll.h b/arch/riscv/mach-virt/include/mach/debug_ll.h
new file mode 100644
index 000000000000..056b7a330bdd
--- /dev/null
+++ b/arch/riscv/mach-virt/include/mach/debug_ll.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Antony Pavlov <antonynpavlov@gmail.com>
+ */
+
+#ifndef __MACH_VIRT_DEBUG_LL__
+#define __MACH_VIRT_DEBUG_LL__
+
+/** @file
+ * This File contains declaration for early output support
+ */
+
+#include <linux/kconfig.h>
+
+#define DEBUG_LL_UART_ADDR 0x10000000
+#define DEBUG_LL_UART_SHIFT 0
+#define DEBUG_LL_UART_IOSIZE8
+
+#define DEBUG_LL_UART_CLK 0x00384000
+#define DEBUG_LL_UART_BPS CONFIG_BAUDRATE
+#define DEBUG_LL_UART_DIVISOR (DEBUG_LL_UART_CLK / DEBUG_LL_UART_BPS)
+
+#include <asm/debug_ll_ns16550.h>
+
+#endif /* __MACH_VIRT_DEBUG_LL__ */
--
2.29.2
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^ permalink raw reply [flat|nested] 36+ messages in thread* [PATCH] fixup! RISC-V: add Qemu virt support
2021-03-14 12:28 ` [PATCH 20/20] RISC-V: add Qemu virt support Ahmad Fatoum
@ 2021-03-14 16:30 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-14 16:30 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
Activate first console in order to support machines where the virtio
console is the only console as there is no way there to specify
what the default console should be.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
arch/riscv/configs/virt32_defconfig | 1 -
arch/riscv/configs/virt64_defconfig | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/riscv/configs/virt32_defconfig b/arch/riscv/configs/virt32_defconfig
index 2c6ecd7005c4..83e3ca1bade8 100644
--- a/arch/riscv/configs/virt32_defconfig
+++ b/arch/riscv/configs/virt32_defconfig
@@ -11,7 +11,6 @@ CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_IMD_TARGET=y
-CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_CONSOLE_ALLOW_COLOR=y
CONFIG_PBL_CONSOLE=y
CONFIG_PARTITION_DISK_EFI=y
diff --git a/arch/riscv/configs/virt64_defconfig b/arch/riscv/configs/virt64_defconfig
index adfa6c3613b8..17ce16637d96 100644
--- a/arch/riscv/configs/virt64_defconfig
+++ b/arch/riscv/configs/virt64_defconfig
@@ -12,7 +12,6 @@ CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_IMD_TARGET=y
-CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_CONSOLE_ALLOW_COLOR=y
CONFIG_PBL_CONSOLE=y
CONFIG_PARTITION_DISK_EFI=y
--
2.30.0
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barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support
2021-03-14 12:27 [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
` (19 preceding siblings ...)
2021-03-14 12:28 ` [PATCH 20/20] RISC-V: add Qemu virt support Ahmad Fatoum
@ 2021-03-15 8:22 ` Antony Pavlov
2021-03-15 10:30 ` Ahmad Fatoum
20 siblings, 1 reply; 36+ messages in thread
From: Antony Pavlov @ 2021-03-15 8:22 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, rcz
On Sun, 14 Mar 2021 13:27:44 +0100
Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
Hi!
I'm very glad to see RISC-V support improvement!
Can you please push your RISC-V working branch to github (or other public git repo),
so I can test it too?
At the moment I have at least two out-of tree RISC-V branches that which I want
to rebase on latest barebox with your patches:
* https://github.com/frantony/barebox/tree/20200222.riscv-sifive
contains hacky 64-bit support and add Sifive U500 qemu support.
* https://github.com/litex-hub/barebox/tree/20200727.litex-vexriscv-linux
contains litex SoC with RISC-V 32-bit CPU core support.
It can run linux on Arty, please see
https://github.com/enjoy-digital/litex/issues/413#issuecomment-609047340
It seems, that ethernet driver needs update: https://github.com/litex-hub/barebox/issues/1
I suppose that you can add 'bootm: add RISC-V image type' patch to your series
(I'll send you the patch in a few minutes). The patch used in the litex series.
> With these changes applied, barebox can now generate images that can
> be booted on qemu/tinyemu virt32 and virt64 machines.
>
> The boards have clocksource, virtio, cfi-flash, reboot and poweroff
> support.
>
> Cheers,
> Ahmad Fatoum (18):
> partitions: don't allocate dma capable memory
> images: make BOARD_ARM_GENERIC_DT available for other arches
> ARM: rename CONFIG_ARM_USE_COMPRESSED_DTB to CONFIG_USE_COMPRESSED_DTB
> ARM: aarch64: ommit unused label in assembly
> serial: virtio-console: depend on, but don't select VIRTIO
> filetype: detect RISC-V Linux kernel image
> asm: unaligned: don't do unaligned accesses
> RISC-V: debug_ll: ns16550: align C access size with assembly's
> RISC-V: drop duplicate or unneeded cflags
> RISC-V: add cacheless HAS_DMA support
> RISC-V: erizo: move to arch/riscv/boards/erizo
> RISC-V: import Linux' optimized string functions
> RISC-V: implement PBL and relocation support
> RISC-V: erizo: migrate to PBL
> RISC-V: support symbol names in barebox image
> RISC-V: add generic DT image
> clocksource: add driver for RISC-V CLINT timer
> power: reset: add drivers for generic syscon reset and poweroff
>
> Rouven Czerwinski (2):
> RISC-V: add 64-bit support
> RISC-V: add Qemu virt support
>
> Documentation/boards/riscv.rst | 72 ++++++-
> Makefile | 1 +
> arch/arm/Kconfig | 9 +-
> arch/arm/cpu/start.c | 2 +-
> arch/arm/lib64/runtime-offset.S | 2 +-
> arch/arm/mach-at91/Kconfig | 2 +-
> arch/arm/mach-imx/Kconfig | 26 +--
> arch/arm/mach-omap/Kconfig | 2 +-
> arch/riscv/Kconfig | 66 +++++--
> arch/riscv/Makefile | 34 ++--
> arch/riscv/boards/Makefile | 2 +
> arch/riscv/boards/erizo/Makefile | 3 +
> arch/riscv/boards/erizo/lowlevel.c | 18 ++
> arch/riscv/boot/Makefile | 5 +-
> arch/riscv/boot/board-dt-2nd-entry.S | 26 +++
> arch/riscv/boot/board-dt-2nd.c | 29 +++
> arch/riscv/boot/dtb.c | 25 ---
> arch/riscv/boot/entry.c | 33 ++++
> arch/riscv/boot/entry.h | 15 ++
> arch/riscv/boot/entry_ll.S | 15 ++
> arch/riscv/boot/main_entry.c | 35 ----
> arch/riscv/boot/start.S | 68 -------
> arch/riscv/boot/start.c | 197 +++++++++++++++++++
> arch/riscv/boot/uncompress.c | 74 +++++++
> arch/riscv/configs/erizo_generic_defconfig | 5 -
> arch/riscv/configs/virt32_defconfig | 117 +++++++++++
> arch/riscv/configs/virt64_defconfig | 118 +++++++++++
> arch/riscv/dts/Makefile | 9 +-
> arch/riscv/include/asm/barebox-riscv.h | 101 ++++++++++
> arch/riscv/include/asm/common.h | 10 +-
> arch/riscv/include/asm/debug_ll_ns16550.h | 16 +-
> arch/riscv/include/asm/dma.h | 44 +++++
> arch/riscv/include/asm/elf.h | 8 +-
> arch/riscv/include/asm/image.h | 65 ++++++
> arch/riscv/include/asm/linkage.h | 4 +
> arch/riscv/include/asm/sections.h | 15 ++
> arch/riscv/include/asm/string.h | 21 +-
> arch/riscv/include/asm/types.h | 8 +-
> arch/riscv/include/asm/unaligned.h | 16 +-
> arch/riscv/lib/Makefile | 6 +-
> arch/riscv/lib/barebox.lds.S | 55 ++++--
> arch/riscv/lib/dtb.c | 26 +++
> arch/riscv/lib/memcpy.S | 108 ++++++++++
> arch/riscv/lib/memmove.S | 64 ++++++
> arch/riscv/lib/memset.S | 113 +++++++++++
> arch/riscv/lib/pbl.lds.S | 88 +++++++++
> arch/riscv/lib/reloc.c | 64 ++++++
> arch/riscv/lib/runtime-offset.S | 12 ++
> arch/riscv/lib/sections.c | 9 +
> arch/riscv/lib/setupc.S | 55 ++++++
> arch/riscv/mach-virt/Makefile | 3 +
> arch/riscv/mach-virt/include/mach/debug_ll.h | 25 +++
> common/Kconfig | 8 +-
> common/filetype.c | 3 +
> common/partitions.c | 5 +-
> common/partitions/dos.c | 7 +-
> common/partitions/efi.c | 1 -
> drivers/clocksource/Kconfig | 7 +
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/timer-clint.c | 98 +++++++++
> drivers/power/reset/Kconfig | 14 ++
> drivers/power/reset/Makefile | 2 +
> drivers/power/reset/syscon-poweroff.c | 76 +++++++
> drivers/power/reset/syscon-reboot.c | 92 +++++++++
> drivers/serial/Kconfig | 2 +-
> images/Makefile | 8 +-
> images/Makefile.erizo | 12 ++
> include/dma.h | 1 +
> include/filetype.h | 1 +
> pbl/Kconfig | 6 +-
> scripts/.gitignore | 1 +
> scripts/Makefile | 1 +
> scripts/Makefile.lib | 11 ++
> scripts/prelink-riscv.c | 122 ++++++++++++
> scripts/prelink-riscv.inc | 123 ++++++++++++
> 75 files changed, 2285 insertions(+), 263 deletions(-)
> create mode 100644 arch/riscv/boards/Makefile
> create mode 100644 arch/riscv/boards/erizo/Makefile
> create mode 100644 arch/riscv/boards/erizo/lowlevel.c
> create mode 100644 arch/riscv/boot/board-dt-2nd-entry.S
> create mode 100644 arch/riscv/boot/board-dt-2nd.c
> delete mode 100644 arch/riscv/boot/dtb.c
> create mode 100644 arch/riscv/boot/entry.c
> create mode 100644 arch/riscv/boot/entry.h
> create mode 100644 arch/riscv/boot/entry_ll.S
> delete mode 100644 arch/riscv/boot/main_entry.c
> delete mode 100644 arch/riscv/boot/start.S
> create mode 100644 arch/riscv/boot/start.c
> create mode 100644 arch/riscv/boot/uncompress.c
> create mode 100644 arch/riscv/configs/virt32_defconfig
> create mode 100644 arch/riscv/configs/virt64_defconfig
> create mode 100644 arch/riscv/include/asm/barebox-riscv.h
> create mode 100644 arch/riscv/include/asm/dma.h
> create mode 100644 arch/riscv/include/asm/image.h
> create mode 100644 arch/riscv/lib/dtb.c
> create mode 100644 arch/riscv/lib/memcpy.S
> create mode 100644 arch/riscv/lib/memmove.S
> create mode 100644 arch/riscv/lib/memset.S
> create mode 100644 arch/riscv/lib/pbl.lds.S
> create mode 100644 arch/riscv/lib/reloc.c
> create mode 100644 arch/riscv/lib/runtime-offset.S
> create mode 100644 arch/riscv/lib/sections.c
> create mode 100644 arch/riscv/lib/setupc.S
> create mode 100644 arch/riscv/mach-virt/Makefile
> create mode 100644 arch/riscv/mach-virt/include/mach/debug_ll.h
> create mode 100644 drivers/clocksource/timer-clint.c
> create mode 100644 drivers/power/reset/syscon-poweroff.c
> create mode 100644 drivers/power/reset/syscon-reboot.c
> create mode 100644 images/Makefile.erizo
> create mode 100644 scripts/prelink-riscv.c
> create mode 100644 scripts/prelink-riscv.inc
>
> --
> 2.29.2
>
--
Best regards,
Antony Pavlov
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support
2021-03-15 8:22 ` [PATCH 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Antony Pavlov
@ 2021-03-15 10:30 ` Ahmad Fatoum
0 siblings, 0 replies; 36+ messages in thread
From: Ahmad Fatoum @ 2021-03-15 10:30 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox, rcz
Hello Antony,
On 15.03.21 09:22, Antony Pavlov wrote:
> On Sun, 14 Mar 2021 13:27:44 +0100
> Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
> I'm very glad to see RISC-V support improvement!
Your erizo barebox/qemu work made the initial iterations much quicker,
so thanks for that!
> Can you please push your RISC-V working branch to github (or other public git repo),
> so I can test it too?
Sure. I'll send out a v2 and send you a github link later today or early tomorrow.
> At the moment I have at least two out-of tree RISC-V branches that which I want
> to rebase on latest barebox with your patches:
>
> * https://github.com/frantony/barebox/tree/20200222.riscv-sifive
> contains hacky 64-bit support and add Sifive U500 qemu support.
This is becoming relevant for us as well as we'' port barebox to the
BeagleV. Our intention is to get the other Qemu platforms running
as well in preparation for actual hardware support.
>
> * https://github.com/litex-hub/barebox/tree/20200727.litex-vexriscv-linux
> contains litex SoC with RISC-V 32-bit CPU core support.
> It can run linux on Arty, please see
> https://github.com/enjoy-digital/litex/issues/413#issuecomment-609047340
>
> It seems, that ethernet driver needs update: https://github.com/litex-hub/barebox/issues/1
Thanks for the heads up. I will take a look at your rebased branches,
once they are available.
> I suppose that you can add 'bootm: add RISC-V image type' patch to your series
> (I'll send you the patch in a few minutes). The patch used in the litex series.
Sascha just picked it up.
Cheers,
Ahmad
>
>
>> With these changes applied, barebox can now generate images that can
>> be booted on qemu/tinyemu virt32 and virt64 machines.
>>
>> The boards have clocksource, virtio, cfi-flash, reboot and poweroff
>> support.
>>
>> Cheers,
>> Ahmad Fatoum (18):
>> partitions: don't allocate dma capable memory
>> images: make BOARD_ARM_GENERIC_DT available for other arches
>> ARM: rename CONFIG_ARM_USE_COMPRESSED_DTB to CONFIG_USE_COMPRESSED_DTB
>> ARM: aarch64: ommit unused label in assembly
>> serial: virtio-console: depend on, but don't select VIRTIO
>> filetype: detect RISC-V Linux kernel image
>> asm: unaligned: don't do unaligned accesses
>> RISC-V: debug_ll: ns16550: align C access size with assembly's
>> RISC-V: drop duplicate or unneeded cflags
>> RISC-V: add cacheless HAS_DMA support
>> RISC-V: erizo: move to arch/riscv/boards/erizo
>> RISC-V: import Linux' optimized string functions
>> RISC-V: implement PBL and relocation support
>> RISC-V: erizo: migrate to PBL
>> RISC-V: support symbol names in barebox image
>> RISC-V: add generic DT image
>> clocksource: add driver for RISC-V CLINT timer
>> power: reset: add drivers for generic syscon reset and poweroff
>>
>> Rouven Czerwinski (2):
>> RISC-V: add 64-bit support
>> RISC-V: add Qemu virt support
>>
>> Documentation/boards/riscv.rst | 72 ++++++-
>> Makefile | 1 +
>> arch/arm/Kconfig | 9 +-
>> arch/arm/cpu/start.c | 2 +-
>> arch/arm/lib64/runtime-offset.S | 2 +-
>> arch/arm/mach-at91/Kconfig | 2 +-
>> arch/arm/mach-imx/Kconfig | 26 +--
>> arch/arm/mach-omap/Kconfig | 2 +-
>> arch/riscv/Kconfig | 66 +++++--
>> arch/riscv/Makefile | 34 ++--
>> arch/riscv/boards/Makefile | 2 +
>> arch/riscv/boards/erizo/Makefile | 3 +
>> arch/riscv/boards/erizo/lowlevel.c | 18 ++
>> arch/riscv/boot/Makefile | 5 +-
>> arch/riscv/boot/board-dt-2nd-entry.S | 26 +++
>> arch/riscv/boot/board-dt-2nd.c | 29 +++
>> arch/riscv/boot/dtb.c | 25 ---
>> arch/riscv/boot/entry.c | 33 ++++
>> arch/riscv/boot/entry.h | 15 ++
>> arch/riscv/boot/entry_ll.S | 15 ++
>> arch/riscv/boot/main_entry.c | 35 ----
>> arch/riscv/boot/start.S | 68 -------
>> arch/riscv/boot/start.c | 197 +++++++++++++++++++
>> arch/riscv/boot/uncompress.c | 74 +++++++
>> arch/riscv/configs/erizo_generic_defconfig | 5 -
>> arch/riscv/configs/virt32_defconfig | 117 +++++++++++
>> arch/riscv/configs/virt64_defconfig | 118 +++++++++++
>> arch/riscv/dts/Makefile | 9 +-
>> arch/riscv/include/asm/barebox-riscv.h | 101 ++++++++++
>> arch/riscv/include/asm/common.h | 10 +-
>> arch/riscv/include/asm/debug_ll_ns16550.h | 16 +-
>> arch/riscv/include/asm/dma.h | 44 +++++
>> arch/riscv/include/asm/elf.h | 8 +-
>> arch/riscv/include/asm/image.h | 65 ++++++
>> arch/riscv/include/asm/linkage.h | 4 +
>> arch/riscv/include/asm/sections.h | 15 ++
>> arch/riscv/include/asm/string.h | 21 +-
>> arch/riscv/include/asm/types.h | 8 +-
>> arch/riscv/include/asm/unaligned.h | 16 +-
>> arch/riscv/lib/Makefile | 6 +-
>> arch/riscv/lib/barebox.lds.S | 55 ++++--
>> arch/riscv/lib/dtb.c | 26 +++
>> arch/riscv/lib/memcpy.S | 108 ++++++++++
>> arch/riscv/lib/memmove.S | 64 ++++++
>> arch/riscv/lib/memset.S | 113 +++++++++++
>> arch/riscv/lib/pbl.lds.S | 88 +++++++++
>> arch/riscv/lib/reloc.c | 64 ++++++
>> arch/riscv/lib/runtime-offset.S | 12 ++
>> arch/riscv/lib/sections.c | 9 +
>> arch/riscv/lib/setupc.S | 55 ++++++
>> arch/riscv/mach-virt/Makefile | 3 +
>> arch/riscv/mach-virt/include/mach/debug_ll.h | 25 +++
>> common/Kconfig | 8 +-
>> common/filetype.c | 3 +
>> common/partitions.c | 5 +-
>> common/partitions/dos.c | 7 +-
>> common/partitions/efi.c | 1 -
>> drivers/clocksource/Kconfig | 7 +
>> drivers/clocksource/Makefile | 1 +
>> drivers/clocksource/timer-clint.c | 98 +++++++++
>> drivers/power/reset/Kconfig | 14 ++
>> drivers/power/reset/Makefile | 2 +
>> drivers/power/reset/syscon-poweroff.c | 76 +++++++
>> drivers/power/reset/syscon-reboot.c | 92 +++++++++
>> drivers/serial/Kconfig | 2 +-
>> images/Makefile | 8 +-
>> images/Makefile.erizo | 12 ++
>> include/dma.h | 1 +
>> include/filetype.h | 1 +
>> pbl/Kconfig | 6 +-
>> scripts/.gitignore | 1 +
>> scripts/Makefile | 1 +
>> scripts/Makefile.lib | 11 ++
>> scripts/prelink-riscv.c | 122 ++++++++++++
>> scripts/prelink-riscv.inc | 123 ++++++++++++
>> 75 files changed, 2285 insertions(+), 263 deletions(-)
>> create mode 100644 arch/riscv/boards/Makefile
>> create mode 100644 arch/riscv/boards/erizo/Makefile
>> create mode 100644 arch/riscv/boards/erizo/lowlevel.c
>> create mode 100644 arch/riscv/boot/board-dt-2nd-entry.S
>> create mode 100644 arch/riscv/boot/board-dt-2nd.c
>> delete mode 100644 arch/riscv/boot/dtb.c
>> create mode 100644 arch/riscv/boot/entry.c
>> create mode 100644 arch/riscv/boot/entry.h
>> create mode 100644 arch/riscv/boot/entry_ll.S
>> delete mode 100644 arch/riscv/boot/main_entry.c
>> delete mode 100644 arch/riscv/boot/start.S
>> create mode 100644 arch/riscv/boot/start.c
>> create mode 100644 arch/riscv/boot/uncompress.c
>> create mode 100644 arch/riscv/configs/virt32_defconfig
>> create mode 100644 arch/riscv/configs/virt64_defconfig
>> create mode 100644 arch/riscv/include/asm/barebox-riscv.h
>> create mode 100644 arch/riscv/include/asm/dma.h
>> create mode 100644 arch/riscv/include/asm/image.h
>> create mode 100644 arch/riscv/lib/dtb.c
>> create mode 100644 arch/riscv/lib/memcpy.S
>> create mode 100644 arch/riscv/lib/memmove.S
>> create mode 100644 arch/riscv/lib/memset.S
>> create mode 100644 arch/riscv/lib/pbl.lds.S
>> create mode 100644 arch/riscv/lib/reloc.c
>> create mode 100644 arch/riscv/lib/runtime-offset.S
>> create mode 100644 arch/riscv/lib/sections.c
>> create mode 100644 arch/riscv/lib/setupc.S
>> create mode 100644 arch/riscv/mach-virt/Makefile
>> create mode 100644 arch/riscv/mach-virt/include/mach/debug_ll.h
>> create mode 100644 drivers/clocksource/timer-clint.c
>> create mode 100644 drivers/power/reset/syscon-poweroff.c
>> create mode 100644 drivers/power/reset/syscon-reboot.c
>> create mode 100644 images/Makefile.erizo
>> create mode 100644 scripts/prelink-riscv.c
>> create mode 100644 scripts/prelink-riscv.inc
>>
>> --
>> 2.29.2
>>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 36+ messages in thread