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From: Michael Tretter <m.tretter@pengutronix.de>
To: barebox@lists.infradead.org
Cc: m.tretter@pengutronix.de
Subject: [PATCH 6/7] net: phy: dp83867: read status from PHY status register PHYSTS
Date: Fri, 19 Mar 2021 14:10:15 +0100	[thread overview]
Message-ID: <20210319131016.2612134-7-m.tretter@pengutronix.de> (raw)
In-Reply-To: <20210319131016.2612134-1-m.tretter@pengutronix.de>

From: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>

Read link status information in dp83867 specific register instead of
using `genphy_read_status()`.

In case of a link downshift, `genphy_read_status()` can return
`SPEED_1000` even if the negotiated speed is 100 Mbit.

A downshift can happen, if both link-partners are gigabit-capable, but
the connection supports only 100 MBit, for example because of a 100 MBit
PoE injector that connects only 2 of the 4 twisted pairs.

Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/net/phy/dp83867.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index dd769b4d3e38..c19f6ecba267 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -16,6 +16,7 @@
 #define DP83867_DEVADDR		MDIO_MMD_VEND2
 
 #define MII_DP83867_PHYCTRL	0x10
+#define MII_DP83867_PHYSTS	0x11
 #define MII_DP83867_MICR	0x12
 #define MII_DP83867_ISR		0x13
 #define MII_DP83867_CFG2	0x14
@@ -65,6 +66,11 @@
 #define DP83867_PHYCTRL_TXFIFO_SHIFT		14
 #define DP83867_PHYCR_RESERVED_MASK		BIT(11)
 
+/* PHY STS bits */
+#define DP83867_PHYSTS_SPEED_1000		BIT(15)
+#define DP83867_PHYSTS_SPEED_100		BIT(14)
+#define DP83867_PHYSTS_DUPLEX_FULL		BIT(13)
+
 /* RGMIIDCTL bits */
 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT	4
 
@@ -109,6 +115,35 @@ struct dp83867_private {
 	bool rxctrl_strap_quirk;
 };
 
+static int dp83867_read_status(struct phy_device *phydev)
+{
+	int status;
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	status = phy_read(phydev, MII_DP83867_PHYSTS);
+	if (status < 0)
+		return status;
+
+	phydev->speed = SPEED_10;
+	phydev->duplex = DUPLEX_HALF;
+
+	if (status & DP83867_PHYSTS_SPEED_1000)
+		phydev->speed = SPEED_1000;
+	else if (status & DP83867_PHYSTS_SPEED_100)
+		phydev->speed = SPEED_100;
+
+	if (status & DP83867_PHYSTS_DUPLEX_FULL)
+		phydev->duplex = DUPLEX_FULL;
+
+	phydev->pause = phydev->asym_pause = 0;
+
+	return 0;
+}
+
 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 {
 	struct dp83867_private *dp83867 = phydev->priv;
@@ -279,6 +314,7 @@ static struct phy_driver dp83867_driver[] = {
 		.drv.name = "TI DP83867",
 		.features = PHY_GBIT_FEATURES,
 		.config_init = dp83867_config_init,
+		.read_status = dp83867_read_status,
 	},
 };
 
-- 
2.29.2


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  parent reply	other threads:[~2021-03-19 13:12 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-19 13:10 [PATCH 0/7] net: phy: dp83867: cleanup and link downshift support Michael Tretter
2021-03-19 13:10 ` [PATCH 1/7] net: phy: dp83867: convert driver to spdx Michael Tretter
2021-03-19 13:10 ` [PATCH 2/7] net: phy: dp83867: fix checkpatch checks and warnings Michael Tretter
2021-03-19 13:10 ` [PATCH 3/7] net: phy: dp83867: remove useless call to genphy_config_aneg Michael Tretter
2021-03-19 13:10 ` [PATCH 4/7] net: phy: dp83867: simplify dp83867_config_init Michael Tretter
2021-03-19 13:10 ` [PATCH 5/7] net: phy: dp83867: remove explicit setting of cfg2 Michael Tretter
2021-03-19 13:10 ` Michael Tretter [this message]
2021-03-19 13:10 ` [PATCH 7/7] net: phy: dp83867: enable link downshift by default Michael Tretter
2021-03-22  5:02 ` [PATCH 0/7] net: phy: dp83867: cleanup and link downshift support Sascha Hauer

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