From: Antony Pavlov <antonynpavlov@gmail.com>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: barebox@lists.infradead.org, rcz@pengutronix.de
Subject: Re: [PATCH v2 14/20] RISC-V: erizo: migrate to PBL
Date: Sat, 20 Mar 2021 10:49:10 +0300 [thread overview]
Message-ID: <20210320104910.c14dc0ab27d06e653c29e1c1@gmail.com> (raw)
In-Reply-To: <20210316080505.19361-15-a.fatoum@pengutronix.de>
On Tue, 16 Mar 2021 09:04:59 +0100
Ahmad Fatoum <a.fatoum@pengutronix.de> wrote:
> We now have everything in place to migrate erizo to PBL.
> As currently, this is the only board, we can drop all non-PBL support
> in the same go.
...
> diff --git a/arch/riscv/boards/erizo/lowlevel.c b/arch/riscv/boards/erizo/lowlevel.c
> index f9c640c1123f..d9edb530b746 100644
> --- a/arch/riscv/boards/erizo/lowlevel.c
> +++ b/arch/riscv/boards/erizo/lowlevel.c
> @@ -1,35 +1,18 @@
> // SPDX-License-Identifier: GPL-2.0-only
> -/*
> - * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
> - *
> - * This file is part of barebox.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - */
>
> #include <common.h>
> -#include <memory.h>
> -#include <asm-generic/memory_layout.h>
> -#include <asm/sections.h>
> +#include <asm/barebox-riscv.h>
> +#include <debug_ll.h>
>
> -void main_entry(void);
> -
> -/**
> - * Called plainly from assembler code
> - *
> - * @note The C environment isn't initialized yet
> - */
> -void main_entry(void)
> +ENTRY_FUNCTION(start_erizo_generic, a0, a1, a2)
> {
> - /* clear the BSS first */
> - memset(__bss_start, 0x00, __bss_stop - __bss_start);
> + extern char __dtb_z_erizo_generic_start[];
> +
> + debug_ll_ns16550_init();
> + putc_ll('>');
>
> - mem_malloc_init((void *)MALLOC_BASE,
> - (void *)(MALLOC_BASE + MALLOC_SIZE - 1));
> + /* On POR, we are running from read-only memory here. */
>
> - start_barebox();
> + barebox_riscv_entry(0x80000000, SZ_8M,
> + __dtb_z_erizo_generic_start + get_runtime_offset());
> }
Let's see first instructions of resulting barebox-erizo-generic.img image:
barebox$ xxd -l 16 -e -g 4 ./images/barebox-erizo-generic.img
00000000: ff010113 00112623 900007b7 08700713 ....#&........p.
one can disassembly it:
barebox$ riscv64-linux-gnu-objdump -D images/start_erizo_generic.pbl | head -n 9
images/start_erizo_generic.pbl: file format elf32-littleriscv
Disassembly of section .text:
00000000 <start_erizo_generic>:
0: ff010113 addi sp,sp,-16
4: 00112623 sw ra,12(sp)
In general case 'sp' is in indeterminate state at start.
But despite this we use 'sp'-based address
for storing 'ra' register in memory! (sw ra,12(sp))
This behaviour can be fixed with adding __naked to ENTRY_FUNCTION macro definition:
--- a/arch/riscv/include/asm/barebox-riscv.h
+++ b/arch/riscv/include/asm/barebox-riscv.h
@@ -78,7 +78,7 @@ static inline unsigned long riscv_mem_barebox_image(unsigned long membase,
#define ENTRY_FUNCTION(name, arg0, arg1, arg2) \
void name (ulong a0, ulong a1, ulong a2); \
- void __section(.text_head_entry_##name) name (ulong a0, ulong a1, ulong a2)
+ void __section(.text_head_entry_##name) __naked name (ulong a0, ulong a1, ulong a2)
/*
* When using compressed images in conjunction with relocatable images
--
Best regards,
Antony Pavlov
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next prev parent reply other threads:[~2021-03-20 7:50 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-16 8:04 [PATCH v2 00/20] RISC-V: rework for PBL, VIRT and 64-Bit support Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 01/20] partitions: don't allocate dma capable memory Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 02/20] images: make BOARD_ARM_GENERIC_DT available for other arches Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 03/20] ARM: make ARM_USE_COMPRESSED_DTB " Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 04/20] ARM: aarch64: ommit unused label in assembly Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 05/20] serial: virtio-console: depend on, but don't select VIRTIO Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 06/20] filetype: detect RISC-V Linux kernel image Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 07/20] asm: unaligned: don't do unaligned accesses Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 08/20] RISC-V: debug_ll: ns16550: align C access size with assembly's Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 09/20] RISC-V: drop duplicate or unneeded cflags Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 10/20] RISC-V: add cacheless HAS_DMA support Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 11/20] RISC-V: erizo: move to arch/riscv/boards/erizo Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 12/20] RISC-V: import Linux' optimized string functions Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 13/20] RISC-V: implement PBL and relocation support Ahmad Fatoum
2021-03-16 8:04 ` [PATCH v2 14/20] RISC-V: erizo: migrate to PBL Ahmad Fatoum
2021-03-16 14:12 ` Antony Pavlov
2021-03-16 18:38 ` Ahmad Fatoum
2021-03-19 15:37 ` Antony Pavlov
2021-03-19 18:28 ` Ahmad Fatoum
2021-03-20 5:55 ` Antony Pavlov
2021-03-21 15:14 ` Ahmad Fatoum
2021-03-20 7:49 ` Antony Pavlov [this message]
2021-03-21 15:16 ` Ahmad Fatoum
2021-03-16 8:05 ` [PATCH v2 15/20] RISC-V: support symbol names in barebox image Ahmad Fatoum
2021-03-16 8:05 ` [PATCH v2 16/20] RISC-V: add 64-bit support Ahmad Fatoum
2021-03-16 8:05 ` [PATCH v2 17/20] RISC-V: add generic DT image Ahmad Fatoum
2021-03-16 8:05 ` [PATCH v2 18/20] clocksource: add driver for RISC-V and CLINT timers Ahmad Fatoum
2021-03-16 8:05 ` [PATCH v2 19/20] power: reset: add drivers for generic syscon reset and poweroff Ahmad Fatoum
2021-03-16 8:05 ` [PATCH v2 20/20] RISC-V: add Qemu virt support Ahmad Fatoum
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