From: Sascha Hauer <sha@pengutronix.de>
To: Ahmad Fatoum <a.fatoum@pengutronix.de>
Cc: barebox@lists.infradead.org, rcz@pengutronix.de
Subject: Re: [PATCH 04/12] RISC-V: support multi-image for all machines
Date: Mon, 3 May 2021 14:00:43 +0200 [thread overview]
Message-ID: <20210503120043.GG19819@pengutronix.de> (raw)
In-Reply-To: <c6ac7eb8-c664-85c9-8ddc-2b0b95266281@pengutronix.de>
On Mon, May 03, 2021 at 01:39:59PM +0200, Ahmad Fatoum wrote:
> Hello Sascha,
>
> On 03.05.21 13:33, Sascha Hauer wrote:
> > Hi Ahmad,
> >
> > This patch doesn't apply, I think there's something wrong with it.
> >
> > On Tue, Apr 27, 2021 at 10:23:01PM +0200, Ahmad Fatoum wrote:
> >> -config MACH_ERIZO
> >> - bool "erizo family"
> >> - select ARCH_RV32I
> >> - select HAS_DEBUG_LL
> >> - select HAS_NMON
> >> - select USE_COMPRESSED_DTB
> >> - select RISCV_M_MODE
> >> - select RISCV_TIMER
> >> -
> >> -config MACH_VIRT
> >> - bool "virt family"
> >> - select BOARD_RISCV_GENERIC_DT
> >> - select CLINT_TIMER
> >> - help
> >> - Generates an image tht can be be booted by QEMU. The image is called
> >> - barebox-dt-2nd.img
> >
> > This drops MACH_ERIZO and MACH_VIRT in favour of:
> >
> >> +config SOC_ERIZO
> >> + bool "Erizo SoC"
> >> + select ARCH_RV32I
> >> + select HAS_DEBUG_LL
> >> + select HAS_NMON
> >> + select USE_COMPRESSED_DTB
> >> + select RISCV_M_MODE
> >> + select RISCV_TIMER
> >> +
> >> +config SOC_VIRT
> >> + bool "QEMU Virt Machine"
> >> + select BOARD_RISCV_GENERIC_DT
> >> + select CLINT_TIMER
> >> + help
> >> + Generates an image tht can be be booted by QEMU. The image is called
> >> + barebox-dt-2nd.img
> >
> >> @@ -19,7 +19,7 @@ LDFLAGS_pbl += $(riscv-ldflags-y)
> >> cflags-y += $(riscv-cflags-y)
> >> LDFLAGS_barebox += -nostdlib
> >>
> >> -machine-$(CONFIG_MACH_ERIZO) := erizo
> >> +machine-$(CONFIG_SOC_ERIZO) := erizo
> >
> > for CONFIG_*_ERIZO this is changed here as well, but here the file has:
> >
> > machine-$(CONFIG_MACH_ERIZO) := erizo
> > machine-$(CONFIG_MACH_VIRT) := virt
> >
> > I think CONFIG_MACH_VIRT should be replaced here as well. I could fix
> > the obvious, but I am not sure how this happened and if this is the only
> > mistake here, so not applying this. Please resend.
>
> Sorry, I should have noted that this applied on top of the earlier RISC-V
> patches:
>
> https://lore.barebox.org/barebox/20210410110638.2106658-1-ahmad@a3f.at/
Ok, applied that one first.
Sascha
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next prev parent reply other threads:[~2021-05-03 12:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-27 20:22 [PATCH 01/12] clk: add SiFive PRCI clock controller support Ahmad Fatoum
2021-04-27 20:22 ` [PATCH 02/12] serial: implement SiFive UART support Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 03/12] debug_ll: support <asm/debug_ll.h> to get rid of mach directories Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 04/12] RISC-V: support multi-image for all machines Ahmad Fatoum
2021-05-03 11:33 ` Sascha Hauer
2021-05-03 11:39 ` Ahmad Fatoum
2021-05-03 12:00 ` Sascha Hauer [this message]
2021-04-27 20:23 ` [PATCH 05/12] RISC-V: erizo: restrict to RV32I Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 06/12] RISC-V: erizo: drop mach-erizo directory Ahmad Fatoum
2021-05-05 10:18 ` Antony Pavlov
2021-05-05 10:21 ` Ahmad Fatoum
2021-05-07 11:27 ` Antony Pavlov
2021-04-27 20:23 ` [PATCH 07/12] RISC-V: add SBI based cpuinfo Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 08/12] gpio: gpio-generic-platform: remove unused non-DT support Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 09/12] gpio: generic: sync with upstream Linux gpio-mmio driver Ahmad Fatoum
2021-05-06 23:45 ` Antony Pavlov
2021-04-27 20:23 ` [PATCH 10/12] gpio: add SiFive GPIO controller support Ahmad Fatoum
2021-04-27 20:23 ` [PATCH 11/12] net: macb: add SiFive support Ahmad Fatoum
2021-05-17 6:39 ` Sascha Hauer
2021-04-27 20:23 ` [PATCH 12/12] RISC-V: sifive: add HiFive board support Ahmad Fatoum
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