From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH 3/3] RISC-V: add Linux kernel boot support
Date: Tue, 4 May 2021 12:45:13 +0200 [thread overview]
Message-ID: <20210504104513.2640-3-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20210504104513.2640-1-a.fatoum@pengutronix.de>
The Linux kernel RISC-V header has the same structure as on ARM64. The
barebox header for the architecture also follows the same structure.
Add the architecture-specific glue for barebox to be able to boot both
RISC-V Linux and barebox.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/bootm.c | 51 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
create mode 100644 arch/riscv/lib/bootm.c
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 49750d576ae1..a399de7399cb 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_HAS_ARCH_SJLJ) += setjmp.o longjmp.o
obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o
obj-$(CONFIG_RISCV_SBI) += sbi.o
obj-$(CONFIG_CMD_RISCV_CPUINFO) += cpuinfo.o
+obj-$(CONFIG_BOOTM) += bootm.o
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
new file mode 100644
index 000000000000..b3e41de4a890
--- /dev/null
+++ b/arch/riscv/lib/bootm.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2018 Sascha Hauer <s.hauer@pengutronix.de>
+
+#include <common.h>
+#include <bootm.h>
+
+static int do_bootm_linux(struct image_data *data)
+{
+ void (*fn)(unsigned long a0, unsigned long dtb, unsigned long a2);
+ phys_addr_t devicetree;
+
+ fn = booti_load_image(data, &devicetree);
+ if (IS_ERR(fn))
+ return PTR_ERR(fn);
+
+ shutdown_barebox();
+
+ fn(0, devicetree, 0);
+
+ return -EINVAL;
+}
+
+static struct image_handler riscv_linux_handler = {
+ .name = "RISC-V Linux image",
+ .bootm = do_bootm_linux,
+ .filetype = filetype_riscv_linux_image,
+};
+
+static struct image_handler riscv_fit_handler = {
+ .name = "FIT image",
+ .bootm = do_bootm_linux,
+ .filetype = filetype_oftree,
+};
+
+static struct image_handler riscv_barebox_handler = {
+ .name = "RISC-V barebox image",
+ .bootm = do_bootm_linux,
+ .filetype = filetype_riscv_barebox_image,
+};
+
+static int riscv_register_image_handler(void)
+{
+ register_image_handler(&riscv_linux_handler);
+ register_image_handler(&riscv_barebox_handler);
+
+ if (IS_ENABLED(CONFIG_FITIMAGE))
+ register_image_handler(&riscv_fit_handler);
+
+ return 0;
+}
+late_initcall(riscv_register_image_handler);
--
2.29.2
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next prev parent reply other threads:[~2021-05-04 10:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-04 10:45 [PATCH 1/3] bootm: move ARM64 Linux image parsing to common directory Ahmad Fatoum
2021-05-04 10:45 ` [PATCH 2/3] RISC-V: asm: barebox-riscv-head: use load-offset of 0 Ahmad Fatoum
2021-05-04 10:45 ` Ahmad Fatoum [this message]
2021-05-07 7:28 ` [PATCH 1/3] bootm: move ARM64 Linux image parsing to common directory Sascha Hauer
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