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[193.232.173.35]) by smtp.gmail.com with ESMTPSA id a26sm1401901lfl.127.2021.05.07.10.41.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 10:41:37 -0700 (PDT) Date: Fri, 7 May 2021 20:41:36 +0300 From: Antony Pavlov To: Ahmad Fatoum Message-Id: <20210507204136.0289302048cc5edb0c06596b@gmail.com> In-Reply-To: <3683b25f-f736-6447-90f7-f62e1f9ccb64@pengutronix.de> References: <20210506220834.223350-1-antonynpavlov@gmail.com> <20210506220834.223350-2-antonynpavlov@gmail.com> <3683b25f-f736-6447-90f7-f62e1f9ccb64@pengutronix.de> X-Mailer: Sylpheed 3.7.0 (GTK+ 2.24.32; i686-pc-linux-gnu) Mime-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210507_104140_520513_E5D6CA97 X-CRM114-Status: GOOD ( 33.80 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: barebox@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "barebox" X-SA-Exim-Connect-IP: 2001:8b0:10b:1:d65d:64ff:fe57:4e05 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-2.6 required=4.0 tests=AWL,BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: [PATCH v2 01/11] clocksource: timer-riscv: select CSR from device tree X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) On Fri, 7 May 2021 13:34:30 +0200 Ahmad Fatoum wrote: > Hello Antony, > = > On 07.05.21 00:08, Antony Pavlov wrote: > > barebox timer-riscv driver supports one of user counters: > > = > > * 'cycle', counter for RDCYCLE instruction (CSR 0xc00); > > * 'time', timer for RDTIME instruction (CSR 0xc01). > > = > > At the moment in S-mode timer-riscv uses the 'cycle' counter, > > and in M-mode timer-riscv uses the 'time' timer. > = > Other way round, right? cycle for M-Mode, time for S-Mode? Yes, you are right, my bad. > > = > > Alas picorv32 CPU core supports only the 'cycle' counter. > > VexRiscV CPU core supports only the 'time' timer. > > = > > This patch makes it possible to use the 'time' timer > > for VexRiscV CPU in M-mode. > = > Is that allowed by the ISA? To provide time, but not cycle? > Can VexRiscV boot Linux? If so, how does Linux handle lack > of this CSR? Here is an unobvious answer for all these questions at once. The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Document Version 20190608-Priv-MSU-Ratified states that << Attempts to access a non-existent CSR raise an illegal instruction excep= tion >> So you can even realize in hardware very few CSR for exception handling (ms= tatus, mcause, mtvec, mie, mepc) and try to emulate all other CSR in software ! As a result exception handler for VexRiscv emulates access to 'cycle' CSR (= RDCYCLE pseudo-op) by reading the 'time' CSR ! = Please see https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/c/emu= lator/src/main.c#L239 opensbi do near the same ! Please see https://github.com/riscv/opensbi/blob= /master/lib/sbi/sbi_emulate_csr.c#L64 Can VexRiscV boot Linux? Yes, it can boot linux! Please see this demo: https://asciinema.org/a/7fLu84ytgtVd3rjPm7Li3GD4r In this demo barebox loads emulator.bin into the RAM. This emulator.bin realizes SBI for linux kernel and emulates all missed fea= tures necessary for running linux. > = > > Signed-off-by: Antony Pavlov > > --- > > arch/riscv/cpu/time.c | 7 +++++++ > > arch/riscv/dts/erizo.dtsi | 2 ++ > > arch/riscv/include/asm/timer.h | 1 + > > drivers/clocksource/timer-riscv.c | 19 ++++++++----------- > > 4 files changed, 18 insertions(+), 11 deletions(-) > > = > > diff --git a/arch/riscv/cpu/time.c b/arch/riscv/cpu/time.c > > index 39bb6a5112..59c8ca61d6 100644 > > --- a/arch/riscv/cpu/time.c > > +++ b/arch/riscv/cpu/time.c > > @@ -18,6 +18,7 @@ > > #include > > = > > unsigned long riscv_timebase; > > +unsigned long riscv_use_csr_cycle; > > = > > int timer_init(void) > > { > > @@ -32,6 +33,12 @@ int timer_init(void) > > = > > riscv_timebase =3D prop; > > = > > + if (of_property_read_bool(cpu, "csr-cycle")) { > > + riscv_use_csr_cycle =3D 1; > > + } else { > > + riscv_use_csr_cycle =3D 0; > > + } > > + > = > Any reason this couldn't happen in driver probe? Because we already have riscv_timebase parse routine outside of driver prob= e. I tryed to avoid code duplication. Why we couldn't parse riscv_timebase in driver probe? > I'd also prefer another name, e.g. barebox,use-csr-cycle ? Yes, barebox,use-csr-cycle is a better name. > > of_platform_populate(cpu, NULL, NULL); > > = > > return 0; > > diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi > > index 228711bd69..b3ccf281f2 100644 > > --- a/arch/riscv/dts/erizo.dtsi > > +++ b/arch/riscv/dts/erizo.dtsi > > @@ -22,6 +22,8 @@ > > = > > timebase-frequency =3D <24000000>; > > = > > + csr-cycle; > > + > > cpu@0 { > > device_type =3D "cpu"; > > compatible =3D "cliffordwolf,picorv32", "riscv"; > > diff --git a/arch/riscv/include/asm/timer.h b/arch/riscv/include/asm/ti= mer.h > > index 1f78ef4c00..555b3f5989 100644 > > --- a/arch/riscv/include/asm/timer.h > > +++ b/arch/riscv/include/asm/timer.h > > @@ -5,5 +5,6 @@ > > = > > int timer_init(void); > > extern unsigned long riscv_timebase; > > +extern unsigned long riscv_use_csr_cycle; > > = > > #endif /* _ASM_RISCV_DELAY_H */ > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/ti= mer-riscv.c > > index ef67cff475..c0deed40eb 100644 > > --- a/drivers/clocksource/timer-riscv.c > > +++ b/drivers/clocksource/timer-riscv.c > > @@ -13,7 +13,7 @@ > > #include > > #include > > = > > -static u64 notrace riscv_timer_get_count_sbi(void) > > +static u64 notrace riscv_timer_get_count_time(void) > > { > > __maybe_unused u32 hi, lo; > > = > > @@ -28,7 +28,7 @@ static u64 notrace riscv_timer_get_count_sbi(void) > > return ((u64)hi << 32) | lo; > > } > > = > > -static u64 notrace riscv_timer_get_count_rdcycle(void) > > +static u64 notrace riscv_timer_get_count_cycle(void) > > { > > __maybe_unused u32 hi, lo; > > = > > @@ -43,16 +43,7 @@ static u64 notrace riscv_timer_get_count_rdcycle(voi= d) > > return ((u64)hi << 32) | lo; > > } > > = > > -static u64 notrace riscv_timer_get_count(void) > > -{ > > - if (IS_ENABLED(CONFIG_RISCV_SBI)) > > - return riscv_timer_get_count_sbi(); > > - else > > - return riscv_timer_get_count_rdcycle(); > > -} > > - > > static struct clocksource riscv_clocksource =3D { > > - .read =3D riscv_timer_get_count, > > .mask =3D CLOCKSOURCE_MASK(64), > > .priority =3D 100, > > }; > > @@ -61,6 +52,12 @@ static int riscv_timer_init(struct device_d* dev) > > { > > dev_info(dev, "running at %lu Hz\n", riscv_timebase); > > = > > + if (riscv_use_csr_cycle) { > > + riscv_clocksource.read =3D riscv_timer_get_count_cycle; > > + } else { > > + riscv_clocksource.read =3D riscv_timer_get_count_time; > > + } > > + > > riscv_clocksource.mult =3D clocksource_hz2mult(riscv_timebase, riscv_= clocksource.shift); > > = > > return init_clock(&riscv_clocksource); > > = > = > -- = > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- = Best regards, =A0 Antony Pavlov _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox