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From: Sascha Hauer <>
To: Barebox List <>
Subject: [PATCH 1/4] watchdog: dw_wdt: Write counter restart register
Date: Thu, 10 Jun 2021 15:06:10 +0200	[thread overview]
Message-ID: <> (raw)

At least some variants of the dwc watchdog controllers need the
value 0x76 written to the counter restart register to actually
take the value written to the Timeout range register. Happened
on Rockchip RK3568, without this the watchdog immediately resets
the system.

Signed-off-by: Sascha Hauer <>
 drivers/watchdog/dw_wdt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c
index 17771c7126..bc5d4a889a 100644
--- a/drivers/watchdog/dw_wdt.c
+++ b/drivers/watchdog/dw_wdt.c
@@ -111,6 +111,9 @@ static int dw_wdt_set_timeout(struct watchdog *wdd, unsigned int top_s)
 	writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
 	       dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
+	       dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
 	return 0;

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             reply	other threads:[~2021-06-10 13:08 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-10 13:06 Sascha Hauer [this message]
2021-06-10 13:06 ` [PATCH 2/4] watchdog: dw_wdt: Detect if running initially Sascha Hauer
2021-06-10 13:06 ` [PATCH 3/4] watchdog: dw_wdt: set maximum timeout Sascha Hauer
2021-06-10 13:06 ` [PATCH 4/4] watchdog: dw_wdt: denote message to debug level Sascha Hauer

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