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From: Sascha Hauer <sha@pengutronix.de>
To: "Barbier, Renaud" <renaud.barbier@abaco.com>
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>,
	Barebox List <barebox@lists.infradead.org>
Subject: Re: NXP Layerscape
Date: Tue, 15 Jun 2021 10:49:22 +0200	[thread overview]
Message-ID: <20210615084922.GC9782@pengutronix.de> (raw)
In-Reply-To: <MN2PR16MB3135E10CC5F4B532EDA547D291319@MN2PR16MB3135.namprd16.prod.outlook.com>

On Mon, Jun 14, 2021 at 03:16:27PM +0000, Barbier, Renaud wrote:
> I am a bit confused on how the QSPI image is built.
> From images/Makefile.layerscape
> $(obj)/barebox-ls1046ardb-qspi.image: $(obj)/start_ls1046ardb.pblb \
>           $(board)/ls1046ardb/ls1046ardb_rcw_qspi.cfg \
>          $(board)/ls1046ardb/ls1046ardb_pbi.cfg
> 
> It makes use of the file ls1046ardb/ls1046ardb_pbi.cfg not ls1046ardb/ls1046ardb_qspi_pbi.cfg. 
> ls1046a_qspi_pbi.cfg contains an endian swap that I can see in the U-boot rcw+pbi data.
> 
> When I take an hex dump of the barebox-ls1046ardb-qspi.image, I see that the scratchpad register 2 (BOOTLOCPTR) in the PBI section points to 0x10000000 (as in the PBI file), not the PBL address start address.
> How can this work?

Let's have a look at the differences between both files:

> --- arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg       2021-05-04 10:21:05.961665227 +0200
> +++ arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg  2021-05-04 10:21:05.961665227 +0200
> @@ -1,3 +1,5 @@
> +#QSPI clk
> +0957015c 40100000

Not sure about this one. It might be not necessary because the SPI clock
must have a sane value without it, in the end this data has just been
read from SPI flash.

>  #Configure Scratch register
>  09570600 00000000
>  09570604 10000000
> @@ -20,3 +22,5 @@
>  09570158 00001000
>  #flush PBI data
>  096100c0 000fffff
> +#Change endianness
> +09550000 000f400c

This is the weird one. The QSPI read data is memory mapped in some SRAM
where it is directly executed. Now the snippet above changes the
endianess of the read data, so that beginning after the line above the
rest of the data must be written to flash with a different endianess. In
barebox we do that differently. Instead of changing the endianess of the
controller we change the endianess of the data written to flash. This
type of image is generated with the -s option to the pblimage tool.
This means we don't need a special QSPI variant for the PBI file.
arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg could be removed,
it's there as a leftover from the files imported from U-Boot.

Sascha

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Pengutronix e.K.                           |                             |
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  reply	other threads:[~2021-06-15 17:22 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-10 13:49 Barbier, Renaud
2021-06-10 14:09 ` Ahmad Fatoum
2021-06-10 17:08   ` Barbier, Renaud
     [not found]   ` <MN2PR16MB31359FACA75C0F54E7672C5691359@MN2PR16MB3135.namprd16.prod.outlook.com>
     [not found]     ` <33d59215-cd45-71cc-5f0b-e26d0a43e9d1@pengutronix.de>
     [not found]       ` <MN2PR16MB31352F2590A920BB39ACC17F91359@MN2PR16MB3135.namprd16.prod.outlook.com>
2021-06-10 16:35         ` Ahmad Fatoum
     [not found]           ` <MN2PR16MB3135880DC913705C5BE493BB91359@MN2PR16MB3135.namprd16.prod.outlook.com>
2021-06-10 16:50             ` Ahmad Fatoum
     [not found]       ` <MN2PR16MB3135787D6B3FCF98CAA0F53591359@MN2PR16MB3135.namprd16.prod.outlook.com>
2021-06-11  8:29         ` Ahmad Fatoum
2021-06-14 15:16   ` Barbier, Renaud
2021-06-15  8:49     ` Sascha Hauer [this message]
2021-06-15 19:02       ` Barbier, Renaud

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