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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:e::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.3 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.2 Subject: Re: NXP Layerscape X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) On Mon, Jun 14, 2021 at 03:16:27PM +0000, Barbier, Renaud wrote: > I am a bit confused on how the QSPI image is built. > From images/Makefile.layerscape > $(obj)/barebox-ls1046ardb-qspi.image: $(obj)/start_ls1046ardb.pblb \ > $(board)/ls1046ardb/ls1046ardb_rcw_qspi.cfg \ > $(board)/ls1046ardb/ls1046ardb_pbi.cfg > > It makes use of the file ls1046ardb/ls1046ardb_pbi.cfg not ls1046ardb/ls1046ardb_qspi_pbi.cfg. > ls1046a_qspi_pbi.cfg contains an endian swap that I can see in the U-boot rcw+pbi data. > > When I take an hex dump of the barebox-ls1046ardb-qspi.image, I see that the scratchpad register 2 (BOOTLOCPTR) in the PBI section points to 0x10000000 (as in the PBI file), not the PBL address start address. > How can this work? Let's have a look at the differences between both files: > --- arch/arm/boards/ls1046ardb/ls1046ardb_pbi.cfg 2021-05-04 10:21:05.961665227 +0200 > +++ arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg 2021-05-04 10:21:05.961665227 +0200 > @@ -1,3 +1,5 @@ > +#QSPI clk > +0957015c 40100000 Not sure about this one. It might be not necessary because the SPI clock must have a sane value without it, in the end this data has just been read from SPI flash. > #Configure Scratch register > 09570600 00000000 > 09570604 10000000 > @@ -20,3 +22,5 @@ > 09570158 00001000 > #flush PBI data > 096100c0 000fffff > +#Change endianness > +09550000 000f400c This is the weird one. The QSPI read data is memory mapped in some SRAM where it is directly executed. Now the snippet above changes the endianess of the read data, so that beginning after the line above the rest of the data must be written to flash with a different endianess. In barebox we do that differently. Instead of changing the endianess of the controller we change the endianess of the data written to flash. This type of image is generated with the -s option to the pblimage tool. This means we don't need a special QSPI variant for the PBI file. arch/arm/boards/ls1046ardb/ls1046ardb_qspi_pbi.cfg could be removed, it's there as a leftover from the files imported from U-Boot. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox