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From: Michael Tretter <>
Cc: Michael Graichen <>
Subject: [PATCH 4/5] mci: arasan: wait for XFER_COMPLETE for busy response
Date: Wed, 16 Jun 2021 09:39:56 +0200	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

I observed errors on the ZynqMP during reading the EXT_CSD registers
using CMD8. The Zynq UltraScale+ Device TRM UG1085 (v2.2) p. 777 states
that the driver shall wait 2 ms after sending CMD6 for setting a EXT_CSD

The JEDEC Standard No. 84-A43 p. 35 does not specify the delay but
states that CMD6 expects an R1b response and that the host has to wait
until the busy signal is de-asserted. This is signaled via the

Wait for the XFER_COMPLETE interrupt after sending a command that
expects an R1b response.

Signed-off-by: Michael Tretter <>
 drivers/mci/arasan-sdhci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mci/arasan-sdhci.c b/drivers/mci/arasan-sdhci.c
index 732f838d8395..d45f9184cd1d 100644
--- a/drivers/mci/arasan-sdhci.c
+++ b/drivers/mci/arasan-sdhci.c
@@ -193,6 +193,8 @@ static int arasan_sdhci_send_cmd(struct mci_host *mci, struct mci_cmd *cmd,
 	if (data && data->flags == MMC_DATA_READ)
+	if (cmd->resp_type & MMC_RSP_BUSY)
 				cmd, data, false, &command, &xfer);

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  parent reply	other threads:[~2021-06-16  7:41 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-16  7:39 [PATCH 0/5] Cleanup and fix arasan-sdhci Michael Tretter
2021-06-16  7:39 ` [PATCH 1/5] mci: mci-core: respect disable-wp property Michael Tretter
2021-06-16  7:39 ` [PATCH 2/5] mci: arasan: fix most checkpatch warnings Michael Tretter
2021-06-16  7:39 ` [PATCH 3/5] mci: arasan: remove duplicate stop clock Michael Tretter
2021-06-16  7:39 ` Michael Tretter [this message]
2021-06-16  7:39 ` [PATCH 5/5] ARM: zynqmp: defconfig: enable MCI_ARASAN Michael Tretter
2021-06-16  7:52 ` [PATCH 0/5] Cleanup and fix arasan-sdhci Sascha Hauer

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