From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 02/12] clk: rockchip rk3568: Initialize clocks
Date: Mon, 21 Jun 2021 11:27:52 +0200 [thread overview]
Message-ID: <20210621092802.27275-3-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20210621092802.27275-1-s.hauer@pengutronix.de>
This initializes the rk3568 clocks in the way U-Boot initializes them as
well.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210615141641.31577-3-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/rockchip/clk-rk3568.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 4605158500..620d932a09 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1623,6 +1623,12 @@ static void __init rk3568_pmu_clk_init(struct device_node *np)
ARRAY_SIZE(rk3568_pmucru_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
+
+ clk_name_set_parent("ppll", "pll_ppll");
+ clk_name_set_parent("clk_rtc_32k", "clk_rtc32k_frac");
+ clk_name_set_rate("clk_rtc_32k", 32768);
+ clk_name_set_rate("pclk_pmu", 100000000);
+ clk_name_set_rate("pll_ppll", 200000000);
}
static void __init rk3568_clk_init(struct device_node *np)
@@ -1660,6 +1666,28 @@ static void __init rk3568_clk_init(struct device_node *np)
ARRAY_SIZE(rk3568_cru_critical_clocks));
rockchip_clk_of_add_provider(np, ctx);
+
+ clk_name_set_parent("npll", "pll_npll");
+ clk_name_set_parent("vpll", "pll_vpll");
+ clk_name_set_parent("pclk_bus", "gpll_100m");
+ clk_name_set_parent("clk_sdmmc0", "cpll_50m");
+ clk_name_set_parent("cclk_emmc", "gpll_200m");
+
+ clk_name_set_rate("pll_cpll", 1000000000);
+ clk_name_set_rate("pll_gpll", 1188000000);
+ clk_name_set_rate("armclk", 600000000);
+ clk_name_set_rate("aclk_bus", 150000000);
+ clk_name_set_rate("pclk_bus", 100000000);
+ clk_name_set_rate("aclk_top_high", 300000000);
+ clk_name_set_rate("aclk_top_low", 200000000);
+ clk_name_set_rate("hclk_top", 150000000);
+ clk_name_set_rate("pclk_top", 100000000);
+ clk_name_set_rate("aclk_perimid", 300000000);
+ clk_name_set_rate("hclk_perimid", 150000000);
+ clk_name_set_rate("pll_npll", 1200000000);
+ clk_name_set_rate("pll_apll", 816000000);
+
+ clk_name_set_parent("pclk_top", "gpll_100m");
}
struct clk_rk3568_inits {
--
2.29.2
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next prev parent reply other threads:[~2021-06-21 9:29 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-21 9:27 [PATCH v2 00/12] Rockchip RK3568 support Sascha Hauer
2021-06-21 9:27 ` [PATCH 01/12] clk: Add clk_name_* functions Sascha Hauer
2021-06-21 9:27 ` Sascha Hauer [this message]
2021-06-21 9:27 ` [PATCH 03/12] filetype: Add Rockchip boot image type Sascha Hauer
2021-06-21 9:27 ` [PATCH 04/12] ARM: Rockchip: Add rkimage tool Sascha Hauer
2021-06-21 9:27 ` [PATCH 05/12] ARM: Add relocate_to_adr_full() Sascha Hauer
2021-06-21 9:27 ` [PATCH 06/12] ARM: Rockchip: Add rk3568 dtsi files Sascha Hauer
2021-06-21 9:27 ` [PATCH 07/12] ARM: Rockchip: Add rk3568 support Sascha Hauer
2021-06-21 9:27 ` [PATCH 08/12] ARM: Add atf common support Sascha Hauer
2021-06-21 9:27 ` [PATCH 09/12] ARM: rockchip: Add bootm handler for RKNS images Sascha Hauer
2021-06-21 9:28 ` [PATCH 10/12] ARM: Rockchip: Add rk3568 evb board support Sascha Hauer
2021-06-21 9:28 ` [PATCH 11/12] Add rockchip_v8_defconfig Sascha Hauer
2021-06-21 9:28 ` [PATCH 12/12] fixup! clk: Rockchip: Add rk3568 clk support Sascha Hauer
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