* [PATCH 1/2] clocksource: add ARMv7-M SysTick driver
@ 2022-01-31 8:11 Ahmad Fatoum
2022-01-31 8:11 ` [PATCH 2/2] clocksource: add STM32 Timer driver Ahmad Fatoum
2022-01-31 10:23 ` [PATCH 1/2] clocksource: add ARMv7-M SysTick driver Sascha Hauer
0 siblings, 2 replies; 3+ messages in thread
From: Ahmad Fatoum @ 2022-01-31 8:11 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
The SysTick is a simple 24-bit system timer that's required for ARMv7-M
implementations. Add a clocksource driver for it for Cortex-M system
support.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clocksource/Kconfig | 5 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/armv7m_systick.c | 87 ++++++++++++++++++++++++++++
3 files changed, 93 insertions(+)
create mode 100644 drivers/clocksource/armv7m_systick.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index c6ca72d4e927..9fae1f2d352e 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -115,4 +115,9 @@ config CLINT_TIMER
This option enables the CLINT timer for RISC-V systems. The CLINT
driver is usually used for NoMMU RISC-V systems.
+config ARMV7M_SYSTICK
+ bool "Support for the ARMv7M system timer" if COMPILE_TEST
+ help
+ This option enables support for the ARMv7M system timer unit.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 21fd83a0930b..a4a7b84fae0c 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_CLOCKSOURCE_TI_DM) += timer-ti-dm.o
obj-$(CONFIG_CLOCKSOURCE_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
+obj-$(CONFIG_ARMV7M_SYSTICK) += armv7m_systick.o
diff --git a/drivers/clocksource/armv7m_systick.c b/drivers/clocksource/armv7m_systick.c
new file mode 100644
index 000000000000..5f9222c50b8a
--- /dev/null
+++ b/drivers/clocksource/armv7m_systick.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#define SYST_CSR 0x00
+#define SYST_RVR 0x04
+#define SYST_CVR 0x08
+#define SYST_CALIB 0x0c
+
+#define SYSTICK_CTRL_EN BIT(0)
+/* Clock source: 0 = Ref clock, 1 = CPU clock */
+#define SYSTICK_CTRL_CPU_CLK BIT(2)
+#define SYSTICK_CAL_NOREF BIT(31)
+
+#define SYSTICK_LOAD_RELOAD_MASK 0x00FFFFFF
+
+static __iomem void *systick_base;
+
+static u64 armv7m_systick_clocksource_read(void)
+{
+ return SYSTICK_LOAD_RELOAD_MASK - readl(systick_base + SYST_CVR);
+}
+
+static struct clocksource cs = {
+ .read = armv7m_systick_clocksource_read,
+ .mask = CLOCKSOURCE_MASK(24),
+ .shift = 0,
+};
+
+static int armv7m_systick_probe(struct device_d *dev)
+{
+ struct clk *clk = NULL;
+ u32 rate, cal;
+ int ret;
+
+ systick_base = dev_request_mem_region_err_null(dev, 0);
+ if (!systick_base)
+ return -ENOENT;
+
+ ret = of_property_read_u32(dev->device_node, "clock-frequency", &rate);
+ if (ret) {
+ clk = clk_get(dev, NULL);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ ret = clk_enable(clk);
+ if (ret)
+ return ret;
+
+ rate = clk_get_rate(clk);
+ if (!rate)
+ return -EINVAL;
+ }
+
+ writel_relaxed(SYSTICK_LOAD_RELOAD_MASK, systick_base + SYST_RVR);
+
+ cal = readl(&systick_base + SYST_CALIB);
+ if (cal & SYSTICK_CAL_NOREF)
+ writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, systick_base + SYST_CSR);
+ else
+ writel(SYSTICK_CTRL_EN, systick_base + SYST_CSR);
+
+ cs.mult = clocksource_hz2mult(rate, cs.shift);
+
+ return init_clock(&cs);
+}
+
+static struct of_device_id armv7m_systick_dt_ids[] = {
+ { .compatible = "arm,armv7m-systick", },
+ { }
+};
+
+static struct driver_d armv7m_systick_driver = {
+ .name = "armv7m-systick-timer",
+ .probe = armv7m_systick_probe,
+ .of_compatible = DRV_OF_COMPAT(armv7m_systick_dt_ids),
+};
+postcore_platform_driver(armv7m_systick_driver);
--
2.30.2
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^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH 2/2] clocksource: add STM32 Timer driver
2022-01-31 8:11 [PATCH 1/2] clocksource: add ARMv7-M SysTick driver Ahmad Fatoum
@ 2022-01-31 8:11 ` Ahmad Fatoum
2022-01-31 10:23 ` [PATCH 1/2] clocksource: add ARMv7-M SysTick driver Sascha Hauer
1 sibling, 0 replies; 3+ messages in thread
From: Ahmad Fatoum @ 2022-01-31 8:11 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
The STM32 timer is 32-bit and thus takes longer to wrap around than the
24-bit SysTick timer. Add a driver for it at a higher priority.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clocksource/Kconfig | 4 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-stm32.c | 122 ++++++++++++++++++++++++++++++
3 files changed, 127 insertions(+)
create mode 100644 drivers/clocksource/timer-stm32.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 9fae1f2d352e..e1bff23320de 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -120,4 +120,8 @@ config ARMV7M_SYSTICK
help
This option enables support for the ARMv7M system timer unit.
+config CLKSRC_STM32
+ bool "Clocksource for STM32 SoCs"
+ depends on OFDEVICE && (ARCH_STM32 || COMPILE_TEST)
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index a4a7b84fae0c..eceaa990d43d 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_CLOCKSOURCE_TI_32K) += timer-ti-32k.o
obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
obj-$(CONFIG_ARMV7M_SYSTICK) += armv7m_systick.o
+obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o
diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c
new file mode 100644
index 000000000000..dec48fccf5a2
--- /dev/null
+++ b/drivers/clocksource/timer-stm32.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ */
+
+#include <common.h>
+#include <linux/clk.h>
+#include <clock.h>
+#include <init.h>
+#include <io.h>
+
+/* Timer control1 register */
+#define CR1_CEN BIT(0)
+#define CR1_ARPE BIT(7)
+
+/* Event Generation Register register */
+#define EGR_UG BIT(0)
+
+/* Auto reload register for free running config */
+#define GPT_FREE_RUNNING 0xFFFFFFFF
+
+#define MHZ_1 1000000
+
+struct stm32_timer_regs {
+ u32 cr1;
+ u32 cr2;
+ u32 smcr;
+ u32 dier;
+ u32 sr;
+ u32 egr;
+ u32 ccmr1;
+ u32 ccmr2;
+ u32 ccer;
+ u32 cnt;
+ u32 psc;
+ u32 arr;
+ u32 reserved;
+ u32 ccr1;
+ u32 ccr2;
+ u32 ccr3;
+ u32 ccr4;
+ u32 reserved1;
+ u32 dcr;
+ u32 dmar;
+ u32 tim2_5_or;
+};
+
+static struct stm32_timer_regs *timer_base;
+
+static u64 stm32_timer_read(void)
+{
+ return readl(&timer_base->cnt);
+}
+
+/* A bit obvious isn't it? */
+static struct clocksource cs = {
+ .read = stm32_timer_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 0,
+ .priority = 100,
+};
+
+static int stm32_timer_probe(struct device_d *dev)
+{
+ struct resource *iores;
+ struct clk *clk;
+ u32 rate, psc;
+ int ret;
+
+ iores = dev_request_mem_resource(dev, 0);
+ if (IS_ERR(iores))
+ return PTR_ERR(iores);
+
+ timer_base = IOMEM(iores->start);
+
+ clk = clk_get(dev, NULL);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ ret = clk_enable(clk);
+ if (ret)
+ return ret;
+
+ /* Stop the timer */
+ clrbits_le32(&timer_base->cr1, CR1_CEN);
+
+ /* get timer clock */
+ rate = clk_get_rate(clk);
+
+ /* we set timer prescaler to obtain a 1MHz timer counter frequency */
+ psc = (rate / MHZ_1) - 1;
+ writel(psc, &timer_base->psc);
+
+ /* Configure timer for auto-reload */
+ setbits_le32(&timer_base->cr1, CR1_ARPE);
+
+ /* load value for auto reload */
+ writel(GPT_FREE_RUNNING, &timer_base->arr);
+
+ /* start timer */
+ setbits_le32(&timer_base->cr1, CR1_CEN);
+
+ /* Update generation */
+ setbits_le32(&timer_base->egr, EGR_UG);
+
+ cs.mult = clocksource_hz2mult(MHZ_1, cs.shift);
+
+ return init_clock(&cs);
+}
+
+static struct of_device_id stm32_timer_dt_ids[] = {
+ { .compatible = "st,stm32-timer" },
+ { /* sentinel */ }
+};
+
+static struct driver_d stm32_timer_driver = {
+ .name = "stm32-timer",
+ .probe = stm32_timer_probe,
+ .of_compatible = stm32_timer_dt_ids,
+};
+postcore_platform_driver(stm32_timer_driver);
--
2.30.2
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 1/2] clocksource: add ARMv7-M SysTick driver
2022-01-31 8:11 [PATCH 1/2] clocksource: add ARMv7-M SysTick driver Ahmad Fatoum
2022-01-31 8:11 ` [PATCH 2/2] clocksource: add STM32 Timer driver Ahmad Fatoum
@ 2022-01-31 10:23 ` Sascha Hauer
1 sibling, 0 replies; 3+ messages in thread
From: Sascha Hauer @ 2022-01-31 10:23 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Mon, Jan 31, 2022 at 09:11:45AM +0100, Ahmad Fatoum wrote:
> The SysTick is a simple 24-bit system timer that's required for ARMv7-M
> implementations. Add a clocksource driver for it for Cortex-M system
> support.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> drivers/clocksource/Kconfig | 5 ++
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/armv7m_systick.c | 87 ++++++++++++++++++++++++++++
> 3 files changed, 93 insertions(+)
> create mode 100644 drivers/clocksource/armv7m_systick.c
Applied, thanks
Sascha
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