Re: [PATCH 1/2] ARM: stm32mp: ddrctl: add STM32MP131 RAM size querying support

[Sascha Hauer <sha@pengutronix.de>]

On Mon, Feb 21, 2022 at 11:36:24AM +0100, Ahmad Fatoum wrote:
> Full buswidth for STM32MP131 means 2 byte wide, not 4 as the memory bus
> is restricted to 16-bit. Teach barebox the difference.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  arch/arm/mach-stm32mp/ddrctrl.c               | 26 ++++++++++++++-----
>  arch/arm/mach-stm32mp/include/mach/revision.h |  8 ++++++
>  2 files changed, 27 insertions(+), 7 deletions(-)

Applied, thanks

Sascha

> 
> diff --git a/arch/arm/mach-stm32mp/ddrctrl.c b/arch/arm/mach-stm32mp/ddrctrl.c
> index 93996d0afc79..7f0944d7e77c 100644
> --- a/arch/arm/mach-stm32mp/ddrctrl.c
> +++ b/arch/arm/mach-stm32mp/ddrctrl.c
> @@ -9,6 +9,7 @@
>  #include <mach/ddr_regs.h>
>  #include <mach/entry.h>
>  #include <mach/stm32.h>
> +#include <mach/revision.h>
>  #include <asm/barebox-arm.h>
>  #include <asm/memory.h>
>  #include <pbl.h>
> @@ -62,7 +63,8 @@ enum ddrctrl_buswidth {
>  };
>  
>  static unsigned long ddrctrl_addrmap_ramsize(struct stm32mp1_ddrctl __iomem *d,
> -					     enum ddrctrl_buswidth buswidth)
> +					     enum ddrctrl_buswidth buswidth,
> +					     unsigned nb_bytes)
>  {
>  	unsigned banks = 3, cols = 12, rows = 16;
>  	u32 reg;
> @@ -99,21 +101,26 @@ static unsigned long ddrctrl_addrmap_ramsize(struct stm32mp1_ddrctl __iomem *d,
>  	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B13)) rows--;
>  	if (LINE_UNUSED(reg, ADDRMAP6_ROW_B12)) rows--;
>  
> -	return memory_sdram_size(cols, rows, BIT(banks), 4 / BIT(buswidth));
> +	return memory_sdram_size(cols, rows, BIT(banks), nb_bytes / BIT(buswidth));
>  }
>  
> -static inline unsigned ddrctrl_ramsize(void __iomem *base)
> +static inline unsigned ddrctrl_ramsize(void __iomem *base, unsigned nb_bytes)
>  {
>  	struct stm32mp1_ddrctl __iomem *ddrctl = base;
>  	unsigned buswidth = readl(&ddrctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
>  	buswidth >>= DDRCTRL_MSTR_DATA_BUS_WIDTH_SHIFT;
>  
> -	return ddrctrl_addrmap_ramsize(ddrctl, buswidth);
> +	return ddrctrl_addrmap_ramsize(ddrctl, buswidth, nb_bytes);
>  }
>  
>  static inline unsigned stm32mp1_ddrctrl_ramsize(void)
>  {
> -	return ddrctrl_ramsize(IOMEM(STM32_DDRCTL_BASE));
> +	u32 nb_bytes = 4;
> +
> +	if (cpu_stm32_is_stm32mp13())
> +		nb_bytes /= 2;
> +
> +	return ddrctrl_ramsize(IOMEM(STM32_DDRCTL_BASE), nb_bytes);
>  }
>  
>  void __noreturn stm32mp1_barebox_entry(void *boarddata)
> @@ -126,17 +133,22 @@ static int stm32mp1_ddr_probe(struct device_d *dev)
>  {
>  	struct resource *iores;
>  	void __iomem *base;
> +	unsigned long nb_bytes;
>  
>  	iores = dev_request_mem_resource(dev, 0);
>  	if (IS_ERR(iores))
>  		return PTR_ERR(iores);
>  	base = IOMEM(iores->start);
>  
> -	return arm_add_mem_device("ram0", STM32_DDR_BASE, ddrctrl_ramsize(base));
> +	nb_bytes = (unsigned long)device_get_match_data(dev);
> +
> +	return arm_add_mem_device("ram0", STM32_DDR_BASE,
> +				  ddrctrl_ramsize(base, nb_bytes));
>  }
>  
>  static __maybe_unused struct of_device_id stm32mp1_ddr_dt_ids[] = {
> -	{ .compatible = "st,stm32mp1-ddr" },
> +	{ .compatible = "st,stm32mp1-ddr", .data = (void *)4 },
> +	{ .compatible = "st,stm32mp13-ddr", .data = (void *)2 },
>  	{ /* sentinel */ }
>  };
>  
> diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h
> index 2ef8ef30c3ae..c141b925a156 100644
> --- a/arch/arm/mach-stm32mp/include/mach/revision.h
> +++ b/arch/arm/mach-stm32mp/include/mach/revision.h
> @@ -32,6 +32,14 @@
>  #define CPU_STM32MP151Fxx	0x050000AE
>  #define CPU_STM32MP151Dxx	0x050000AF
>  
> +#define cpu_stm32_is(mask, val) ({ \
> +	u32 type; \
> +	__stm32mp_get_cpu_type(&type) == 0 ? (type & mask) == val : 0; \
> +})
> +
> +#define cpu_stm32_is_stm32mp15() cpu_stm32_is(0xFFFF0000, 0x05000000)
> +#define cpu_stm32_is_stm32mp13() cpu_stm32_is(0xFFFF0000, 0x05010000)
> +
>  /* silicon revisions */
>  #define CPU_REV_A	0x1000
>  #define CPU_REV_B	0x2000
> -- 
> 2.30.2
> 
> 
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