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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Christian Melki <christian.melki@t2data.com>,
	Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH RFT 2/2] ARM: i.MX6: configure AIPS3 for i.MX6ULL/i.MX6SX
Date: Thu,  3 Mar 2022 15:42:46 +0100	[thread overview]
Message-ID: <20220303144246.3603311-2-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20220303144246.3603311-1-a.fatoum@pengutronix.de>

UltraLiteLite and SoloX both have an AIPS3, which has e.g. RNGB on it.
COnfigure that likewise to AIPS1 and AIPS2.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
Untested on actual HW.
---
 arch/arm/mach-imx/imx6.c                   |  5 +++++
 arch/arm/mach-imx/include/mach/imx6-regs.h | 10 ++++++++++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 256288b25a88..7bd29446e927 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -56,6 +56,9 @@ static void imx6_init_lowlevel(void)
 {
 	bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
 	bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
+	bool is_imx6ull = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6ULL;
+	bool is_imx6sx = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6SX;
+
 	uint32_t val_480;
 	uint32_t val_528;
 	uint32_t periph_sel_1;
@@ -72,6 +75,8 @@ static void imx6_init_lowlevel(void)
 
 	imx6_configure_aips(IOMEM(MX6_AIPS1_ON_BASE_ADDR));
 	imx6_configure_aips(IOMEM(MX6_AIPS2_ON_BASE_ADDR));
+	if (is_imx6ull || is_imx6sx)
+		imx6_configure_aips(IOMEM(MX6_AIPS3_ON_BASE_ADDR));
 
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
 	 * to make sure PFD is working right, otherwise, PFDs may
diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h
index b2753b0fa7dd..35f03036cb5b 100644
--- a/arch/arm/mach-imx/include/mach/imx6-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx6-regs.h
@@ -11,9 +11,13 @@
 #define MX6_AIPS1_ARB_BASE_ADDR		0x02000000
 #define MX6_AIPS2_ARB_BASE_ADDR		0x02100000
 
+#define MX6_AIPS3_ARB_BASE_ADDR		0x02200000
+#define MX6_AIPS3_ARB_END_ADDR		0x022FFFFF
+
 /* Defines for Blocks connected via AIPS (SkyBlue) */
 #define MX6_ATZ1_BASE_ADDR              MX6_AIPS1_ARB_BASE_ADDR
 #define MX6_ATZ2_BASE_ADDR              MX6_AIPS2_ARB_BASE_ADDR
+#define MX6_ATZ3_BASE_ADDR              MX6_AIPS3_ARB_BASE_ADDR
 
 /* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */
 #define MX6_SPDIF_BASE_ADDR             (MX6_ATZ1_BASE_ADDR + 0x04000)
@@ -81,6 +85,12 @@
 #define MX6_CAAM_BASE_ADDR              (MX6_ATZ2_BASE_ADDR)
 #define MX6_ARM_BASE_ADDR		(MX6_ATZ2_BASE_ADDR + 0x40000)
 
+/* ATZ#3- On Platform */
+#define MX6_AIPS3_ON_BASE_ADDR          (MX6_ATZ3_BASE_ADDR + 0x7C000)
+
+/* ATZ#2- Off Platform */
+#define MX6_AIPS3_OFF_BASE_ADDR         (MX6_ATZ3_BASE_ADDR + 0x80000)
+
 #define MX6_USBOH3_PL301_BASE_ADDR      (MX6_AIPS2_OFF_BASE_ADDR + 0x0000)
 #define MX6_USBOH3_USB_BASE_ADDR        (MX6_AIPS2_OFF_BASE_ADDR + 0x4000)
 #define MX6_OTG_BASE_ADDR		MX6_USBOH3_USB_BASE_ADDR
-- 
2.30.2


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  reply	other threads:[~2022-03-03 14:44 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-03 14:42 [PATCH 1/2] ARM: i.MX: factor out AIPS configuration into helper function Ahmad Fatoum
2022-03-03 14:42 ` Ahmad Fatoum [this message]
2022-03-04 14:29 ` Sascha Hauer

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