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From: Juergen Borleis <jbe@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH v2 2/3] ARM: webasto-marvel: add device tree shared with the kernel
Date: Mon, 21 Mar 2022 15:08:55 +0100	[thread overview]
Message-ID: <20220321140856.59479-2-jbe@pengutronix.de> (raw)
In-Reply-To: <20220321140856.59479-1-jbe@pengutronix.de>

Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
---
 arch/arm/dts/Makefile                  |   1 +
 arch/arm/dts/imx6ul-webasto-marvel.dts | 586 +++++++++++++++++++++++++
 2 files changed, 587 insertions(+)
 create mode 100644 arch/arm/dts/imx6ul-webasto-marvel.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 925ac12..e0177d8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -160,6 +160,7 @@ lwl-$(CONFIG_MACH_VSCOM_BALTOS) += am335x-baltos-minimal.dtb.o
 lwl-$(CONFIG_MACH_WARP7) += imx7s-warp.dtb.o
 lwl-$(CONFIG_MACH_VF610_TWR) += vf610-twr.dtb.o
 lwl-$(CONFIG_MACH_WEBASTO_CCBV2) += imx6ul-webasto-ccbv2.dtb.o
+lwl-$(CONFIG_MACH_WEBASTO_CCBV2) += imx6ul-webasto-marvel.dtb.o
 lwl-$(CONFIG_MACH_ZII_RDU1) +=	\
 	imx51-zii-rdu1.dtb.o		\
 	imx51-zii-scu2-mezz.dtb.o	\
diff --git a/arch/arm/dts/imx6ul-webasto-marvel.dts b/arch/arm/dts/imx6ul-webasto-marvel.dts
new file mode 100644
index 0000000..b8ecb00
--- /dev/null
+++ b/arch/arm/dts/imx6ul-webasto-marvel.dts
@@ -0,0 +1,586 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019, Webasto SE
+ * Author: Johannes Eigner <johannes.eigner@webasto.com>
+ *
+ * Description of the Marvel B2, MK3 Comboard
+ */
+
+/dts-v1/;
+
+#include <arm/imx6ul.dtsi>
+
+/ {
+	model = "Webasto common communication board Marvel MK3";
+	compatible = "webasto,imx6ul-marvel-b2", "webasto,imx6ul-marvel", "fsl,imx6ul";
+
+	chosen {
+		stdout-path = &uart7;
+		environment {
+			compatible = "barebox,environment";
+			device-path = &environment_emmc;
+		};
+	};
+
+	aliases {
+		state = &state_emmc;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		dt-overlay@84000000 {
+			reg = <0x84000000 0x100000>;
+			no-map;
+		};
+	};
+
+	state_emmc: state {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "barebox,state";
+		magic = <0x290cf8c6>;
+		backend-type = "raw";
+		backend = <&backend_state_emmc>;
+		backend-stridesize = <0x200>;
+
+		bootstate {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			system0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@0 {
+					reg = <0x0 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+
+				priority@4 {
+					reg = <0x4 0x4>;
+					type = "uint32";
+					default = <20>;
+				};
+			};
+
+			system1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts@8 {
+					reg = <0x8 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+
+				priority@c {
+					reg = <0xc 0x4>;
+					type = "uint32";
+					default = <21>;
+				};
+			};
+
+			last_chosen@10 {
+				reg = <0x10 0x4>;
+				type = "uint32";
+			};
+		};
+	};
+
+	transceiver1_en: regulator-can1phy {
+		compatible = "regulator-fixed";
+		regulator-name = "can-transceiver1";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctl_can1phy>;
+		vin-supply = <&swbst_reg>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_4v: regulator-4v {
+		compatible = "regulator-fixed";
+		regulator-name = "V_+4V";
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <4000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_wl18xx_vmmc: regulator-wl18xx {
+		compatible = "regulator-fixed";
+		regulator-name = "wl1837";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wifi_reg>;
+		vin-supply = <&reg_4v>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	reg_dp83822_en: regulator-dp83822 {
+		compatible = "regulator-fixed";
+		regulator-name = "dp83822";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_phy_reg>;
+		vin-supply = <&vcc_eth>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&asrc {
+	status = "disabled";
+};
+
+&can1 {
+	xceiver-supply = <&transceiver1_en>; /* CAN side */
+	vdd-supply = <&vgen1_reg>; /* I/O side */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctl_can1>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-supply = <&reg_dp83822_en>;
+	phy-handle = <&dp83822i>;
+	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dp83822i: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			clocks = <&clks IMX6UL_CLK_ENET_REF>;
+			clock-names = "rmii-ref";
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	pmic: mc34pf3000@8 {
+		compatible = "fsl,pfuze3000";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctl_pmic_irq>;
+		interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>;
+		reg = <0x08>;
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-name = "V_+3V3_SW1A";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			vdd_soc_in: sw1b {
+				regulator-name = "V_+1V4_SW1B";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-ramp-delay = <6250>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			sw2_reg: sw2 {
+				regulator-name = "V_+3V3_SW2";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vcc_ddr3: sw3 {
+				regulator-name = "V_+1V35_SW3";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			swbst_reg: swbst {
+				regulator-name = "V_+5V0_SWBST";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-boot-on;
+				regulator-always-on; /* due to hardware requirements */
+			};
+			vdd_snvs: vsnvs {
+				regulator-name = "V_+3V0_SNVS";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vrefddr: vrefddr {
+				regulator-name = "V_+0V675_VREFDDR";
+				vin-supply = <&vcc_ddr3>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			/* 3V3 Supply: i.MX6 modules */
+			vgen1_reg: vldo1 {
+				regulator-name = "V_+3V3_LDO1";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vgen2_reg: vldo2 {
+				/* not connected */
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+			};
+			vdd_high_in: v33 {
+				regulator-name = "V_+3V3_V33";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vcc_eth: vldo3 {
+				regulator-name = "V_+1V8_LDO3";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			vgen6_reg: vldo4 {
+				regulator-name = "V_+1V8_LDO4";
+				vin-supply = <&reg_4v>;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_phy_reg: phyreggrp {
+		fsl,pins = <
+			/* high = phy enabled */
+			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x13030
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+			/* Note: 1.8 V */
+			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
+			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
+			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x13030
+		>;
+	};
+
+	pinctl_pmic_irq: pmicgrp {
+		fsl,pins = <
+			/* 1.8 V level */
+			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x10000
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			/* 1.8 V level for all */
+			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
+			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
+		>;
+	};
+
+	pinctrl_uart6: uart6grp {
+		fsl,pins = <
+			/* 1.8 V level for all */
+			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x1b0b0
+			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x1b0b0
+			MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS	0x1b0b0
+			MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS	0x1b0b0
+			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x10030
+		>;
+	};
+
+	pinctrl_uart7: uart7grp {
+		fsl,pins = <
+			/* 3.3 V level for all */
+			MX6UL_PAD_LCD_DATA16__UART7_DCE_TX	0x0b0b0
+			MX6UL_PAD_LCD_DATA17__UART7_DCE_RX	0x1b0b0
+		>;
+	};
+
+	pinctrl_wifi_reg: wifigrp {
+		fsl,pins = <
+			/* 1.8 V level for all */
+			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x10030
+			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x00010
+		>;
+	};
+
+	pinctrl_wifi_irq: wifiirqgrp {
+		fsl,pins = <
+			/* 1.8 V level */
+			MX6UL_PAD_CSI_DATA00__GPIO4_IO21	0x17000
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			/* 1.8 V level for all */
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x10059
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x10059
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x10059
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x10059
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x10059
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp_slow {
+		fsl,pins = <
+			/* 3.3 V level for all, *no* external PU */
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10079
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17029
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17029
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17029
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17029
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17029
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x17029
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x17029
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x17029
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x17029
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B	0x00008
+		>;
+	};
+
+	pinctrl_usdhc2_100MHZ: usdhc2grp_100m {
+		fsl,pins = <
+			/* 3.3 V level for all, *no* external PU */
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100e9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x1b0a9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x1b0a9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x1b0a9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x1b0a9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x1b0a9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x1b0a9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x1b0a9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x1b0a9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x1b0a9
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B	0x00008
+		>;
+	};
+
+	pinctrl_usdhc2_200MHZ: usdhc2grp_200m {
+		fsl,pins = <
+			/* 3.3 V level for all, *no* external PU */
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100e9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x1b0e9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x1b0e9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x1b0e9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x1b0e9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x1b0e9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x1b0e9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x1b0e9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x1b0e9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x1b0e9
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B	0x00008
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x00b0
+		>;
+	};
+
+	pinctl_can1phy: can1phygrp {
+		fsl,pins = <
+			/* 3.3 V level */
+			MX6UL_PAD_LCD_DATA14__GPIO3_IO19	0x00008
+		>;
+	};
+
+	pinctl_can1: can1grp {
+		fsl,pins = <
+			/* 3.3 V level for all */
+			MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX	0x00009
+			MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX	0x17000
+		>;
+	};
+
+	pinctrl_usbotg2: cmgrp {
+		fsl,pins = <
+			MX6UL_PAD_UART2_RTS_B__GPIO1_IO23       0x10800  /* shutdown signal from voltage monitor */
+			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20     0x00028  /* power on signal to modem */
+			MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21     0x00028  /* fast shutdown signal to modem */
+			MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x00028  /* emergency reset signal to modem */
+			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25     0x14000  /* status signal from modem */
+		>;
+	};
+};
+
+&gpio1 {
+	gpio-line-names = "", "", "", "", "", "", "", "",
+		     "", "", "", "", "", "", "", "",
+		     "", "", "", "", "PWRON_CM_UC_DO", "FST_SHDN_CM_UC_DO", "", "INT_VMON_OUT",
+		     "", "STATUS_CM_UC_DI", "RST_EMERG_UC_DO", "", "";
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec1 0x620>;
+};
+
+&reg_arm {
+	vin-supply = <&vdd_soc_in>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&vdd_soc_in>;
+	regulator-allow-bypass;
+};
+
+&uart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart6>;
+	uart-has-rtscts;
+	bluetooth {
+		compatible = "ti,wl1837-st";
+		enable-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&reg_4v>;
+	};
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart7>;
+	status = "okay";
+};
+
+&usbotg1 {
+	/* Micro-USB-plug */
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usbotg2 {
+	/* Modem (e.g. internal only) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg2>;
+	vbus-supply = <&swbst_reg>;
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc1 {
+	/* SDIO (WIFI/BT) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_wl18xx_vmmc>;
+	vqmmc-supply = <&vgen6_reg>;
+	non-removable;
+	no-sd;
+	no-mmc;
+	keep-power-in-suspend;
+	cap-power-off-card;
+	max-frequency = <25000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1837";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_wifi_irq>;
+		reg = <2>;
+		interrupts-extended = <&gpio4 21 IRQ_TYPE_LEVEL_HIGH>;
+		tcxo-clock-frequency = <26000000>;
+	};
+};
+
+&usdhc2 {
+	/* eMMC */
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100MHZ>;
+	pinctrl-2 = <&pinctrl_usdhc2_200MHZ>;
+	bus-width = <8>;
+	vmmc-supply = <&sw1a_reg>;
+	vqmmc-supply = <&vgen1_reg>;
+	no-1-8-v;
+	non-removable;
+	no-sd;
+	no-sdio;
+	keep-power-in-suspend;
+	cap-mmc-hw-reset;
+	status = "okay";
+	/* bootloader specific */
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0x100000>;
+		};
+
+		environment_emmc: partition@100000 {
+			label = "barebox-environment";
+			reg = <0x100000 0x100000>;
+		};
+
+		backend_state_emmc: partition@200000 {
+			label = "barebox-state";
+			reg = <0x200000 0x100000>;
+		};
+	};
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+/* include the FIT public key for verifying on demand */
+#ifdef CONFIG_BOOTM_FITIMAGE_PUBKEY
+#include CONFIG_BOOTM_FITIMAGE_PUBKEY
+#endif
-- 
2.30.2


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  reply	other threads:[~2022-03-21 14:10 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-21 14:08 [PATCH v2 1/3] ARM: webasto-ccbv2: consider the available memory size for optee Juergen Borleis
2022-03-21 14:08 ` Juergen Borleis [this message]
2022-03-21 14:08 ` [PATCH v2 3/3] ARM: webasto-marvel: share the run-time setup with the ccbv2 variant Juergen Borleis
2022-03-28  8:28 ` [PATCH v2 1/3] ARM: webasto-ccbv2: consider the available memory size for optee Sascha Hauer

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