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From: Alexander Shiyan <eagle.alexander923@gmail.com>
To: barebox@lists.infradead.org
Cc: Alexander Shiyan <eagle.alexander923@gmail.com>
Subject: [RFC 1/8] ARM: OMAP: Rearranging EMIF4 definitions
Date: Fri,  3 Jun 2022 14:25:33 +0300	[thread overview]
Message-ID: <20220603112540.51644-1-eagle.alexander923@gmail.com> (raw)

Currently we have three different definitions for EMIF management:
- Offsets
- Offsets relative to the base address
- Offsets in the structure

The patch represents the first attempt to unify this.

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 arch/arm/boards/afi-gf/lowlevel.c             | 39 +++++++++---------
 arch/arm/mach-omap/am33xx_generic.c           | 41 +++++++++----------
 .../mach-omap/include/mach/am33xx-silicon.h   | 10 +----
 3 files changed, 42 insertions(+), 48 deletions(-)

diff --git a/arch/arm/boards/afi-gf/lowlevel.c b/arch/arm/boards/afi-gf/lowlevel.c
index de40f6c5af..88ffcfae5b 100644
--- a/arch/arm/boards/afi-gf/lowlevel.c
+++ b/arch/arm/boards/afi-gf/lowlevel.c
@@ -130,34 +130,35 @@ static void board_config_vtp(void)
 
 static void board_config_emif_ddr(void)
 {
+	const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE);
 	u32 i;
 
 	/*Program EMIF0 CFG Registers*/
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
-	__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
-	__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
-	__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
-	__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
-
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
-
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+	__raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1);
+	__raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW);
+	__raw_writel(EMIF_READ_LATENCY, emif4 + EMIF4_DDR_PHY_CTRL_2);
+	__raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1);
+	__raw_writel(EMIF_TIM1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW);
+	__raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2);
+	__raw_writel(EMIF_TIM2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW);
+	__raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3);
+	__raw_writel(EMIF_TIM3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW);
+
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG);
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2);
+
+	__raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL);
+	__raw_writel(0x00004650, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
 
 	for (i = 0; i < 5000; i++) {
 
 	}
 
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
+	__raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL);
+	__raw_writel(EMIF_SDREF, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
 
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-	__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG);
+	__raw_writel(EMIF_SDCFG, emif4 + EMIF4_SDRAM_CONFIG2);
 }
 
 static void board_config_ddr(void)
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index 3c5cdf065c..896968f2f3 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -307,18 +307,20 @@ void am33xx_ddr_phydata_cmd_macro(const struct am33xx_cmd_control *cmd_ctrl)
 
 void am33xx_config_sdram(const struct am33xx_emif_regs *regs)
 {
-	writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
-	writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
-	writel(regs->emif_read_latency, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
-	writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
-	writel(regs->emif_tim1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
-	writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
-	writel(regs->emif_tim2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
-	writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
-	writel(regs->emif_tim3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
+	const void __iomem *emif4 = IOMEM(AM33XX_EMIF4_BASE);
+
+	writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1);
+	writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW);
+	writel(regs->emif_read_latency, emif4 + EMIF4_DDR_PHY_CTRL_2);
+	writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1);
+	writel(regs->emif_tim1, emif4 + EMIF4_SDRAM_TIM_1_SHADOW);
+	writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2);
+	writel(regs->emif_tim2, emif4 + EMIF4_SDRAM_TIM_2_SHADOW);
+	writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3);
+	writel(regs->emif_tim3, emif4 + EMIF4_SDRAM_TIM_3_SHADOW);
 
 	if (regs->ocp_config)
-		writel(regs->ocp_config, AM33XX_EMIF4_0_REG(OCP_CONFIG));
+		writel(regs->ocp_config, emif4 + EMIF4_OCP_CONFIG);
 
 	if (regs->zq_config) {
 		/*
@@ -326,20 +328,17 @@ void am33xx_config_sdram(const struct am33xx_emif_regs *regs)
 		 * about 570us for a delay, which will be long enough
 		 * to configure things.
 		 */
-		writel(0x2800, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-		writel(regs->zq_config, AM33XX_EMIF4_0_REG(ZQ_CONFIG));
+		writel(0x2800, emif4 + EMIF4_SDRAM_REF_CTRL);
+		writel(regs->zq_config, emif4 + EMIF4_ZQ_CONFIG);
 		writel(regs->sdram_config, CM_EMIF_SDRAM_CONFIG);
-		writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
-		writel(regs->sdram_ref_ctrl,
-				AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-		writel(regs->sdram_ref_ctrl,
-			AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-
+		writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG);
+		writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL);
+		writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
 	}
 
-	writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
-	writel(regs->sdram_ref_ctrl, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
-	writel(regs->sdram_config, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
+	writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL);
+	writel(regs->sdram_ref_ctrl, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW);
+	writel(regs->sdram_config, emif4 + EMIF4_SDRAM_CONFIG);
 }
 
 /**
diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
index 0467dac03b..d090b0f29c 100644
--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h
+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h
@@ -37,9 +37,6 @@
 #define AM33XX_GPIO2_BASE		(AM33XX_L4_PER_BASE + 0x1AC000 + 0x100)
 #define AM33XX_GPIO3_BASE		(AM33XX_L4_PER_BASE + 0x1AE000 + 0x100)
 
-/* EMFI Registers */
-#define AM33XX_EMFI0_BASE		0x4C000000
-
 #define AM33XX_DRAM_ADDR_SPACE_START	0x80000000
 #define AM33XX_DRAM_ADDR_SPACE_END	0xC0000000
 
@@ -83,8 +80,8 @@
 #define AM33XX_WDT_BASE			0x44E35000
 
 /* EMIF Base address */
-#define AM33XX_EMIF4_0_CFG_BASE		0x4C000000
-#define AM33XX_EMIF4_1_CFG_BASE		0x4D000000
+#define AM33XX_EMIF4_BASE		0x4c000000
+
 #define AM33XX_DMM_BASE			0x4E000000
 
 #define AM335X_CPSW_BASE		0x4A100000
@@ -97,9 +94,6 @@
 #define AM33XX_DMM_LISA_MAP__3		(AM33XX_DMM_BASE + 0x4C)
 #define AM33XX_DMM_PAT_BASE_ADDR	(AM33XX_DMM_BASE + 0x460)
 
-#define AM33XX_EMIF4_0_REG(REGNAME)	(AM33XX_EMIF4_0_CFG_BASE + EMIF4_##REGNAME)
-#define AM33XX_EMIF4_1_REG(REGNAME)	(AM33XX_EMIF4_1_CFG_BASE + EMIF4_##REGNAME)
-
 #define EMIF4_MOD_ID_REV		0x0
 #define EMIF4_SDRAM_STATUS		0x04
 #define EMIF4_SDRAM_CONFIG		0x08
-- 
2.32.0


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             reply	other threads:[~2022-06-03 11:27 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-03 11:25 Alexander Shiyan [this message]
2022-06-03 11:25 ` [RFC 2/8] ARM: OMAP: Move EMIF4 definitions to appropriate header Alexander Shiyan
2022-06-03 11:25 ` [RFC 3/8] ARM: OMAP: Adopt am35xx_emif4_init() to use fixed offset definitions Alexander Shiyan
2022-06-03 11:25 ` [RFC 4/8] ARM: OMAP: Move locally used definitions from emif4 header to am35xx_emif4 Alexander Shiyan
2022-06-03 11:25 ` [RFC 5/8] ARM: OMAP: emif: Abstract am35xx_emif4 from any CPU-specific includes Alexander Shiyan
2022-06-03 11:25 ` [RFC 6/8] ARM: OMAP: emif: Rename am35xx_emif4 unit Alexander Shiyan
2022-06-03 11:25 ` [RFC 7/8] ARM: OMAP: Use EMIF4 registers for get SDRAM size Alexander Shiyan
2022-06-03 11:25 ` [RFC 8/8] ARM: OMAP: Move am33xx_sdram_size() into EMIF module and make it generic Alexander Shiyan
2022-06-07  7:38 ` [RFC 1/8] ARM: OMAP: Rearranging EMIF4 definitions Sascha Hauer
2022-06-07  7:47   ` Alexander Shiyan

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