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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-3.0 required=4.0 tests=AWL,BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [RFC 3/8] ARM: OMAP: Adopt am35xx_emif4_init() to use fixed offset definitions X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Signed-off-by: Alexander Shiyan --- arch/arm/mach-omap/am35xx_emif4.c | 40 ++++++++++++------------- arch/arm/mach-omap/include/mach/emif4.h | 24 --------------- 2 files changed, 20 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c index 678a338fd6..8780dfb539 100644 --- a/arch/arm/mach-omap/am35xx_emif4.c +++ b/arch/arm/mach-omap/am35xx_emif4.c @@ -21,58 +21,58 @@ */ void am35xx_emif4_init(void) { + const void __iomem *emif4 = IOMEM(OMAP3_SDRC_BASE); unsigned int regval; - struct emif4 *emif4_base = IOMEM(OMAP3_SDRC_BASE); /* Set the DDR PHY parameters in PHY ctrl registers */ regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | EMIF4_DDR1_EXT_STRB_DIS); - writel(regval, &emif4_base->ddr_phyctrl1); - writel(regval, &emif4_base->ddr_phyctrl1_shdw); - writel(0, &emif4_base->ddr_phyctrl2); + writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1); + writel(regval, emif4 + EMIF4_DDR_PHY_CTRL_1_SHADOW); + writel(0, emif4 + EMIF4_DDR_PHY_CTRL_2); /* Reset the DDR PHY and wait till completed */ - regval = readl(&emif4_base->sdram_iodft_tlgc); + regval = readl(emif4 + EMIF4_IODFT_TLGC); regval |= (1 << 10); - writel(regval, &emif4_base->sdram_iodft_tlgc); + writel(regval, emif4 + EMIF4_IODFT_TLGC); /* Wait till that bit clears*/ - while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)); + while (readl(emif4 + EMIF4_IODFT_TLGC) & (1 << 10)); /* Re-verify the DDR PHY status*/ - while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0); + while ((readl(emif4 + EMIF4_STATUS) & (1 << 2)) == 0x0); regval |= (1 << 0); - writel(regval, &emif4_base->sdram_iodft_tlgc); + writel(regval, emif4 + EMIF4_IODFT_TLGC); /* Set SDR timing registers */ regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS | EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD | EMIF4_TIM1_T_RP); - writel(regval, &emif4_base->sdram_time1); - writel(regval, &emif4_base->sdram_time1_shdw); + writel(regval, emif4 + EMIF4_SDRAM_TIM_1); + writel(regval, emif4 + EMIF4_SDRAM_TIM_1_SHADOW); regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP | EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR | EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP); - writel(regval, &emif4_base->sdram_time2); - writel(regval, &emif4_base->sdram_time2_shdw); + writel(regval, emif4 + EMIF4_SDRAM_TIM_2); + writel(regval, emif4 + EMIF4_SDRAM_TIM_2_SHADOW); regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC); - writel(regval, &emif4_base->sdram_time3); - writel(regval, &emif4_base->sdram_time3_shdw); + writel(regval, emif4 + EMIF4_SDRAM_TIM_3); + writel(regval, emif4 + EMIF4_SDRAM_TIM_3_SHADOW); /* Set the PWR control register */ regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE | EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE); - writel(regval, &emif4_base->sdram_pwr_mgmt); - writel(regval, &emif4_base->sdram_pwr_mgmt_shdw); + writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL); + writel(regval, emif4 + EMIF4_POWER_MANAGEMENT_CTRL_SHADOW); /* Set the DDR refresh rate control register */ regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS); - writel(regval, &emif4_base->sdram_refresh_ctrl); - writel(regval, &emif4_base->sdram_refresh_ctrl_shdw); + writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL); + writel(regval, emif4 + EMIF4_SDRAM_REF_CTRL_SHADOW); /* set the SDRAM configuration register */ regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK | @@ -81,5 +81,5 @@ void am35xx_emif4_init(void) EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL | EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM | EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP); - writel(regval, &emif4_base->sdram_config); + writel(regval, emif4 + EMIF4_SDRAM_CONFIG); } diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h index 559443c9a6..06dabc5939 100644 --- a/arch/arm/mach-omap/include/mach/emif4.h +++ b/arch/arm/mach-omap/include/mach/emif4.h @@ -97,30 +97,6 @@ #define EMIF4_DDR1_PWRDN_EN (0x1 << 6) #define EMIF4_DDR1_READ_LAT (0x6 << 0) -struct emif4 { - unsigned int emif_mod_id_rev; - unsigned int sdram_sts; - unsigned int sdram_config; - unsigned int res1; - unsigned int sdram_refresh_ctrl; - unsigned int sdram_refresh_ctrl_shdw; - unsigned int sdram_time1; - unsigned int sdram_time1_shdw; - unsigned int sdram_time2; - unsigned int sdram_time2_shdw; - unsigned int sdram_time3; - unsigned int sdram_time3_shdw; - unsigned char res2[8]; - unsigned int sdram_pwr_mgmt; - unsigned int sdram_pwr_mgmt_shdw; - unsigned char res3[32]; - unsigned int sdram_iodft_tlgc; - unsigned char res4[128]; - unsigned int ddr_phyctrl1; - unsigned int ddr_phyctrl1_shdw; - unsigned int ddr_phyctrl2; -}; - void am35xx_emif4_init(void); #endif /* endif _EMIF_H_ */ -- 2.32.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox