From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: lst@pengutronix.de, ukl@pengutronix.de,
Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH 05/10] soc: imx: add i.MX8M feature controller driver
Date: Thu, 18 Aug 2022 07:19:50 +0200 [thread overview]
Message-ID: <20220818051955.2088238-6-a.fatoum@pengutronix.de> (raw)
In-Reply-To: <20220818051955.2088238-1-a.fatoum@pengutronix.de>
The tester4 fuse bank of the i.MX8M is a 32-bit collection of fuses,
apaprently fused during test, which contains information about the
available IPs: How many cores are available and whether a VPU and GPU
is available an usable. Add a imx8m_feat_ctrl_init() function
that initializes a bitmap of supported features using tester4's value
and registers a feature controller with a check callback that just
looks up the relevant bit.
This function can then be called from a standalone driver or from the
fuse bank (ocotp) driver itself.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/soc/imx/Kconfig | 6 +++
drivers/soc/imx/Makefile | 1 +
drivers/soc/imx/imx8m-featctrl.c | 64 ++++++++++++++++++++++++++++++++
include/soc/imx8m/featctrl.h | 25 +++++++++++++
4 files changed, 96 insertions(+)
create mode 100644 drivers/soc/imx/imx8m-featctrl.c
create mode 100644 include/soc/imx8m/featctrl.h
diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig
index 742d13c4f5d7..eabe4a06d22c 100644
--- a/drivers/soc/imx/Kconfig
+++ b/drivers/soc/imx/Kconfig
@@ -7,4 +7,10 @@ config IMX_GPCV2_PM_DOMAINS
select PM_GENERIC_DOMAINS
default y if ARCH_IMX7 || ARCH_IMX8MQ
+config IMX8M_FEATCTRL
+ bool "i.MX8M feature controller"
+ depends on ARCH_IMX8M
+ select FEATURE_CONTROLLER
+ default y
+
endmenu
diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 3a8a8d0b00db..bd1717b03883 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
+obj-$(CONFIG_IMX8M_FEATCTRL) += imx8m-featctrl.o
diff --git a/drivers/soc/imx/imx8m-featctrl.c b/drivers/soc/imx/imx8m-featctrl.c
new file mode 100644
index 000000000000..480c80e6c1d9
--- /dev/null
+++ b/drivers/soc/imx/imx8m-featctrl.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+#include <common.h>
+#include <linux/bitmap.h>
+#include <featctrl.h>
+#include <soc/imx8m/featctrl.h>
+
+#include <dt-bindings/features/imx8m.h>
+
+struct imx_feat {
+ struct feature_controller feat;
+ unsigned long features[BITS_TO_LONGS(IMX8M_FEAT_END)];
+};
+
+static struct imx_feat *to_imx_feat(struct feature_controller *feat)
+{
+ return container_of(feat, struct imx_feat, feat);
+}
+
+static int imx8m_feat_check(struct feature_controller *feat, int idx)
+{
+ struct imx_feat *priv = to_imx_feat(feat);
+
+ if (idx > IMX8M_FEAT_END)
+ return -EINVAL;
+
+ return test_bit(idx, priv->features) ? FEATCTRL_OKAY : FEATCTRL_GATED;
+}
+
+int imx8m_feat_ctrl_init(struct device_d *dev, u32 tester4,
+ const struct imx8m_featctrl_data *data)
+{
+ unsigned long *features;
+ struct imx_feat *priv;
+
+ if (!dev || !data)
+ return -ENODEV;
+
+ dev_dbg(dev, "tester4 = 0x%08x\n", tester4);
+
+ priv = xzalloc(sizeof(*priv));
+ features = priv->features;
+
+ bitmap_fill(features, IMX8M_FEAT_END);
+
+ if (tester4 & data->vpu_bitmask)
+ clear_bit(IMX8M_FEAT_VPU, features);
+ if (tester4 & data->gpu_bitmask)
+ clear_bit(IMX8M_FEAT_GPU, features);
+
+ switch (tester4 & 3) {
+ case 0b11:
+ clear_bit(IMX8M_FEAT_CPU_DUAL, features);
+ fallthrough;
+ case 0b10:
+ clear_bit(IMX8M_FEAT_CPU_QUAD, features);
+ }
+
+ priv->feat.dev = dev;
+ priv->feat.check = imx8m_feat_check;
+
+ return feature_controller_register(&priv->feat);
+}
diff --git a/include/soc/imx8m/featctrl.h b/include/soc/imx8m/featctrl.h
new file mode 100644
index 000000000000..af94995a916a
--- /dev/null
+++ b/include/soc/imx8m/featctrl.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix */
+
+#ifndef __IMX8M_FEATCTRL_H_
+#define __IMX8M_FEATCTRL_H_
+
+#include <linux/types.h>
+
+struct imx8m_featctrl_data {
+ u32 vpu_bitmask;
+ u32 gpu_bitmask;
+};
+
+#ifdef CONFIG_IMX8M_FEATCTRL
+int imx8m_feat_ctrl_init(struct device_d *dev, u32 tester4,
+ const struct imx8m_featctrl_data *data);
+#else
+static inline int imx8m_feat_ctrl_init(struct device_d *dev, u32 tester4,
+ const struct imx8m_featctrl_data *data)
+{
+ return -ENODEV;
+}
+#endif
+
+#endif
--
2.30.2
next prev parent reply other threads:[~2022-08-18 5:21 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 5:19 [PATCH 00/10] Add new feature controller framework Ahmad Fatoum
2022-08-18 5:19 ` [PATCH 01/10] driver: add " Ahmad Fatoum
2022-08-18 5:19 ` [PATCH 02/10] driver: consult feature controller prior to device probe Ahmad Fatoum
2022-08-18 8:19 ` Philipp Zabel
2022-08-18 8:34 ` Ahmad Fatoum
2022-08-18 5:19 ` [PATCH 03/10] driver: featctrl: fixup kernel device tree Ahmad Fatoum
2022-08-18 5:19 ` [PATCH 04/10] dt-bindings: add i.MX8M feature controller bindings Ahmad Fatoum
2022-08-18 5:19 ` Ahmad Fatoum [this message]
2022-08-18 5:19 ` [PATCH 06/10] nvmem: import Linux nvmem_cell_read_variable_le_u32 Ahmad Fatoum
2022-08-18 5:19 ` [PATCH 07/10] nvmem: ocotp: add i.MX8M[MN] feature controller support Ahmad Fatoum
2022-08-18 5:19 ` [PATCH 08/10] ARM: dts: i.MX8MN: describe feature controller Ahmad Fatoum
2022-08-18 5:19 ` [PATCH 09/10] RFC: soc: imx: imx8m-featctrl: add i.MX8M[MN] stand-alone driver Ahmad Fatoum
2022-08-18 5:19 ` [PATCH 10/10] RFC: ARM: dts: i.MX8MM: describe standlone feature controller Ahmad Fatoum
2022-08-30 7:32 ` [PATCH 00/10] Add new feature controller framework Sascha Hauer
2022-08-30 7:38 ` Ahmad Fatoum
2022-08-31 6:06 ` Sascha Hauer
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