* [PATCH 2/4] ARM: socfpga: add Arria10-specific errata init
2022-08-26 6:49 [PATCH 1/4] ARM: socfpga: achilles: fix entry_function usage Steffen Trumtrar
@ 2022-08-26 6:49 ` Steffen Trumtrar
2022-08-26 6:49 ` [PATCH 3/4] ARM: socfpga: Enclustra AA1: enable ARM errata Steffen Trumtrar
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2022-08-26 6:49 UTC (permalink / raw)
To: barebox
The Cortex A9 on the Arria10 has multiple known errata.
Enable at least the currently supported ones in barebox.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boards/enclustra-aa1/lowlevel.c | 1 +
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/cpu_init.c | 12 ++++++++++++
arch/arm/mach-socfpga/include/mach/init.h | 8 ++++++++
4 files changed, 22 insertions(+)
create mode 100644 arch/arm/mach-socfpga/cpu_init.c
create mode 100644 arch/arm/mach-socfpga/include/mach/init.h
diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c
index 9f2d66a6bc..d819d9feae 100644
--- a/arch/arm/boards/enclustra-aa1/lowlevel.c
+++ b/arch/arm/boards/enclustra-aa1/lowlevel.c
@@ -40,6 +40,7 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_xload, ARRIA10_STACKTOP, r0, r1, r2)
int bitstream = 0;
arm_cpu_lowlevel_init();
+ arria10_cpu_lowlevel_init();
relocate_to_current_adr();
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 935270bfad..008dbc3887 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -3,6 +3,7 @@
pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-init.o cyclone5-freeze-controller.o cyclone5-scan-manager.o cyclone5-system-manager.o
pbl-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-clock-manager.o
obj-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += cyclone5-generic.o nic301.o cyclone5-bootsource.o cyclone5-reset-manager.o
+lwl-y += cpu_init.o
pbl-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += arria10-xload.o \
arria10-xload-emmc.o
diff --git a/arch/arm/mach-socfpga/cpu_init.c b/arch/arm/mach-socfpga/cpu_init.c
new file mode 100644
index 0000000000..1e0df1f6a5
--- /dev/null
+++ b/arch/arm/mach-socfpga/cpu_init.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/errata.h>
+#include <mach/init.h>
+
+void arria10_cpu_lowlevel_init(void)
+{
+ enable_arm_errata_794072_war();
+ enable_arm_errata_845369_war();
+}
diff --git a/arch/arm/mach-socfpga/include/mach/init.h b/arch/arm/mach-socfpga/include/mach/init.h
new file mode 100644
index 0000000000..c0e073ee13
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/init.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __MACH_INIT_H
+#define __MACH_INIT_H
+
+void arria10_cpu_lowlevel_init(void);
+
+#endif
--
2.33.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 3/4] ARM: socfpga: Enclustra AA1: enable ARM errata
2022-08-26 6:49 [PATCH 1/4] ARM: socfpga: achilles: fix entry_function usage Steffen Trumtrar
2022-08-26 6:49 ` [PATCH 2/4] ARM: socfpga: add Arria10-specific errata init Steffen Trumtrar
@ 2022-08-26 6:49 ` Steffen Trumtrar
2022-08-26 6:49 ` [PATCH 4/4] ARM: Socfpga: Achilles: Enable " Steffen Trumtrar
2022-08-30 7:33 ` [PATCH 1/4] ARM: socfpga: achilles: fix entry_function usage Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2022-08-26 6:49 UTC (permalink / raw)
To: barebox
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boards/enclustra-aa1/lowlevel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boards/enclustra-aa1/lowlevel.c b/arch/arm/boards/enclustra-aa1/lowlevel.c
index d819d9feae..b1a0f4876f 100644
--- a/arch/arm/boards/enclustra-aa1/lowlevel.c
+++ b/arch/arm/boards/enclustra-aa1/lowlevel.c
@@ -16,6 +16,7 @@
#include <mach/arria10-clock-manager.h>
#include <mach/arria10-pinmux.h>
#include <mach/arria10-fpga.h>
+#include <mach/init.h>
#include "pll-config-arria10.c"
#include "pinmux-config-arria10.c"
#include <mach/generic.h>
@@ -102,6 +103,7 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_aa1_bringup, ARRIA10_STACKTOP, r0, r1, r2
void *fdt;
arm_cpu_lowlevel_init();
+ arria10_cpu_lowlevel_init();
relocate_to_current_adr();
setup_c();
--
2.33.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 4/4] ARM: Socfpga: Achilles: Enable ARM errata
2022-08-26 6:49 [PATCH 1/4] ARM: socfpga: achilles: fix entry_function usage Steffen Trumtrar
2022-08-26 6:49 ` [PATCH 2/4] ARM: socfpga: add Arria10-specific errata init Steffen Trumtrar
2022-08-26 6:49 ` [PATCH 3/4] ARM: socfpga: Enclustra AA1: enable ARM errata Steffen Trumtrar
@ 2022-08-26 6:49 ` Steffen Trumtrar
2022-08-30 7:33 ` [PATCH 1/4] ARM: socfpga: achilles: fix entry_function usage Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2022-08-26 6:49 UTC (permalink / raw)
To: barebox
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boards/reflex-achilles/lowlevel.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
index f5efb961a1..511b41fd01 100644
--- a/arch/arm/boards/reflex-achilles/lowlevel.c
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -16,6 +16,7 @@
#include <mach/arria10-clock-manager.h>
#include <mach/arria10-pinmux.h>
#include <mach/arria10-fpga.h>
+#include <mach/init.h>
#include "pll-config-arria10.c"
#include "pinmux-config-arria10.c"
#include <mach/generic.h>
@@ -41,6 +42,7 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0, r1,
int bitstream = 0;
arm_cpu_lowlevel_init();
+ arria10_cpu_lowlevel_init();
relocate_to_current_adr();
setup_c();
@@ -93,6 +95,7 @@ ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_bringup, ARRIA10_STACKTOP, r0, r
void *fdt;
arm_cpu_lowlevel_init();
+ arria10_cpu_lowlevel_init();
relocate_to_current_adr();
setup_c();
--
2.33.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/4] ARM: socfpga: achilles: fix entry_function usage
2022-08-26 6:49 [PATCH 1/4] ARM: socfpga: achilles: fix entry_function usage Steffen Trumtrar
` (2 preceding siblings ...)
2022-08-26 6:49 ` [PATCH 4/4] ARM: Socfpga: Achilles: Enable " Steffen Trumtrar
@ 2022-08-30 7:33 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2022-08-30 7:33 UTC (permalink / raw)
To: Steffen Trumtrar; +Cc: barebox
On Fri, Aug 26, 2022 at 08:49:53AM +0200, Steffen Trumtrar wrote:
> Since commit 3e62b38ff641f263df2f6c9e3ebda3c7c62f310b
> we use ENTRY_FUNCTION_WITHSTACK in the bringup barebox.
> The patch should have removed the arm_setup_stack line
> as it is already done in the ENTRY_FUNCTION_WITHSTACK macro.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
> arch/arm/boards/reflex-achilles/lowlevel.c | 2 --
> 1 file changed, 2 deletions(-)
Applied, thanks
Sascha
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^ permalink raw reply [flat|nested] 5+ messages in thread