From: Johannes Zink <j.zink@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Johannes Zink <j.zink@pengutronix.de>
Subject: [PATCH master] ARM: i.MX7: enable caches when booted over USB
Date: Fri, 30 Sep 2022 15:37:02 +0200 [thread overview]
Message-ID: <20220930133702.518949-1-j.zink@pengutronix.de> (raw)
From: Ahmad Fatoum <a.fatoum@pengutronix.de>
BootROM on the i.MX7 doesn't set the SMP bit when booted
over serial download. This leads to vastly worse performance
when doing memory-heavy operations in a USB-booted system,
as the caches are not utilized. Example running md5sum over
a 25M image in ramfs:
without patch: 10796ms
with patch: 457ms
This issue isn't unique to the i.MX7, but exists for the i.MX6UL as
well, which also has the Cortex-A7 as CPU. Like with
imx6ul_cpu_lowlevel_init(), adapt imx7_cpu_lowlevel_init() to avoid this
slow down.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
---
arch/arm/mach-imx/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c
index ea36215419..ede2076102 100644
--- a/arch/arm/mach-imx/cpu_init.c
+++ b/arch/arm/mach-imx/cpu_init.c
@@ -49,7 +49,7 @@ void imx6ul_cpu_lowlevel_init(void)
void imx7_cpu_lowlevel_init(void)
{
- arm_cpu_lowlevel_init();
+ cortex_a7_lowlevel_init();
imx_cpu_timer_init(IOMEM(MX7_SYSCNT_CTRL_BASE_ADDR));
}
--
2.30.2
next reply other threads:[~2022-09-30 13:38 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 13:37 Johannes Zink [this message]
2022-10-04 7:54 ` Marco Felsch
2022-10-10 6:32 ` Ahmad Fatoum
2022-10-10 5:52 ` Sascha Hauer
2022-10-10 6:35 ` Ahmad Fatoum
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