* [PATCH v2 2/7] RISC-V: add riscv_vendor_id() support
2022-10-05 11:12 [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
@ 2022-10-05 11:12 ` Marco Felsch
2022-10-05 11:12 ` [PATCH v2 3/7] RISC-V: import vendorid list from linux Marco Felsch
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Marco Felsch @ 2022-10-05 11:12 UTC (permalink / raw)
To: barebox
Add the support to query the vendorid which is stored within the
mvendorid register. This register is only accessible from M-Mode so we
need to use the sbi interface if we are running from S-Mode.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
v2:
- adapt switch-case to fix compile error.
arch/riscv/include/asm/system.h | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index adf856f9e9..89516f075b 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -5,6 +5,8 @@
#ifndef __ASSEMBLY__
+#include <asm/sbi.h>
+
#define RISCV_MODE_MASK 0x3
enum riscv_mode {
RISCV_U_MODE = 0,
@@ -42,6 +44,30 @@ static inline long __riscv_hartid(u32 flags)
return hartid;
}
+static inline long __riscv_vendor_id(u32 flags)
+{
+ struct sbiret ret;
+ long id;
+
+ switch (__riscv_mode(flags)) {
+ case RISCV_M_MODE:
+ __asm__ volatile("csrr %0, mvendorid\n" : "=r"(id));
+ return id;
+ case RISCV_S_MODE:
+ /*
+ * We need to use the sbi_ecall() since it can be that we got
+ * called without a working stack
+ */
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID,
+ 0, 0, 0, 0, 0, 0);
+ if (!ret.error)
+ return ret.value;
+ return -1;
+ default:
+ return -1;
+ }
+}
+
#ifndef __PBL__
extern unsigned barebox_riscv_pbl_flags;
@@ -54,6 +80,11 @@ static inline long riscv_hartid(void)
{
return __riscv_hartid(barebox_riscv_pbl_flags);
}
+
+static inline long riscv_vendor_id(void)
+{
+ return __riscv_vendor_id(barebox_riscv_pbl_flags);
+}
#endif
#endif
--
2.30.2
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v2 3/7] RISC-V: import vendorid list from linux
2022-10-05 11:12 [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-10-05 11:12 ` [PATCH v2 2/7] RISC-V: add riscv_vendor_id() support Marco Felsch
@ 2022-10-05 11:12 ` Marco Felsch
2022-10-05 11:12 ` [PATCH v2 4/7] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Marco Felsch @ 2022-10-05 11:12 UTC (permalink / raw)
To: barebox
Import the vendor id list from upstream linux.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
arch/riscv/include/asm/vendorid_list.h | 11 +++++++++++
1 file changed, 11 insertions(+)
create mode 100644 arch/riscv/include/asm/vendorid_list.h
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
new file mode 100644
index 0000000000..cb89af3f07
--- /dev/null
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2021 SiFive
+ */
+#ifndef ASM_VENDOR_LIST_H
+#define ASM_VENDOR_LIST_H
+
+#define SIFIVE_VENDOR_ID 0x489
+#define THEAD_VENDOR_ID 0x5b7
+
+#endif
--
2.30.2
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v2 4/7] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags
2022-10-05 11:12 [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
2022-10-05 11:12 ` [PATCH v2 2/7] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-10-05 11:12 ` [PATCH v2 3/7] RISC-V: import vendorid list from linux Marco Felsch
@ 2022-10-05 11:12 ` Marco Felsch
2022-10-05 11:12 ` [PATCH v2 5/7] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Marco Felsch @ 2022-10-05 11:12 UTC (permalink / raw)
To: barebox
Use the dedicated scratch register for setting the pbl flags. Each mode
has it's own scratch register so we are not conflicting with M-mode
running firmware e.g. OpenSBI. Using the scratch register has two main
advantages:
1st) It can be used in PBL and non-PBL use-case.
2nd) It is not affected by the relocation code.
This commit prepares barebox to add support for the special cache ops
used by several T-Head CPUs.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
v2:
- adapt switch-case to fix compile error
arch/riscv/boot/entry.c | 3 +-
arch/riscv/boot/entry.h | 6 ++--
arch/riscv/boot/start.c | 13 +++----
arch/riscv/boot/uncompress.c | 8 ++---
arch/riscv/include/asm/system.h | 63 ++++++++++++++++++++-------------
5 files changed, 51 insertions(+), 42 deletions(-)
diff --git a/arch/riscv/boot/entry.c b/arch/riscv/boot/entry.c
index e4a5c2208d..f5a536fc78 100644
--- a/arch/riscv/boot/entry.c
+++ b/arch/riscv/boot/entry.c
@@ -25,6 +25,7 @@ void __noreturn __naked barebox_riscv_entry(unsigned long membase,
{
unsigned long stack_top = riscv_mem_stack_top(membase, membase + memsize);
asm volatile ("move sp, %0" : : "r"(stack_top));
- barebox_pbl_start(membase, memsize, boarddata, flags);
+ riscv_set_flags(flags);
+ barebox_pbl_start(membase, memsize, boarddata);
}
diff --git a/arch/riscv/boot/entry.h b/arch/riscv/boot/entry.h
index fb4af5eae5..b3a24d2783 100644
--- a/arch/riscv/boot/entry.h
+++ b/arch/riscv/boot/entry.h
@@ -6,12 +6,10 @@
void __noreturn barebox_non_pbl_start(unsigned long membase,
unsigned long memsize,
- void *boarddata,
- unsigned flags);
+ void *boarddata);
void __noreturn barebox_pbl_start(unsigned long membase,
unsigned long memsize,
- void *boarddata,
- unsigned flags);
+ void *boarddata);
#endif
diff --git a/arch/riscv/boot/start.c b/arch/riscv/boot/start.c
index 8b4c8bb2f0..27d9066243 100644
--- a/arch/riscv/boot/start.c
+++ b/arch/riscv/boot/start.c
@@ -27,7 +27,6 @@ static unsigned long riscv_barebox_size;
static unsigned long riscv_endmem;
static void *barebox_boarddata;
static unsigned long barebox_boarddata_size;
-unsigned barebox_riscv_pbl_flags;
void *barebox_riscv_boot_dtb(void)
{
@@ -108,7 +107,7 @@ device_initcall(barebox_memory_areas_init);
*/
__noreturn __no_sanitize_address __section(.text_entry)
void barebox_non_pbl_start(unsigned long membase, unsigned long memsize,
- void *boarddata, unsigned flags)
+ void *boarddata)
{
unsigned long endmem = membase + memsize;
unsigned long malloc_start, malloc_end;
@@ -121,7 +120,7 @@ void barebox_non_pbl_start(unsigned long membase, unsigned long memsize,
barrier();
- irq_init_vector(__riscv_mode(flags));
+ irq_init_vector(riscv_mode());
pr_debug("memory at 0x%08lx, size 0x%08lx\n", membase, memsize);
@@ -171,20 +170,18 @@ void barebox_non_pbl_start(unsigned long membase, unsigned long memsize,
mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1);
- barebox_riscv_pbl_flags = flags;
-
pr_debug("starting barebox...\n");
start_barebox();
}
-void start(unsigned long membase, unsigned long memsize, void *boarddata, unsigned flags);
+void start(unsigned long membase, unsigned long memsize, void *boarddata);
/*
* First function in the uncompressed image. We get here from
* the pbl. The stack already has been set up by the pbl.
*/
void __no_sanitize_address __section(.text_entry) start(unsigned long membase,
- unsigned long memsize, void *boarddata, unsigned flags)
+ unsigned long memsize, void *boarddata)
{
- barebox_non_pbl_start(membase, memsize, boarddata, flags);
+ barebox_non_pbl_start(membase, memsize, boarddata);
}
diff --git a/arch/riscv/boot/uncompress.c b/arch/riscv/boot/uncompress.c
index 4ed9b4d371..ee24f81e01 100644
--- a/arch/riscv/boot/uncompress.c
+++ b/arch/riscv/boot/uncompress.c
@@ -24,16 +24,16 @@ unsigned long free_mem_ptr;
unsigned long free_mem_end_ptr;
void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
- void *fdt, unsigned flags)
+ void *fdt)
{
uint32_t pg_len, uncompressed_len;
- void __noreturn (*barebox)(unsigned long, unsigned long, void *, unsigned);
+ void __noreturn (*barebox)(unsigned long, unsigned long, void *);
unsigned long endmem = membase + memsize;
unsigned long barebox_base;
void *pg_start, *pg_end;
unsigned long pc = get_pc();
- irq_init_vector(__riscv_mode(flags));
+ irq_init_vector(riscv_mode());
/* piggy data is not relocated, so determine the bounds now */
pg_start = input_data + get_runtime_offset();
@@ -72,5 +72,5 @@ void __noreturn barebox_pbl_start(unsigned long membase, unsigned long memsize,
pr_debug("jumping to uncompressed image at 0x%p. dtb=0x%p\n", barebox, fdt);
- barebox(membase, memsize, fdt, flags);
+ barebox(membase, memsize, fdt);
}
diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index 89516f075b..f0b6bf2945 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -15,7 +15,39 @@ enum riscv_mode {
RISCV_M_MODE = 3,
};
-static inline enum riscv_mode __riscv_mode(u32 flags)
+static inline void riscv_set_flags(unsigned flags)
+{
+ switch (flags & RISCV_MODE_MASK) {
+ case RISCV_S_MODE:
+ __asm__ volatile("csrw sscratch, %0" : : "r"(flags));
+ break;
+ case RISCV_M_MODE:
+ __asm__ volatile("csrw mscratch, %0" : : "r"(flags));
+ break;
+ default:
+ /* Other modes are not implemented yet */
+ break;
+ }
+}
+
+static inline u32 riscv_get_flags(void)
+{
+ u32 flags = 0;
+
+ if (IS_ENABLED(CONFIG_RISCV_S_MODE))
+ __asm__ volatile("csrr %0, sscratch" : "=r"(flags));
+
+ /*
+ * Since we always set the scratch register on the very beginning, a
+ * empty flags indicates that we are running in M-mode.
+ */
+ if (!flags)
+ __asm__ volatile("csrr %0, mscratch" : "=r"(flags));
+
+ return flags;
+}
+
+static inline enum riscv_mode riscv_mode(void)
{
/* allow non-LTO builds to discard code for unused modes */
if (!IS_ENABLED(CONFIG_RISCV_MULTI_MODE)) {
@@ -25,14 +57,14 @@ static inline enum riscv_mode __riscv_mode(u32 flags)
return RISCV_S_MODE;
}
- return flags & RISCV_MODE_MASK;
+ return riscv_get_flags() & RISCV_MODE_MASK;
}
-static inline long __riscv_hartid(u32 flags)
+static inline long riscv_hartid(void)
{
long hartid = -1;
- switch (__riscv_mode(flags)) {
+ switch (riscv_mode()) {
case RISCV_S_MODE:
__asm__ volatile("mv %0, tp\n" : "=r"(hartid) :);
break;
@@ -44,12 +76,12 @@ static inline long __riscv_hartid(u32 flags)
return hartid;
}
-static inline long __riscv_vendor_id(u32 flags)
+static inline long riscv_vendor_id(void)
{
struct sbiret ret;
long id;
- switch (__riscv_mode(flags)) {
+ switch (riscv_mode()) {
case RISCV_M_MODE:
__asm__ volatile("csrr %0, mvendorid\n" : "=r"(id));
return id;
@@ -68,25 +100,6 @@ static inline long __riscv_vendor_id(u32 flags)
}
}
-#ifndef __PBL__
-extern unsigned barebox_riscv_pbl_flags;
-
-static inline enum riscv_mode riscv_mode(void)
-{
- return __riscv_mode(barebox_riscv_pbl_flags);
-}
-
-static inline long riscv_hartid(void)
-{
- return __riscv_hartid(barebox_riscv_pbl_flags);
-}
-
-static inline long riscv_vendor_id(void)
-{
- return __riscv_vendor_id(barebox_riscv_pbl_flags);
-}
-#endif
-
#endif
#endif
--
2.30.2
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v2 5/7] RISC-V: implement cache-management errata for T-Head SoCs
2022-10-05 11:12 [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
` (2 preceding siblings ...)
2022-10-05 11:12 ` [PATCH v2 4/7] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
@ 2022-10-05 11:12 ` Marco Felsch
2022-10-05 11:12 ` [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig Marco Felsch
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Marco Felsch @ 2022-10-05 11:12 UTC (permalink / raw)
To: barebox
Since riscv_vendor_id() can be used from pbl and non-pbl context as well
as from relocated and non-relocated code, we are able to query the
vendor id and add special vendor handlings. This is required since the
T-Head C906 and C910 implement a scheme for handling cache operations
different from the generic Zicbom extension.
While on it replace the 'asm' statement by '__asm__' so we are not
relying on GNU extension.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
Hi,
please note that I'm aware of the fact that not all RISC-V cores
implementing the vendorid register, which is quirky according the
"privileged architecture" documentation. For such cores I would propose
to extend the pbl-flags by adding a quirks field. Platforms not
supporting the vendorid register can set the quirk within th
lowlevel/pbl code e.g.:
barebox_riscv_supervisor_entry(DRAM_BASE, SZ_1G, hartid, fdt, RISCV_QUIRK_NO_VENDORID);
This can be parsed by riscv_vendor_id() so in such case the vendorid 0
which is:
3.1.2 Machine Vendor ID Register mvendorid
The mvendorid CSR is a 32-bit read-only register providing the JEDEC
manufacturer ID of the provider of the core. This register must be
readable in any implementation, but a value of 0 can be returned to
indicate the field is not implemented or that this is a non-commercial
implementation.
Regards,
Marco
arch/riscv/include/asm/cache.h | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 6d69ed49bd..c787f89001 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -6,10 +6,29 @@
#ifndef _ASM_RISCV_CACHE_H
#define _ASM_RISCV_CACHE_H
+#include <asm/vendorid_list.h>
+
+static inline void thead_local_flush_icache_all(void)
+{
+ /*
+ * According [1] "13.3 Example of cache settings"
+ * [1]: https://github.com/T-head-Semi/openc906/blob/main/ \
+ * doc/openc906%20datasheet.pd
+ */
+ __asm__ volatile (".long 0x0100000b" ::: "memory"); /* th.icache.iall */
+ __asm__ volatile (".long 0x01b0000b" ::: "memory"); /* th.sync.is */
+}
+
static inline void local_flush_icache_all(void)
{
#ifdef CONFIG_HAS_CACHE
- asm volatile ("fence.i" ::: "memory");
+ switch(riscv_vendor_id()) {
+ case THEAD_VENDOR_ID:
+ thead_local_flush_icache_all();
+ break;
+ default:
+ __asm__ volatile ("fence.i" ::: "memory");
+ }
#endif
}
--
2.30.2
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig
2022-10-05 11:12 [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
` (3 preceding siblings ...)
2022-10-05 11:12 ` [PATCH v2 5/7] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
@ 2022-10-05 11:12 ` Marco Felsch
2022-10-22 7:55 ` Antony Pavlov
2022-10-05 11:12 ` [PATCH v2 7/7] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-10-07 8:30 ` [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Sascha Hauer
6 siblings, 1 reply; 11+ messages in thread
From: Marco Felsch @ 2022-10-05 11:12 UTC (permalink / raw)
To: barebox
This commit squashes all 64bit risc-v defconfigs into one like armv8.
The 32bit defconfigs are not changed since those systems have tight
resource constraints and a generic defconfig may break some systems.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
v2:
- new commit
Documentation/boards/emulated.rst | 4 +-
Documentation/boards/riscv.rst | 6 +-
arch/riscv/Makefile | 2 +-
.../{virt64_defconfig => rv64i_defconfig} | 42 +++++-
arch/riscv/configs/sifive_defconfig | 129 -----------------
arch/riscv/configs/starfive_defconfig | 131 ------------------
6 files changed, 47 insertions(+), 267 deletions(-)
rename arch/riscv/configs/{virt64_defconfig => rv64i_defconfig} (76%)
delete mode 100644 arch/riscv/configs/sifive_defconfig
delete mode 100644 arch/riscv/configs/starfive_defconfig
diff --git a/Documentation/boards/emulated.rst b/Documentation/boards/emulated.rst
index 584883d6ef..ef035ec69a 100644
--- a/Documentation/boards/emulated.rst
+++ b/Documentation/boards/emulated.rst
@@ -64,12 +64,12 @@ The script can also be used with a precompiled barebox tree::
``emulate.pl`` also has some knowledge on paravirtualized devices::
# Run target and pass a block device (here /dev/virtioblk0)
- ARCH=riscv ./test/emulate.pl --blk=rootfs.ext4 virt64_defconfig
+ ARCH=riscv ./test/emulate.pl --blk=rootfs.ext4 rv64i_defconfig
Needed command line options can be passed directly to the
emulator/``pytest`` as well by placing them behind ``--``::
# appends -device ? to the command line. Add -n to see the final result
- ARCH=riscv ./test/emulate.pl virt64_defconfig -- -device ?
+ ARCH=riscv ./test/emulate.pl rv64i_defconfig -- -device ?
For a complete listing of options run ``./test/emulate.pl -h``.
diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst
index b7a3a95f0f..e69eca78c8 100644
--- a/Documentation/boards/riscv.rst
+++ b/Documentation/boards/riscv.rst
@@ -6,10 +6,10 @@ QEMU Virt
barebox supports both the qemu riscv32 and riscv64 ``-M virt`` boards::
- make ARCH=riscv virt64_defconfig
+ make ARCH=riscv rv64i_defconfig
qemu-system-riscv64 -M virt -serial stdio -kernel build/images/barebox-dt-2nd.img
-Replace ``64`` by ``32`` for 32-bit build. :ref:`virtio_sect` over MMIO is supported and
+For 32-bit builds use ``virt32_defconfig``. :ref:`virtio_sect` over MMIO is supported and
can be used for e.g. an extra console or to pass in a virtio-blk device::
qemu-system-riscv64 -M virt -serial stdio \
@@ -65,7 +65,7 @@ BeagleV
barebox has second-stage support for the BeagleV Starlight::
- make ARCH=riscv starfive_defconfig
+ make ARCH=riscv rv64i_defconfig
make
Thie resulting ``./images/barebox-beaglev-starlight.img`` can be used as payload
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6fbf1d4ddd..279db046c0 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-KBUILD_DEFCONFIG := virt64_defconfig
+KBUILD_DEFCONFIG := rv64i_defconfig
KBUILD_CPPFLAGS += -fno-strict-aliasing
diff --git a/arch/riscv/configs/virt64_defconfig b/arch/riscv/configs/rv64i_defconfig
similarity index 76%
rename from arch/riscv/configs/virt64_defconfig
rename to arch/riscv/configs/rv64i_defconfig
index c2edd2dc28..6c8409567d 100644
--- a/arch/riscv/configs/virt64_defconfig
+++ b/arch/riscv/configs/rv64i_defconfig
@@ -1,5 +1,11 @@
CONFIG_ARCH_RV64I=y
+CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_STARFIVE=y
CONFIG_SOC_VIRT=y
+CONFIG_BOARD_BEAGLEV=y
+CONFIG_BOARD_BEAGLEV_BETA=y
+CONFIG_BOARD_HIFIVE=y
+CONFIG_BOARD_RISCV_GENERIC_DT=y
CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_STACK_SIZE=0x20000
CONFIG_MALLOC_SIZE=0x0
@@ -13,6 +19,7 @@ CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_BOOTM_VERBOSE=y
CONFIG_BOOTM_INITRD=y
+CONFIG_SYSTEM_PARTITIONS=y
CONFIG_BLSPEC=y
CONFIG_CONSOLE_ACTIVATE_ALL=y
CONFIG_CONSOLE_ALLOW_COLOR=y
@@ -47,9 +54,11 @@ CONFIG_CMD_LN=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_SHA256SUM=y
+CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_DHCP=y
+CONFIG_CMD_MIITOOL=y
CONFIG_CMD_PING=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_EDIT=y
@@ -66,6 +75,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SPI=y
+CONFIG_CMD_WD=y
CONFIG_CMD_2048=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_OF_DIFF=y
@@ -86,12 +96,21 @@ CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_OF_BAREBOX_ENV_IN_FS=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_VIRTIO_CONSOLE=y
+CONFIG_SERIAL_SIFIVE=y
+CONFIG_DRIVER_NET_MACB=y
+CONFIG_DRIVER_NET_DESIGNWARE=y
+CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y
+CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE=y
CONFIG_DRIVER_NET_VIRTIO=y
+CONFIG_MICREL_PHY=y
+CONFIG_SPI_MEM=y
CONFIG_DRIVER_SPI_GPIO=y
+CONFIG_SPI_SIFIVE=y
CONFIG_I2C=y
CONFIG_I2C_GPIO=y
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_MTD_RAW_DEVICE=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_MTDRAM=y
@@ -104,21 +123,42 @@ CONFIG_VIDEO=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_DRIVER_VIDEO_BOCHS_PCI=y
CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y
+CONFIG_MCI=y
+CONFIG_MCI_SPI=y
+CONFIG_MCI_DW=y
CONFIG_CLOCKSOURCE_DUMMY_RATE=60000
CONFIG_STATE_DRV=y
CONFIG_EEPROM_AT24=y
CONFIG_VIRTIO_INPUT=y
+CONFIG_SRAM=y
+CONFIG_STARFIVE_PWRSEQ=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_WATCHDOG=y
+CONFIG_STARFIVE_WDT=y
CONFIG_HWRNG=y
CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_GPIO_SIFIVE=y
+CONFIG_HW_RANDOM_STARFIVE=y
CONFIG_GPIO_GENERIC_PLATFORM=y
-# CONFIG_PINCTRL is not set
+CONFIG_GPIO_STARFIVE=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_RMEM=y
+CONFIG_STARFIVE_OTP=y
CONFIG_PCI_ECAM_GENERIC=y
CONFIG_BLK_DEV_NVME=y
CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_NVMEM_REBOOT_MODE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_POWER_RESET_HTIF_POWEROFF=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MENU is not set
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
diff --git a/arch/riscv/configs/sifive_defconfig b/arch/riscv/configs/sifive_defconfig
deleted file mode 100644
index 6ebe6eaf37..0000000000
--- a/arch/riscv/configs/sifive_defconfig
+++ /dev/null
@@ -1,129 +0,0 @@
-CONFIG_ARCH_RV64I=y
-CONFIG_SOC_SIFIVE=y
-CONFIG_BOARD_HIFIVE=y
-CONFIG_BOARD_RISCV_GENERIC_DT=y
-CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_STACK_SIZE=0x20000
-CONFIG_MALLOC_SIZE=0x0
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_RELOCATABLE=y
-CONFIG_PANIC_HANG=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_CONSOLE_ALLOW_COLOR=y
-CONFIG_PBL_CONSOLE=y
-CONFIG_PARTITION_DISK_EFI=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_STATE=y
-CONFIG_STATE_CRYPTO=y
-CONFIG_BOOTCHOOSER=y
-CONFIG_RESET_SOURCE=y
-CONFIG_MACHINE_ID=y
-CONFIG_CMD_DMESG=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_IMD=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_POLLER=y
-CONFIG_CMD_SLICE=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADY=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_BOOTCHOOSER=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_CMP=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_LN=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SHA256SUM=y
-CONFIG_CMD_MSLEEP=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MIITOOL=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SPLASH=y
-CONFIG_CMD_FBTEST=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_MM=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DETECT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_2048=y
-CONFIG_CMD_BAREBOX_UPDATE=y
-CONFIG_CMD_OF_DIFF=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OF_DISPLAY_TIMINGS=y
-CONFIG_CMD_OF_FIXUP_STATUS=y
-CONFIG_CMD_OF_OVERLAY=y
-CONFIG_CMD_OFTREE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_DHRYSTONE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_NET_FASTBOOT=y
-CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_SERIAL_SIFIVE=y
-CONFIG_DRIVER_NET_MACB=y
-CONFIG_DRIVER_SPI_GPIO=y
-CONFIG_SPI_SIFIVE=y
-CONFIG_I2C=y
-CONFIG_I2C_GPIO=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_DEVICE=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_M25P80=y
-CONFIG_DRIVER_CFI=y
-CONFIG_DRIVER_CFI_BANK_WIDTH_8=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIDEO=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y
-CONFIG_MCI=y
-CONFIG_MCI_SPI=y
-CONFIG_CLOCKSOURCE_DUMMY_RATE=60000
-CONFIG_EEPROM_AT24=y
-CONFIG_HWRNG=y
-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_GPIO_SIFIVE=y
-# CONFIG_PINCTRL is not set
-CONFIG_SYSCON_REBOOT_MODE=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_NFS=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_FS_UIMAGEFS=y
-CONFIG_FS_PSTORE=y
-CONFIG_FS_SQUASHFS=y
-CONFIG_ZLIB=y
-CONFIG_BZLIB=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DECOMPRESS=y
-CONFIG_BASE64=y
-CONFIG_DIGEST_CRC32_GENERIC=y
-CONFIG_IMD_TARGET=y
-CONFIG_BAREBOXENV_TARGET=y
-CONFIG_BAREBOXCRC32_TARGET=y
diff --git a/arch/riscv/configs/starfive_defconfig b/arch/riscv/configs/starfive_defconfig
deleted file mode 100644
index c4df2256f5..0000000000
--- a/arch/riscv/configs/starfive_defconfig
+++ /dev/null
@@ -1,131 +0,0 @@
-CONFIG_ARCH_RV64I=y
-CONFIG_SOC_STARFIVE=y
-CONFIG_BOARD_BEAGLEV=y
-CONFIG_BOARD_BEAGLEV_BETA=y
-CONFIG_BOARD_RISCV_GENERIC_DT=y
-CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_STACK_SIZE=0x20000
-CONFIG_MALLOC_SIZE=0x0
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_RELOCATABLE=y
-CONFIG_PANIC_HANG=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_MENU=y
-CONFIG_BOOTM_INITRD=y
-CONFIG_SYSTEM_PARTITIONS=y
-CONFIG_IMD_TARGET=y
-CONFIG_CONSOLE_ALLOW_COLOR=y
-CONFIG_PBL_CONSOLE=y
-CONFIG_PARTITION_DISK_EFI=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
-CONFIG_BAREBOXENV_TARGET=y
-CONFIG_BAREBOXCRC32_TARGET=y
-CONFIG_STATE=y
-CONFIG_STATE_CRYPTO=y
-CONFIG_BOOTCHOOSER=y
-CONFIG_RESET_SOURCE=y
-CONFIG_MACHINE_ID=y
-CONFIG_CMD_DMESG=y
-CONFIG_LONGHELP=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_IMD=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_POLLER=y
-CONFIG_CMD_SLICE=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_LOADY=y
-CONFIG_CMD_RESET=y
-CONFIG_CMD_BOOTCHOOSER=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_CMP=y
-CONFIG_CMD_FILETYPE=y
-CONFIG_CMD_LN=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_SHA1SUM=y
-CONFIG_CMD_SHA256SUM=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_CMD_MSLEEP=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_MM=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_DETECT=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_POWEROFF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_WD=y
-CONFIG_CMD_2048=y
-CONFIG_CMD_BAREBOX_UPDATE=y
-CONFIG_CMD_OF_DIFF=y
-CONFIG_CMD_OF_NODE=y
-CONFIG_CMD_OF_PROPERTY=y
-CONFIG_CMD_OF_DISPLAY_TIMINGS=y
-CONFIG_CMD_OF_FIXUP_STATUS=y
-CONFIG_CMD_OF_OVERLAY=y
-CONFIG_CMD_OFTREE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_DHRYSTONE=y
-CONFIG_NET=y
-CONFIG_NET_NFS=y
-CONFIG_DRIVER_SERIAL_NS16550=y
-CONFIG_DRIVER_NET_DESIGNWARE=y
-CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y
-CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE=y
-CONFIG_MICREL_PHY=y
-CONFIG_SPI_MEM=y
-CONFIG_DRIVER_SPI_GPIO=y
-CONFIG_MCI=y
-CONFIG_MCI_DW=y
-CONFIG_CLOCKSOURCE_DUMMY_RATE=60000
-CONFIG_SRAM=y
-CONFIG_STARFIVE_PWRSEQ=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_LED_GPIO_OF=y
-CONFIG_LED_TRIGGERS=y
-CONFIG_WATCHDOG=y
-CONFIG_STARFIVE_WDT=y
-CONFIG_HWRNG=y
-CONFIG_HW_RANDOM_STARFIVE=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_STARFIVE=y
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_RMEM=y
-CONFIG_STARFIVE_OTP=y
-CONFIG_SYSCON_REBOOT_MODE=y
-CONFIG_NVMEM_REBOOT_MODE=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-# CONFIG_VIRTIO_MENU is not set
-CONFIG_FS_EXT4=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_NFS=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_FS_UIMAGEFS=y
-CONFIG_FS_PSTORE=y
-CONFIG_FS_SQUASHFS=y
-CONFIG_ZLIB=y
-CONFIG_BZLIB=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
-CONFIG_XZ_DECOMPRESS=y
-CONFIG_BASE64=y
-CONFIG_DIGEST_CRC32_GENERIC=y
--
2.30.2
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig
2022-10-05 11:12 ` [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig Marco Felsch
@ 2022-10-22 7:55 ` Antony Pavlov
2022-10-24 7:53 ` Marco Felsch
0 siblings, 1 reply; 11+ messages in thread
From: Antony Pavlov @ 2022-10-22 7:55 UTC (permalink / raw)
To: Marco Felsch; +Cc: barebox
On Wed, 5 Oct 2022 13:12:13 +0200
Marco Felsch <m.felsch@pengutronix.de> wrote:
Hi Marco!
It looks like this commit breaks emulate.pl, e.g.
ARCH=riscv
ARCH=${ARCH} ./test/emulate.pl --kconfig-full --test -- --junitxml=$PWD/$ARCH.tests.xml --lg-log=$PWD/log/$ARCH
reports
Can't find default configuration "arch/riscv/configs/virt64_defconfig"!
Please see details: https://gitlab.com/frantony/barebox/-/jobs/3211154690#L111
--
Best regards,
Antony Pavlov
> This commit squashes all 64bit risc-v defconfigs into one like armv8.
> The 32bit defconfigs are not changed since those systems have tight
> resource constraints and a generic defconfig may break some systems.
>
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
> v2:
> - new commit
>
> Documentation/boards/emulated.rst | 4 +-
> Documentation/boards/riscv.rst | 6 +-
> arch/riscv/Makefile | 2 +-
> .../{virt64_defconfig => rv64i_defconfig} | 42 +++++-
> arch/riscv/configs/sifive_defconfig | 129 -----------------
> arch/riscv/configs/starfive_defconfig | 131 ------------------
> 6 files changed, 47 insertions(+), 267 deletions(-)
> rename arch/riscv/configs/{virt64_defconfig => rv64i_defconfig} (76%)
> delete mode 100644 arch/riscv/configs/sifive_defconfig
> delete mode 100644 arch/riscv/configs/starfive_defconfig
>
> diff --git a/Documentation/boards/emulated.rst b/Documentation/boards/emulated.rst
> index 584883d6ef..ef035ec69a 100644
> --- a/Documentation/boards/emulated.rst
> +++ b/Documentation/boards/emulated.rst
> @@ -64,12 +64,12 @@ The script can also be used with a precompiled barebox tree::
> ``emulate.pl`` also has some knowledge on paravirtualized devices::
>
> # Run target and pass a block device (here /dev/virtioblk0)
> - ARCH=riscv ./test/emulate.pl --blk=rootfs.ext4 virt64_defconfig
> + ARCH=riscv ./test/emulate.pl --blk=rootfs.ext4 rv64i_defconfig
>
> Needed command line options can be passed directly to the
> emulator/``pytest`` as well by placing them behind ``--``::
>
> # appends -device ? to the command line. Add -n to see the final result
> - ARCH=riscv ./test/emulate.pl virt64_defconfig -- -device ?
> + ARCH=riscv ./test/emulate.pl rv64i_defconfig -- -device ?
>
> For a complete listing of options run ``./test/emulate.pl -h``.
> diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst
> index b7a3a95f0f..e69eca78c8 100644
> --- a/Documentation/boards/riscv.rst
> +++ b/Documentation/boards/riscv.rst
> @@ -6,10 +6,10 @@ QEMU Virt
>
> barebox supports both the qemu riscv32 and riscv64 ``-M virt`` boards::
>
> - make ARCH=riscv virt64_defconfig
> + make ARCH=riscv rv64i_defconfig
> qemu-system-riscv64 -M virt -serial stdio -kernel build/images/barebox-dt-2nd.img
>
> -Replace ``64`` by ``32`` for 32-bit build. :ref:`virtio_sect` over MMIO is supported and
> +For 32-bit builds use ``virt32_defconfig``. :ref:`virtio_sect` over MMIO is supported and
> can be used for e.g. an extra console or to pass in a virtio-blk device::
>
> qemu-system-riscv64 -M virt -serial stdio \
> @@ -65,7 +65,7 @@ BeagleV
>
> barebox has second-stage support for the BeagleV Starlight::
>
> - make ARCH=riscv starfive_defconfig
> + make ARCH=riscv rv64i_defconfig
> make
>
> Thie resulting ``./images/barebox-beaglev-starlight.img`` can be used as payload
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> index 6fbf1d4ddd..279db046c0 100644
> --- a/arch/riscv/Makefile
> +++ b/arch/riscv/Makefile
> @@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> -KBUILD_DEFCONFIG := virt64_defconfig
> +KBUILD_DEFCONFIG := rv64i_defconfig
>
> KBUILD_CPPFLAGS += -fno-strict-aliasing
>
> diff --git a/arch/riscv/configs/virt64_defconfig b/arch/riscv/configs/rv64i_defconfig
> similarity index 76%
> rename from arch/riscv/configs/virt64_defconfig
> rename to arch/riscv/configs/rv64i_defconfig
> index c2edd2dc28..6c8409567d 100644
> --- a/arch/riscv/configs/virt64_defconfig
> +++ b/arch/riscv/configs/rv64i_defconfig
> @@ -1,5 +1,11 @@
> CONFIG_ARCH_RV64I=y
> +CONFIG_SOC_SIFIVE=y
> +CONFIG_SOC_STARFIVE=y
> CONFIG_SOC_VIRT=y
> +CONFIG_BOARD_BEAGLEV=y
> +CONFIG_BOARD_BEAGLEV_BETA=y
> +CONFIG_BOARD_HIFIVE=y
> +CONFIG_BOARD_RISCV_GENERIC_DT=y
> CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y
> CONFIG_STACK_SIZE=0x20000
> CONFIG_MALLOC_SIZE=0x0
> @@ -13,6 +19,7 @@ CONFIG_AUTO_COMPLETE=y
> CONFIG_MENU=y
> CONFIG_BOOTM_VERBOSE=y
> CONFIG_BOOTM_INITRD=y
> +CONFIG_SYSTEM_PARTITIONS=y
> CONFIG_BLSPEC=y
> CONFIG_CONSOLE_ACTIVATE_ALL=y
> CONFIG_CONSOLE_ALLOW_COLOR=y
> @@ -47,9 +54,11 @@ CONFIG_CMD_LN=y
> CONFIG_CMD_MD5SUM=y
> CONFIG_CMD_SHA1SUM=y
> CONFIG_CMD_SHA256SUM=y
> +CONFIG_CMD_UNCOMPRESS=y
> CONFIG_CMD_MSLEEP=y
> CONFIG_CMD_SLEEP=y
> CONFIG_CMD_DHCP=y
> +CONFIG_CMD_MIITOOL=y
> CONFIG_CMD_PING=y
> CONFIG_CMD_ECHO_E=y
> CONFIG_CMD_EDIT=y
> @@ -66,6 +75,7 @@ CONFIG_CMD_GPIO=y
> CONFIG_CMD_I2C=y
> CONFIG_CMD_POWEROFF=y
> CONFIG_CMD_SPI=y
> +CONFIG_CMD_WD=y
> CONFIG_CMD_2048=y
> CONFIG_CMD_BAREBOX_UPDATE=y
> CONFIG_CMD_OF_DIFF=y
> @@ -86,12 +96,21 @@ CONFIG_OF_BAREBOX_DRIVERS=y
> CONFIG_OF_BAREBOX_ENV_IN_FS=y
> CONFIG_DRIVER_SERIAL_NS16550=y
> CONFIG_VIRTIO_CONSOLE=y
> +CONFIG_SERIAL_SIFIVE=y
> +CONFIG_DRIVER_NET_MACB=y
> +CONFIG_DRIVER_NET_DESIGNWARE=y
> +CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y
> +CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE=y
> CONFIG_DRIVER_NET_VIRTIO=y
> +CONFIG_MICREL_PHY=y
> +CONFIG_SPI_MEM=y
> CONFIG_DRIVER_SPI_GPIO=y
> +CONFIG_SPI_SIFIVE=y
> CONFIG_I2C=y
> CONFIG_I2C_GPIO=y
> CONFIG_MTD=y
> # CONFIG_MTD_OOB_DEVICE is not set
> +CONFIG_MTD_RAW_DEVICE=y
> CONFIG_MTD_CONCAT=y
> CONFIG_MTD_M25P80=y
> CONFIG_MTD_MTDRAM=y
> @@ -104,21 +123,42 @@ CONFIG_VIDEO=y
> CONFIG_FRAMEBUFFER_CONSOLE=y
> CONFIG_DRIVER_VIDEO_BOCHS_PCI=y
> CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y
> +CONFIG_MCI=y
> +CONFIG_MCI_SPI=y
> +CONFIG_MCI_DW=y
> CONFIG_CLOCKSOURCE_DUMMY_RATE=60000
> CONFIG_STATE_DRV=y
> CONFIG_EEPROM_AT24=y
> CONFIG_VIRTIO_INPUT=y
> +CONFIG_SRAM=y
> +CONFIG_STARFIVE_PWRSEQ=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_LED_GPIO_OF=y
> +CONFIG_LED_TRIGGERS=y
> +CONFIG_WATCHDOG=y
> +CONFIG_STARFIVE_WDT=y
> CONFIG_HWRNG=y
> CONFIG_HW_RANDOM_VIRTIO=y
> +CONFIG_GPIO_SIFIVE=y
> +CONFIG_HW_RANDOM_STARFIVE=y
> CONFIG_GPIO_GENERIC_PLATFORM=y
> -# CONFIG_PINCTRL is not set
> +CONFIG_GPIO_STARFIVE=y
> +CONFIG_PINCTRL_SINGLE=y
> +CONFIG_NVMEM=y
> +CONFIG_NVMEM_RMEM=y
> +CONFIG_STARFIVE_OTP=y
> CONFIG_PCI_ECAM_GENERIC=y
> CONFIG_BLK_DEV_NVME=y
> CONFIG_SYSCON_REBOOT_MODE=y
> +CONFIG_NVMEM_REBOOT_MODE=y
> CONFIG_POWER_RESET_SYSCON=y
> CONFIG_POWER_RESET_SYSCON_POWEROFF=y
> CONFIG_POWER_RESET_HTIF_POWEROFF=y
> +CONFIG_POWER_RESET_GPIO=y
> +CONFIG_POWER_RESET_GPIO_RESTART=y
> CONFIG_VIRTIO_MMIO=y
> +# CONFIG_VIRTIO_MENU is not set
> CONFIG_FS_EXT4=y
> CONFIG_FS_TFTP=y
> CONFIG_FS_NFS=y
> diff --git a/arch/riscv/configs/sifive_defconfig b/arch/riscv/configs/sifive_defconfig
> deleted file mode 100644
> index 6ebe6eaf37..0000000000
> --- a/arch/riscv/configs/sifive_defconfig
> +++ /dev/null
> @@ -1,129 +0,0 @@
> -CONFIG_ARCH_RV64I=y
> -CONFIG_SOC_SIFIVE=y
> -CONFIG_BOARD_HIFIVE=y
> -CONFIG_BOARD_RISCV_GENERIC_DT=y
> -CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y
> -CONFIG_STACK_SIZE=0x20000
> -CONFIG_MALLOC_SIZE=0x0
> -CONFIG_MALLOC_TLSF=y
> -CONFIG_KALLSYMS=y
> -CONFIG_RELOCATABLE=y
> -CONFIG_PANIC_HANG=y
> -CONFIG_HUSH_FANCY_PROMPT=y
> -CONFIG_CMDLINE_EDITING=y
> -CONFIG_AUTO_COMPLETE=y
> -CONFIG_MENU=y
> -CONFIG_CONSOLE_ALLOW_COLOR=y
> -CONFIG_PBL_CONSOLE=y
> -CONFIG_PARTITION_DISK_EFI=y
> -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
> -CONFIG_STATE=y
> -CONFIG_STATE_CRYPTO=y
> -CONFIG_BOOTCHOOSER=y
> -CONFIG_RESET_SOURCE=y
> -CONFIG_MACHINE_ID=y
> -CONFIG_CMD_DMESG=y
> -CONFIG_LONGHELP=y
> -CONFIG_CMD_IOMEM=y
> -CONFIG_CMD_IMD=y
> -CONFIG_CMD_MEMINFO=y
> -CONFIG_CMD_POLLER=y
> -CONFIG_CMD_SLICE=y
> -CONFIG_CMD_GO=y
> -CONFIG_CMD_LOADY=y
> -CONFIG_CMD_RESET=y
> -CONFIG_CMD_BOOTCHOOSER=y
> -CONFIG_CMD_EXPORT=y
> -CONFIG_CMD_PRINTENV=y
> -CONFIG_CMD_MAGICVAR=y
> -CONFIG_CMD_MAGICVAR_HELP=y
> -CONFIG_CMD_SAVEENV=y
> -CONFIG_CMD_CMP=y
> -CONFIG_CMD_FILETYPE=y
> -CONFIG_CMD_LN=y
> -CONFIG_CMD_MD5SUM=y
> -CONFIG_CMD_SHA1SUM=y
> -CONFIG_CMD_SHA256SUM=y
> -CONFIG_CMD_MSLEEP=y
> -CONFIG_CMD_SLEEP=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MIITOOL=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_EDIT=y
> -CONFIG_CMD_SPLASH=y
> -CONFIG_CMD_FBTEST=y
> -CONFIG_CMD_READLINE=y
> -CONFIG_CMD_TIMEOUT=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_CMD_MM=y
> -CONFIG_CMD_CLK=y
> -CONFIG_CMD_DETECT=y
> -CONFIG_CMD_FLASH=y
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_POWEROFF=y
> -CONFIG_CMD_SPI=y
> -CONFIG_CMD_2048=y
> -CONFIG_CMD_BAREBOX_UPDATE=y
> -CONFIG_CMD_OF_DIFF=y
> -CONFIG_CMD_OF_NODE=y
> -CONFIG_CMD_OF_PROPERTY=y
> -CONFIG_CMD_OF_DISPLAY_TIMINGS=y
> -CONFIG_CMD_OF_FIXUP_STATUS=y
> -CONFIG_CMD_OF_OVERLAY=y
> -CONFIG_CMD_OFTREE=y
> -CONFIG_CMD_TIME=y
> -CONFIG_CMD_DHRYSTONE=y
> -CONFIG_NET=y
> -CONFIG_NET_NFS=y
> -CONFIG_NET_FASTBOOT=y
> -CONFIG_DRIVER_SERIAL_NS16550=y
> -CONFIG_VIRTIO_CONSOLE=y
> -CONFIG_SERIAL_SIFIVE=y
> -CONFIG_DRIVER_NET_MACB=y
> -CONFIG_DRIVER_SPI_GPIO=y
> -CONFIG_SPI_SIFIVE=y
> -CONFIG_I2C=y
> -CONFIG_I2C_GPIO=y
> -CONFIG_MTD=y
> -CONFIG_MTD_RAW_DEVICE=y
> -CONFIG_MTD_CONCAT=y
> -CONFIG_MTD_M25P80=y
> -CONFIG_DRIVER_CFI=y
> -CONFIG_DRIVER_CFI_BANK_WIDTH_8=y
> -CONFIG_VIRTIO_BLK=y
> -CONFIG_VIDEO=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -CONFIG_DRIVER_VIDEO_SIMPLEFB_CLIENT=y
> -CONFIG_MCI=y
> -CONFIG_MCI_SPI=y
> -CONFIG_CLOCKSOURCE_DUMMY_RATE=60000
> -CONFIG_EEPROM_AT24=y
> -CONFIG_HWRNG=y
> -CONFIG_HW_RANDOM_VIRTIO=y
> -CONFIG_GPIO_SIFIVE=y
> -# CONFIG_PINCTRL is not set
> -CONFIG_SYSCON_REBOOT_MODE=y
> -CONFIG_POWER_RESET_SYSCON=y
> -CONFIG_POWER_RESET_SYSCON_POWEROFF=y
> -CONFIG_POWER_RESET_GPIO_RESTART=y
> -CONFIG_VIRTIO_MMIO=y
> -CONFIG_FS_EXT4=y
> -CONFIG_FS_TFTP=y
> -CONFIG_FS_NFS=y
> -CONFIG_FS_FAT=y
> -CONFIG_FS_FAT_WRITE=y
> -CONFIG_FS_FAT_LFN=y
> -CONFIG_FS_UIMAGEFS=y
> -CONFIG_FS_PSTORE=y
> -CONFIG_FS_SQUASHFS=y
> -CONFIG_ZLIB=y
> -CONFIG_BZLIB=y
> -CONFIG_LZ4_DECOMPRESS=y
> -CONFIG_ZSTD_DECOMPRESS=y
> -CONFIG_XZ_DECOMPRESS=y
> -CONFIG_BASE64=y
> -CONFIG_DIGEST_CRC32_GENERIC=y
> -CONFIG_IMD_TARGET=y
> -CONFIG_BAREBOXENV_TARGET=y
> -CONFIG_BAREBOXCRC32_TARGET=y
> diff --git a/arch/riscv/configs/starfive_defconfig b/arch/riscv/configs/starfive_defconfig
> deleted file mode 100644
> index c4df2256f5..0000000000
> --- a/arch/riscv/configs/starfive_defconfig
> +++ /dev/null
> @@ -1,131 +0,0 @@
> -CONFIG_ARCH_RV64I=y
> -CONFIG_SOC_STARFIVE=y
> -CONFIG_BOARD_BEAGLEV=y
> -CONFIG_BOARD_BEAGLEV_BETA=y
> -CONFIG_BOARD_RISCV_GENERIC_DT=y
> -CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS=y
> -CONFIG_STACK_SIZE=0x20000
> -CONFIG_MALLOC_SIZE=0x0
> -CONFIG_MALLOC_TLSF=y
> -CONFIG_KALLSYMS=y
> -CONFIG_RELOCATABLE=y
> -CONFIG_PANIC_HANG=y
> -CONFIG_HUSH_FANCY_PROMPT=y
> -CONFIG_CMDLINE_EDITING=y
> -CONFIG_AUTO_COMPLETE=y
> -CONFIG_MENU=y
> -CONFIG_BOOTM_INITRD=y
> -CONFIG_SYSTEM_PARTITIONS=y
> -CONFIG_IMD_TARGET=y
> -CONFIG_CONSOLE_ALLOW_COLOR=y
> -CONFIG_PBL_CONSOLE=y
> -CONFIG_PARTITION_DISK_EFI=y
> -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
> -CONFIG_BAREBOXENV_TARGET=y
> -CONFIG_BAREBOXCRC32_TARGET=y
> -CONFIG_STATE=y
> -CONFIG_STATE_CRYPTO=y
> -CONFIG_BOOTCHOOSER=y
> -CONFIG_RESET_SOURCE=y
> -CONFIG_MACHINE_ID=y
> -CONFIG_CMD_DMESG=y
> -CONFIG_LONGHELP=y
> -CONFIG_CMD_IOMEM=y
> -CONFIG_CMD_IMD=y
> -CONFIG_CMD_MEMINFO=y
> -CONFIG_CMD_POLLER=y
> -CONFIG_CMD_SLICE=y
> -CONFIG_CMD_GO=y
> -CONFIG_CMD_LOADY=y
> -CONFIG_CMD_RESET=y
> -CONFIG_CMD_BOOTCHOOSER=y
> -CONFIG_CMD_EXPORT=y
> -CONFIG_CMD_PRINTENV=y
> -CONFIG_CMD_MAGICVAR=y
> -CONFIG_CMD_MAGICVAR_HELP=y
> -CONFIG_CMD_SAVEENV=y
> -CONFIG_CMD_CMP=y
> -CONFIG_CMD_FILETYPE=y
> -CONFIG_CMD_LN=y
> -CONFIG_CMD_MD5SUM=y
> -CONFIG_CMD_SHA1SUM=y
> -CONFIG_CMD_SHA256SUM=y
> -CONFIG_CMD_UNCOMPRESS=y
> -CONFIG_CMD_MSLEEP=y
> -CONFIG_CMD_SLEEP=y
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_EDIT=y
> -CONFIG_CMD_READLINE=y
> -CONFIG_CMD_TIMEOUT=y
> -CONFIG_CMD_MEMTEST=y
> -CONFIG_CMD_MM=y
> -CONFIG_CMD_CLK=y
> -CONFIG_CMD_DETECT=y
> -CONFIG_CMD_FLASH=y
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_POWEROFF=y
> -CONFIG_CMD_SPI=y
> -CONFIG_CMD_WD=y
> -CONFIG_CMD_2048=y
> -CONFIG_CMD_BAREBOX_UPDATE=y
> -CONFIG_CMD_OF_DIFF=y
> -CONFIG_CMD_OF_NODE=y
> -CONFIG_CMD_OF_PROPERTY=y
> -CONFIG_CMD_OF_DISPLAY_TIMINGS=y
> -CONFIG_CMD_OF_FIXUP_STATUS=y
> -CONFIG_CMD_OF_OVERLAY=y
> -CONFIG_CMD_OFTREE=y
> -CONFIG_CMD_TIME=y
> -CONFIG_CMD_DHRYSTONE=y
> -CONFIG_NET=y
> -CONFIG_NET_NFS=y
> -CONFIG_DRIVER_SERIAL_NS16550=y
> -CONFIG_DRIVER_NET_DESIGNWARE=y
> -CONFIG_DRIVER_NET_DESIGNWARE_GENERIC=y
> -CONFIG_DRIVER_NET_DESIGNWARE_STARFIVE=y
> -CONFIG_MICREL_PHY=y
> -CONFIG_SPI_MEM=y
> -CONFIG_DRIVER_SPI_GPIO=y
> -CONFIG_MCI=y
> -CONFIG_MCI_DW=y
> -CONFIG_CLOCKSOURCE_DUMMY_RATE=60000
> -CONFIG_SRAM=y
> -CONFIG_STARFIVE_PWRSEQ=y
> -CONFIG_LED=y
> -CONFIG_LED_GPIO=y
> -CONFIG_LED_GPIO_OF=y
> -CONFIG_LED_TRIGGERS=y
> -CONFIG_WATCHDOG=y
> -CONFIG_STARFIVE_WDT=y
> -CONFIG_HWRNG=y
> -CONFIG_HW_RANDOM_STARFIVE=y
> -CONFIG_GPIO_GENERIC_PLATFORM=y
> -CONFIG_GPIO_STARFIVE=y
> -CONFIG_PINCTRL_SINGLE=y
> -CONFIG_NVMEM=y
> -CONFIG_NVMEM_RMEM=y
> -CONFIG_STARFIVE_OTP=y
> -CONFIG_SYSCON_REBOOT_MODE=y
> -CONFIG_NVMEM_REBOOT_MODE=y
> -CONFIG_POWER_RESET_SYSCON=y
> -CONFIG_POWER_RESET_SYSCON_POWEROFF=y
> -CONFIG_POWER_RESET_GPIO=y
> -CONFIG_POWER_RESET_GPIO_RESTART=y
> -# CONFIG_VIRTIO_MENU is not set
> -CONFIG_FS_EXT4=y
> -CONFIG_FS_TFTP=y
> -CONFIG_FS_NFS=y
> -CONFIG_FS_FAT=y
> -CONFIG_FS_FAT_WRITE=y
> -CONFIG_FS_FAT_LFN=y
> -CONFIG_FS_UIMAGEFS=y
> -CONFIG_FS_PSTORE=y
> -CONFIG_FS_SQUASHFS=y
> -CONFIG_ZLIB=y
> -CONFIG_BZLIB=y
> -CONFIG_LZ4_DECOMPRESS=y
> -CONFIG_ZSTD_DECOMPRESS=y
> -CONFIG_XZ_DECOMPRESS=y
> -CONFIG_BASE64=y
> -CONFIG_DIGEST_CRC32_GENERIC=y
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig
2022-10-22 7:55 ` Antony Pavlov
@ 2022-10-24 7:53 ` Marco Felsch
2022-10-24 8:20 ` Ahmad Fatoum
0 siblings, 1 reply; 11+ messages in thread
From: Marco Felsch @ 2022-10-24 7:53 UTC (permalink / raw)
To: Antony Pavlov; +Cc: barebox
Hi Antony,
On 22-10-22, Antony Pavlov wrote:
> On Wed, 5 Oct 2022 13:12:13 +0200
> Marco Felsch <m.felsch@pengutronix.de> wrote:
>
> Hi Marco!
>
> It looks like this commit breaks emulate.pl, e.g.
>
> ARCH=riscv
> ARCH=${ARCH} ./test/emulate.pl --kconfig-full --test -- --junitxml=$PWD/$ARCH.tests.xml --lg-log=$PWD/log/$ARCH
>
> reports
>
> Can't find default configuration "arch/riscv/configs/virt64_defconfig"!
>
> Please see details: https://gitlab.com/frantony/barebox/-/jobs/3211154690#L111
Please see: https://gitlab.com/frantony/barebox/-/jobs/3211154690#L106
You are passing "--kconfig=virt64_defconfig" to tuxmake. I think this is
the failure.
Regards,
Marco
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig
2022-10-24 7:53 ` Marco Felsch
@ 2022-10-24 8:20 ` Ahmad Fatoum
0 siblings, 0 replies; 11+ messages in thread
From: Ahmad Fatoum @ 2022-10-24 8:20 UTC (permalink / raw)
To: Marco Felsch, Antony Pavlov; +Cc: barebox
On 24.10.22 09:53, Marco Felsch wrote:
> Hi Antony,
>
> On 22-10-22, Antony Pavlov wrote:
>> On Wed, 5 Oct 2022 13:12:13 +0200
>> Marco Felsch <m.felsch@pengutronix.de> wrote:
>>
>> Hi Marco!
>>
>> It looks like this commit breaks emulate.pl, e.g.
>>
>> ARCH=riscv
>> ARCH=${ARCH} ./test/emulate.pl --kconfig-full --test -- --junitxml=$PWD/$ARCH.tests.xml --lg-log=$PWD/log/$ARCH
>>
>> reports
>>
>> Can't find default configuration "arch/riscv/configs/virt64_defconfig"!
>>
>> Please see details: https://gitlab.com/frantony/barebox/-/jobs/3211154690#L111
>
> Please see: https://gitlab.com/frantony/barebox/-/jobs/3211154690#L106
>
> You are passing "--kconfig=virt64_defconfig" to tuxmake. I think this is
> the failure.
The configuration YAMLs are in test/riscv . They will need to be adapted.
E.g. qemu@virt64_defconfig.yaml -> qemu@rv64i_defconfig
Provided, rv64i is a strict superset of virt64, the test should then succeed.
>
> Regards,
> Marco
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 7/7] RISC-V: add Allwinner Sun20i D1 Nezha support
2022-10-05 11:12 [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
` (4 preceding siblings ...)
2022-10-05 11:12 ` [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig Marco Felsch
@ 2022-10-05 11:12 ` Marco Felsch
2022-10-07 8:30 ` [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Sascha Hauer
6 siblings, 0 replies; 11+ messages in thread
From: Marco Felsch @ 2022-10-05 11:12 UTC (permalink / raw)
To: barebox
Add Allwinner sun20i SoC and D1-Nezha board support.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
v2:
- drop own defconfig instead use the new rv64i_defconfig
Documentation/boards/riscv.rst | 102 ++++++++++++++++++++++
arch/riscv/Kconfig.socs | 16 ++++
arch/riscv/boards/Makefile | 1 +
arch/riscv/boards/allwinner-d1/Makefile | 3 +
arch/riscv/boards/allwinner-d1/lowlevel.c | 12 +++
arch/riscv/configs/rv64i_defconfig | 3 +
arch/riscv/include/asm/debug_ll.h | 5 ++
common/Kconfig | 5 ++
images/Makefile.riscv | 4 +
9 files changed, 151 insertions(+)
create mode 100644 arch/riscv/boards/allwinner-d1/Makefile
create mode 100644 arch/riscv/boards/allwinner-d1/lowlevel.c
diff --git a/Documentation/boards/riscv.rst b/Documentation/boards/riscv.rst
index e69eca78c8..92f663cfb9 100644
--- a/Documentation/boards/riscv.rst
+++ b/Documentation/boards/riscv.rst
@@ -188,3 +188,105 @@ Next, start barebox from DRAM::
running /env/bin/init...
/env/bin/init not found
barebox:/
+
+Allwinner D1 Nezha
+------------------
+
+Barebox has limited second-stage support for the Allwinner D1 Nezha (sun20i)::
+
+ ARCH=riscv make rv64i_defconfig
+ ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- make
+
+The resulting ``./images/barebox-allwinner-d1.img`` can be used as 2nd stage
+image which gets called by opensbi::
+
+ git clone https://github.com/tekkamanninja/opensbi -b allwinner_d1
+ cd opensbi
+ CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic FW_PIC=y make
+
+The resulting ``./build/platform/generic/firmware/fw_dynamic.bin`` is loaded
+by the 1st stage (spl) loader, which is basically a u-boot spl::
+
+ git clone https://github.com/smaeul/sun20i_d1_spl -b mainline
+ cd sun20i_d1_spl
+ CROSS_COMPILE=riscv64-linux-gnu- make p=sun20iw1p1 mmc
+
+The resulting ``./nboot/boot0_sdcard_sun20iw1p1.bin`` image used as 1st stage
+bootloader which loads all necessary binaries: dtb, opensbi and barebox to the
+dedicated places in DRAM. After loading it jumps to the opensbi image. The
+initial dtb can be taken from u-boot::
+
+ git clone https://github.com/smaeul/u-boot.git -b d1-wip
+ cd u-boot
+ ARCH=riscv make nezha_defconfig
+ ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- make
+
+Make will print two warnings at the end of this command but those can be ignored
+since we only want the devicetree blob which can be found under ``./u-boot.dtb``.
+
+The final image is build by mkimage. It is some sort of a self-defined toc1
+format. So we need to compile the mkimage with the toc1 format support as
+first::
+
+ cd u-boot
+ make tools-only
+
+The resulting ``tools/mkimage`` is used to build the toc1 image which is loaded
+by the 1st stage bootloader from the mmc interface. To build the final toc1 image
+we need to specify a toc1.cfg like::
+
+ [opensbi]
+ file = <ABSOLUT_PATH_TO>/opensbi/build/platform/generic/firmware/fw_dynamic.bin
+ addr = 0x40000000
+ [dtb]
+ file = <ABSOLUT_PATH_TO>/u-boot/u-boot.dtb
+ addr = 0x44000000
+ [u-boot]
+ file = <ABSOLUT_PATH_TO>/barebox/images/barebox-allwinner-d1.img
+ addr = 0x4a000000
+
+Then we need to call::
+
+ mkimage -T sunxi_toc1 -d toc1.cfg boot.toc1
+
+The last part is to place the 1st stage bootloader and the ``boot.toc1`` image
+onto the correct places. So the ROM loader can find the 1st stage bootloader
+and the 1st bootloader can find the ``boot.toc1`` image. This is done by::
+
+ dd if=boot0_sdcard_sun20iw1p1.bin of=/dev/sd<X> bs=512 seek=16
+ dd if=boot.toc1 of=/dev/sd<X> bs=512 seek=32800
+
+Now plug in the sdcard and power device and you will see::
+
+ [309]HELLO! BOOT0 is starting!
+ [312]BOOT0 commit : 882671f-dirty
+ [315]set pll start
+ [317]periph0 has been enabled
+ [320]set pll end
+ [322]board init ok
+
+ ...
+
+ OpenSBI v0.9-204-gc9024b5
+ ____ _____ ____ _____
+ / __ \ / ____| _ \_ _|
+ | | | |_ __ ___ _ __ | (___ | |_) || |
+ | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
+ | |__| | |_) | __/ | | |____) | |_) || |_
+ \____/| .__/ \___|_| |_|_____/|____/_____|
+ | |
+ |_|
+
+ Platform Name : Allwinner D1 Nezha
+ Platform Features : medeleg
+
+ ...
+
+ barebox 2022.08.0-00262-g38678340903b #1 Tue Sep 13 12:54:29 CEST 2022
+
+
+ Board: Allwinner D1 Nezha
+
+ ...
+
+ barebox@Allwinner D1 Nezha:/
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 828b65a0c1..0f03637a66 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -110,6 +110,22 @@ config BOARD_BEAGLEV_BETA
endif
+config SOC_ALLWINNER_SUN20I
+ bool "Allwinner Sun20i SoCs"
+ depends on ARCH_RV64I
+ select HAS_ASM_DEBUG_LL
+ select HAS_CACHE
+
+if SOC_ALLWINNER_SUN20I
+
+config BOARD_ALLWINNER_D1
+ bool "Allwinner D1 Nezha"
+ select RISCV_S_MODE
+ select RISCV_M_MODE
+ def_bool y
+
+endif
+
comment "CPU features"
config SIFIVE_L2
diff --git a/arch/riscv/boards/Makefile b/arch/riscv/boards/Makefile
index 3b763ff308..df16d38496 100644
--- a/arch/riscv/boards/Makefile
+++ b/arch/riscv/boards/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_BOARD_ALLWINNER_D1) += allwinner-d1/
obj-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo/
obj-$(CONFIG_BOARD_HIFIVE) += hifive/
obj-$(CONFIG_BOARD_BEAGLEV) += beaglev/
diff --git a/arch/riscv/boards/allwinner-d1/Makefile b/arch/riscv/boards/allwinner-d1/Makefile
new file mode 100644
index 0000000000..3d217ffe0b
--- /dev/null
+++ b/arch/riscv/boards/allwinner-d1/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+pbl-y += lowlevel.o
diff --git a/arch/riscv/boards/allwinner-d1/lowlevel.c b/arch/riscv/boards/allwinner-d1/lowlevel.c
new file mode 100644
index 0000000000..2b07a81edb
--- /dev/null
+++ b/arch/riscv/boards/allwinner-d1/lowlevel.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <common.h>
+#include <debug_ll.h>
+#include <asm/barebox-riscv.h>
+
+#define DRAM_BASE 0x40000000
+
+ENTRY_FUNCTION(start_allwinner_d1, a0, a1, a2)
+{
+ barebox_riscv_supervisor_entry(DRAM_BASE, SZ_1G, a0, (void *)a1);
+}
diff --git a/arch/riscv/configs/rv64i_defconfig b/arch/riscv/configs/rv64i_defconfig
index 6c8409567d..2c5bfd2df1 100644
--- a/arch/riscv/configs/rv64i_defconfig
+++ b/arch/riscv/configs/rv64i_defconfig
@@ -1,7 +1,9 @@
CONFIG_ARCH_RV64I=y
+CONFIG_SOC_ALLWINNER_SUN20I=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
CONFIG_SOC_VIRT=y
+CONFIG_BOARD_ALLWINNER_D1=y
CONFIG_BOARD_BEAGLEV=y
CONFIG_BOARD_BEAGLEV_BETA=y
CONFIG_BOARD_HIFIVE=y
@@ -95,6 +97,7 @@ CONFIG_NET_FASTBOOT=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_OF_BAREBOX_ENV_IN_FS=y
CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_SERIAL_SBI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_SERIAL_SIFIVE=y
CONFIG_DRIVER_NET_MACB=y
diff --git a/arch/riscv/include/asm/debug_ll.h b/arch/riscv/include/asm/debug_ll.h
index de9bc5f5fd..34294b09dd 100644
--- a/arch/riscv/include/asm/debug_ll.h
+++ b/arch/riscv/include/asm/debug_ll.h
@@ -29,6 +29,11 @@
#define DEBUG_LL_UART_CLK (58982400 / 16)
#define DEBUG_LL_UART_SHIFT 0
#define DEBUG_LL_UART_IOSIZE8
+#elif defined CONFIG_DEBUG_SUN20I
+#define DEBUG_LL_UART_ADDR 0x2500000
+#define DEBUG_LL_UART_CLK (24000000 / 16)
+#define DEBUG_LL_UART_SHIFT 2
+#define DEBUG_LL_UART_IOSIZE32
#endif
#define DEBUG_LL_UART_BPS CONFIG_BAUDRATE
diff --git a/common/Kconfig b/common/Kconfig
index 350e6aeea7..fb2bf49683 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1469,6 +1469,11 @@ config DEBUG_LITEX
bool "LiteX serial port"
depends on SOC_LITEX
+config DEBUG_SUN20I
+ bool "Allwinner Sun20i ns16550 serial0 port"
+ depends on SOC_ALLWINNER_SUN20I
+ select DEBUG_LL_NS16550
+
endchoice
config DEBUG_LL_NS16550
diff --git a/images/Makefile.riscv b/images/Makefile.riscv
index 0645238c43..df0e5a9146 100644
--- a/images/Makefile.riscv
+++ b/images/Makefile.riscv
@@ -23,3 +23,7 @@ image-$(CONFIG_BOARD_BEAGLEV) += barebox-beaglev-starlight.img
pblb-$(CONFIG_BOARD_LITEX_LINUX) += start_litex_linux
FILE_barebox-litex-linux.img = start_litex_linux.pblb
image-$(CONFIG_BOARD_LITEX_LINUX) += barebox-litex-linux.img
+
+pblb-$(CONFIG_BOARD_ALLWINNER_D1) += start_allwinner_d1
+FILE_barebox-allwinner-d1.img = start_allwinner_d1.pblb
+image-$(CONFIG_BOARD_ALLWINNER_D1) += barebox-allwinner-d1.img
--
2.30.2
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling
2022-10-05 11:12 [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling Marco Felsch
` (5 preceding siblings ...)
2022-10-05 11:12 ` [PATCH v2 7/7] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
@ 2022-10-07 8:30 ` Sascha Hauer
6 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2022-10-07 8:30 UTC (permalink / raw)
To: Marco Felsch; +Cc: barebox
On Wed, Oct 05, 2022 at 01:12:08PM +0200, Marco Felsch wrote:
> Commit fe181ffda9 ("RISC-V: support incoherent I-Cache") added the
> support to handle non-coherent caches and introduced the HAS_CACHE
> Kconfig symbol. The symbol must be used with CONFIG_ prefixed since this
> is the final Kconfig symbol which can be used within the code.
>
> Fixes: fe181ffda9 ("RISC-V: support incoherent I-Cache")
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
> arch/riscv/include/asm/cache.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks
Sascha
>
> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> index 9a0b9326b2..6d69ed49bd 100644
> --- a/arch/riscv/include/asm/cache.h
> +++ b/arch/riscv/include/asm/cache.h
> @@ -8,7 +8,7 @@
>
> static inline void local_flush_icache_all(void)
> {
> -#ifdef HAS_CACHE
> +#ifdef CONFIG_HAS_CACHE
> asm volatile ("fence.i" ::: "memory");
> #endif
> }
> --
> 2.30.2
>
>
>
--
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