From: Sascha Hauer <sha@pengutronix.de>
To: Marco Felsch <m.felsch@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH v2 1/7] RISC-V: cache: fix local_flush_icache_all enabling
Date: Fri, 7 Oct 2022 10:30:07 +0200 [thread overview]
Message-ID: <20221007083007.GY986@pengutronix.de> (raw)
In-Reply-To: <20221005111214.148844-1-m.felsch@pengutronix.de>
On Wed, Oct 05, 2022 at 01:12:08PM +0200, Marco Felsch wrote:
> Commit fe181ffda9 ("RISC-V: support incoherent I-Cache") added the
> support to handle non-coherent caches and introduced the HAS_CACHE
> Kconfig symbol. The symbol must be used with CONFIG_ prefixed since this
> is the final Kconfig symbol which can be used within the code.
>
> Fixes: fe181ffda9 ("RISC-V: support incoherent I-Cache")
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
> arch/riscv/include/asm/cache.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks
Sascha
>
> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> index 9a0b9326b2..6d69ed49bd 100644
> --- a/arch/riscv/include/asm/cache.h
> +++ b/arch/riscv/include/asm/cache.h
> @@ -8,7 +8,7 @@
>
> static inline void local_flush_icache_all(void)
> {
> -#ifdef HAS_CACHE
> +#ifdef CONFIG_HAS_CACHE
> asm volatile ("fence.i" ::: "memory");
> #endif
> }
> --
> 2.30.2
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
prev parent reply other threads:[~2022-10-07 8:32 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-05 11:12 Marco Felsch
2022-10-05 11:12 ` [PATCH v2 2/7] RISC-V: add riscv_vendor_id() support Marco Felsch
2022-10-05 11:12 ` [PATCH v2 3/7] RISC-V: import vendorid list from linux Marco Felsch
2022-10-05 11:12 ` [PATCH v2 4/7] RISC-V: use m/sscratch registers for barebox_riscv_pbl_flags Marco Felsch
2022-10-05 11:12 ` [PATCH v2 5/7] RISC-V: implement cache-management errata for T-Head SoCs Marco Felsch
2022-10-05 11:12 ` [PATCH v2 6/7] RISC-V: squash 64bit defconfigs into rv64i_defconfig Marco Felsch
2022-10-22 7:55 ` Antony Pavlov
2022-10-24 7:53 ` Marco Felsch
2022-10-24 8:20 ` Ahmad Fatoum
2022-10-05 11:12 ` [PATCH v2 7/7] RISC-V: add Allwinner Sun20i D1 Nezha support Marco Felsch
2022-10-07 8:30 ` Sascha Hauer [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221007083007.GY986@pengutronix.de \
--to=sha@pengutronix.de \
--cc=barebox@lists.infradead.org \
--cc=m.felsch@pengutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox