* [RFT PATCH master 2/3] soc: imx: imx8m-featctrl: check if all bits are set
2022-10-17 13:49 [RFT PATCH master 0/3] soc: imx8m-featctrl: fixes and first 8MP support Ahmad Fatoum
2022-10-17 13:49 ` [RFT PATCH master 1/3] dt-bindings: features: imx8m: fix typo in constant Ahmad Fatoum
@ 2022-10-17 13:49 ` Ahmad Fatoum
2022-10-17 13:49 ` [RFT PATCH master 3/3] ARM: i.MX8MP: add feature controller support for Plus Ahmad Fatoum
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Ahmad Fatoum @ 2022-10-17 13:49 UTC (permalink / raw)
To: barebox; +Cc: Hans Christian Lonstad, Ahmad Fatoum
The bits are not documented in the reference manual, so the bit masks
were taken from NXP code written for U-Boot. There, checking is done
for whether any bit is set. For 8MP however, all-bits-set is checked.
Testing on i.MX8MM shows that all bits are set though, so switch to
that for uniformity.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/soc/imx/imx8m-featctrl.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/imx/imx8m-featctrl.c b/drivers/soc/imx/imx8m-featctrl.c
index 480c80e6c1d9..1798d0fc2863 100644
--- a/drivers/soc/imx/imx8m-featctrl.c
+++ b/drivers/soc/imx/imx8m-featctrl.c
@@ -28,6 +28,11 @@ static int imx8m_feat_check(struct feature_controller *feat, int idx)
return test_bit(idx, priv->features) ? FEATCTRL_OKAY : FEATCTRL_GATED;
}
+static inline bool is_fused(u32 val, u32 bitmask)
+{
+ return bitmask && (val & bitmask) == bitmask;
+}
+
int imx8m_feat_ctrl_init(struct device_d *dev, u32 tester4,
const struct imx8m_featctrl_data *data)
{
@@ -44,9 +49,9 @@ int imx8m_feat_ctrl_init(struct device_d *dev, u32 tester4,
bitmap_fill(features, IMX8M_FEAT_END);
- if (tester4 & data->vpu_bitmask)
+ if (is_fused(tester4, data->vpu_bitmask))
clear_bit(IMX8M_FEAT_VPU, features);
- if (tester4 & data->gpu_bitmask)
+ if (is_fused(tester4, data->gpu_bitmask))
clear_bit(IMX8M_FEAT_GPU, features);
switch (tester4 & 3) {
--
2.30.2
^ permalink raw reply [flat|nested] 6+ messages in thread* [RFT PATCH master 3/3] ARM: i.MX8MP: add feature controller support for Plus
2022-10-17 13:49 [RFT PATCH master 0/3] soc: imx8m-featctrl: fixes and first 8MP support Ahmad Fatoum
2022-10-17 13:49 ` [RFT PATCH master 1/3] dt-bindings: features: imx8m: fix typo in constant Ahmad Fatoum
2022-10-17 13:49 ` [RFT PATCH master 2/3] soc: imx: imx8m-featctrl: check if all bits are set Ahmad Fatoum
@ 2022-10-17 13:49 ` Ahmad Fatoum
2022-10-17 19:46 ` [RFT PATCH master 0/3] soc: imx8m-featctrl: fixes and first 8MP support Hans Christian Lønstad
2022-10-18 8:57 ` Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Ahmad Fatoum @ 2022-10-17 13:49 UTC (permalink / raw)
To: barebox; +Cc: Hans Christian Lonstad, Ahmad Fatoum
Plus has lots of peripherals that need be disabled, depending on fusebox
settings. Some of these are already described in the upstream device tree,
so reference them in the barebox DT and add the necessary glue for
disabling them like we already do on i.MX8MM/N.
We omit CPU fusing for now. These are handled by tester3 and would need
a bit more rework.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/dts/imx8mp.dtsi | 43 ++++++++++++++++++++++++++++
drivers/nvmem/ocotp.c | 9 ++++++
drivers/soc/imx/imx8m-featctrl.c | 20 ++++++++-----
include/dt-bindings/features/imx8m.h | 4 ++-
include/soc/imx8m/featctrl.h | 3 ++
5 files changed, 71 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index b251ebeadab2..4ffc3a8de7c0 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+#include <dt-bindings/features/imx8m.h>
+
/ {
remoteproc_cm7: remoteproc-cm7 {
compatible = "fsl,imx8mp-cm7";
@@ -7,3 +9,44 @@
syscon = <&src>;
};
};
+
+feat: &ocotp {
+ #feature-cells = <1>;
+ barebox,feature-controller;
+};
+
+&pgc_mipi_phy1 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>;
+};
+
+&pgc_gpu2d {
+ barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&pgc_gpu3d {
+ barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&pgc_gpumix {
+ barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&pgc_mediamix {
+ barebox,feature-gates = <&feat IMX8M_FEAT_ISP>;
+};
+
+&pgc_mipi_phy2 {
+ barebox,feature-gates = <&feat IMX8M_FEAT_MIPI_DSI>;
+};
+
+&pgc_ispdwp {
+ barebox,feature-gates = <&feat IMX8M_FEAT_ISP>;
+};
+
+&gpu3d {
+ barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
+
+&gpu2d {
+ barebox,feature-gates = <&feat IMX8M_FEAT_GPU>;
+};
diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c
index 9fcbd1a6a414..08171cb5cde9 100644
--- a/drivers/nvmem/ocotp.c
+++ b/drivers/nvmem/ocotp.c
@@ -890,12 +890,19 @@ static struct imx_ocotp_data vf610_ocotp_data = {
.fuse_read = imx6_fuse_read_addr,
};
+static struct imx8m_featctrl_data imx8mp_featctrl_data = {
+ .gpu_bitmask = 0xc0,
+ .mipi_dsi_bitmask = 0x60000,
+ .isp_bitmask = 0x3,
+};
+
static struct imx_ocotp_data imx8mp_ocotp_data = {
.num_regs = 1024,
.addr_to_offset = imx6sl_addr_to_offset,
.mac_offsets_num = 2,
.mac_offsets = { 0x90, 0x96 },
.format_mac = imx_ocotp_format_mac,
+ .feat = &imx8mp_featctrl_data,
};
static struct imx_ocotp_data imx8mq_ocotp_data = {
@@ -911,6 +918,7 @@ static struct imx_ocotp_data imx8mq_ocotp_data = {
static struct imx8m_featctrl_data imx8mm_featctrl_data = {
.vpu_bitmask = 0x1c0000,
+ .check_cpus = true,
};
static struct imx_ocotp_data imx8mm_ocotp_data = {
@@ -927,6 +935,7 @@ static struct imx_ocotp_data imx8mm_ocotp_data = {
static struct imx8m_featctrl_data imx8mn_featctrl_data = {
.gpu_bitmask = 0x1000000,
+ .check_cpus = true,
};
static struct imx_ocotp_data imx8mn_ocotp_data = {
diff --git a/drivers/soc/imx/imx8m-featctrl.c b/drivers/soc/imx/imx8m-featctrl.c
index 1798d0fc2863..f2c57ac136ad 100644
--- a/drivers/soc/imx/imx8m-featctrl.c
+++ b/drivers/soc/imx/imx8m-featctrl.c
@@ -53,13 +53,19 @@ int imx8m_feat_ctrl_init(struct device_d *dev, u32 tester4,
clear_bit(IMX8M_FEAT_VPU, features);
if (is_fused(tester4, data->gpu_bitmask))
clear_bit(IMX8M_FEAT_GPU, features);
-
- switch (tester4 & 3) {
- case 0b11:
- clear_bit(IMX8M_FEAT_CPU_DUAL, features);
- fallthrough;
- case 0b10:
- clear_bit(IMX8M_FEAT_CPU_QUAD, features);
+ if (is_fused(tester4, data->mipi_dsi_bitmask))
+ clear_bit(IMX8M_FEAT_MIPI_DSI, features);
+ if (is_fused(tester4, data->isp_bitmask))
+ clear_bit(IMX8M_FEAT_ISP, features);
+
+ if (data->check_cpus) {
+ switch (tester4 & 3) {
+ case 0b11:
+ clear_bit(IMX8M_FEAT_CPU_DUAL, features);
+ fallthrough;
+ case 0b10:
+ clear_bit(IMX8M_FEAT_CPU_QUAD, features);
+ }
}
priv->feat.dev = dev;
diff --git a/include/dt-bindings/features/imx8m.h b/include/dt-bindings/features/imx8m.h
index 8de69ba28b26..e1ed40413ca2 100644
--- a/include/dt-bindings/features/imx8m.h
+++ b/include/dt-bindings/features/imx8m.h
@@ -8,7 +8,9 @@
#define IMX8M_FEAT_CPU_QUAD 2
#define IMX8M_FEAT_VPU 3
#define IMX8M_FEAT_GPU 4
+#define IMX8M_FEAT_MIPI_DSI 5
+#define IMX8M_FEAT_ISP 6
-#define IMX8M_FEAT_END 5
+#define IMX8M_FEAT_END 7
#endif
diff --git a/include/soc/imx8m/featctrl.h b/include/soc/imx8m/featctrl.h
index af94995a916a..b3eb1a56a5f6 100644
--- a/include/soc/imx8m/featctrl.h
+++ b/include/soc/imx8m/featctrl.h
@@ -9,6 +9,9 @@
struct imx8m_featctrl_data {
u32 vpu_bitmask;
u32 gpu_bitmask;
+ u32 mipi_dsi_bitmask;
+ u32 isp_bitmask;
+ bool check_cpus;
};
#ifdef CONFIG_IMX8M_FEATCTRL
--
2.30.2
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [RFT PATCH master 0/3] soc: imx8m-featctrl: fixes and first 8MP support
2022-10-17 13:49 [RFT PATCH master 0/3] soc: imx8m-featctrl: fixes and first 8MP support Ahmad Fatoum
` (3 preceding siblings ...)
2022-10-17 19:46 ` [RFT PATCH master 0/3] soc: imx8m-featctrl: fixes and first 8MP support Hans Christian Lønstad
@ 2022-10-18 8:57 ` Sascha Hauer
4 siblings, 0 replies; 6+ messages in thread
From: Sascha Hauer @ 2022-10-18 8:57 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, Hans Christian Lonstad
On Mon, Oct 17, 2022 at 03:49:26PM +0200, Ahmad Fatoum wrote:
> Newer upstream kernels may fail to boot with less featureful 8MP SoCs,
> because barebox doesn't fix the DT up appropriately. Fix that.
>
> @Hans, could you give this a test? I tested on 8MM only.
>
> Ahmad Fatoum (3):
> dt-bindings: features: imx8m: fix typo in constant
> soc: imx: imx8m-featctrl: check if all bits are set
> ARM: i.MX8MP: add feature controller support for Plus
>
Applied, thanks
Sascha
> arch/arm/dts/imx8mp.dtsi | 43 ++++++++++++++++++++++++++++
> drivers/nvmem/ocotp.c | 9 ++++++
> drivers/soc/imx/imx8m-featctrl.c | 29 +++++++++++++------
> include/dt-bindings/features/imx8m.h | 6 ++--
> include/soc/imx8m/featctrl.h | 3 ++
> 5 files changed, 79 insertions(+), 11 deletions(-)
>
> --
> 2.30.2
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 6+ messages in thread