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X-OriginatorOrg: leica-geosystems.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2023 10:01:24.1689 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 681a2b9c-ac47-4314-074f-08daf3bacc41 X-MS-Exchange-CrossTenant-Id: 1b16ab3e-b8f6-4fe3-9f3e-2db7fe549f6a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=1b16ab3e-b8f6-4fe3-9f3e-2db7fe549f6a;Ip=[193.8.40.94];Helo=[aherlnxbspsrv01.lgs-net.com] X-MS-Exchange-CrossTenant-AuthSource: AM0EUR02FT035.eop-EUR02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR06MB4358 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230111_020128_691342_FA75D973 X-CRM114-Status: GOOD ( 14.69 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.8 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH v2 1/1] ARM: i.MX8M: add PCA9450 PMIC on rev-b EVK X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Configure and setup the PMIC found on rev-b EVKs. The code is algiend with how imx8mn-evk handles both PMIC variants: pca9450 vs bd71837 Signed-off-by: Johannes Schneider --- arch/arm/boards/nxp-imx8mm-evk/lowlevel.c | 51 +++++++++++++++-------- 1 file changed, 34 insertions(+), 17 deletions(-) diff --git a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c index 6132df53ec..409554c2d5 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mm-evk/lowlevel.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,25 @@ static void setup_uart(void) putc_ll('>'); } +static struct pmic_config pca9450_cfg[] = { + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + { PCA9450_BUCK123_DVS, 0x29 }, + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + { PCA9450_BUCK1OUT_DVS0, 0x1C }, + /* Set DVS1 to 0.85v for suspend */ + /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ + { PCA9450_BUCK1OUT_DVS1, 0x14 }, + { PCA9450_BUCK1CTRL, 0x59 }, + + /* set WDOG_B_CFG to cold reset */ + { PCA9450_RESET_CTRL, 0xA1 }, +}; + static struct pmic_config bd71837_cfg[] = { /* decrease RESET key long push time from the default 10s to 10ms */ { BD718XX_PWRONCONFIG1, 0x0 }, @@ -51,21 +71,6 @@ static struct pmic_config bd71837_cfg[] = { { BD718XX_REGLOCK, 0x11 }, }; -static void power_init_board(void) -{ - struct pbl_i2c *i2c; - - imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL); - imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA); - - imx8mm_early_clock_init(); - imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); - - i2c = imx8m_i2c_early_init(IOMEM(MX8MQ_I2C1_BASE_ADDR)); - - pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg)); -} - extern struct dram_timing_info imx8mm_evk_dram_timing; static void start_atf(void) @@ -78,8 +83,20 @@ static void start_atf(void) if (current_el() != 3) return; - power_init_board(); - imx8mm_ddr_init(&imx8mm_evk_dram_timing, DRAM_TYPE_LPDDR4); + imx8mm_setup_pad(IMX8MM_PAD_I2C1_SCL_I2C1_SCL); + imx8mm_setup_pad(IMX8MM_PAD_I2C1_SDA_I2C1_SDA); + + imx8mm_early_clock_init(); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MM_I2C1_BASE_ADDR)); + + imx8mm_ddr_init(&imx8mm_evk_lpddr4_timing, DRAM_TYPE_LPDDR4); + if (i2c_dev_probe(i2c, 0x25, true) == 0) { + pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg)); + } else { + pmic_configure(i2c, 0x4b, bd71837_cfg, ARRAY_SIZE(bd71837_cfg)); + } imx8mm_load_and_start_image_via_tfa(); } -- 2.25.1