[PATCH v2 1/2] imx6-mmdc: Work around ERR050070

[John Watts <contact@jookia.org>]

The MPWLGCR registers clear the error bits before software can read them,
so rely on the MPWLHWERR registers for error reporting instead.

This errata was announced in 2019 but it seems to apply to all chip revisions.

U-Boot contains a different workaround where it instead checks the calibration
data for the result 0x001F001F (maximum delay) and flag that as a failure.
I can't find the origin of this workaround but I first saw it in the Novena
source code, though I asked Sean Cross and he suggested it was from Freescale.

While we're at it, fix the comment implying this code only checks PHY0 in x32
configuration. This is wrong and misleading.

Signed-off-by: John Watts <contact@jookia.org>
---
Changes v1 -> v2:
- Added a wall of text explaining what the code does and why
- wlcalib_failed now reads from the ips register correctly
---
 arch/arm/mach-imx/imx6-mmdc.c              | 30 +++++++++++++++++++---
 arch/arm/mach-imx/include/mach/imx6-mmdc.h |  1 +
 2 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
index 00b8d30d69..45e1b030d3 100644
--- a/arch/arm/mach-imx/imx6-mmdc.c
+++ b/arch/arm/mach-imx/imx6-mmdc.c
@@ -11,6 +11,30 @@
 #include <mach/imx6-regs.h>
 #include <mach/imx6.h>
 
+static bool wlcalib_failed(void __iomem *ips)
+{
+	/*
+	 * The i.MX 6 reference manual specifies that an MMDC flags reports
+	 * write calibration errors in the MPWLGCR register's HW_WL_ERR field.
+	 *
+	 * ERR050070 specifies that this doesn't work and we should check
+	 * the MPWLHWERR register instead which reports which write leveling
+	 * steps succeeded or failed on a per-byte basis.
+	 *
+	 * Check each byte to see which steps succeeded. If no steps succeeded
+	 * then declare the calibration a failure.
+	*/
+
+	int i;
+
+	for (i = 0; i < 4; ++i) {
+		if (readb(ips + MPWLHWERR + i) == 0)
+			return true;
+	}
+
+	return false;
+}
+
 int mmdc_do_write_level_calibration(void)
 {
 	u32 esdmisc_val, zq_val;
@@ -56,11 +80,9 @@ int mmdc_do_write_level_calibration(void)
 	/* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */
 	while (readl(P0_IPS + MPWLGCR) & 0x00000001);
 
-	/* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */
-	if ((readl(P0_IPS + MPWLGCR) & 0x00000F00) ||
-			(readl(P1_IPS + MPWLGCR) & 0x00000F00)) {
+	/* check for any errors on both PHYs */
+	if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
 		errorcount++;
-	}
 
 	pr_debug("Write leveling calibration completed\n");
 
diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
index bda20aba17..098ba4f5bf 100644
--- a/arch/arm/mach-imx/include/mach/imx6-mmdc.h
+++ b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
@@ -18,6 +18,7 @@
 #define MPWLGCR		0x808
 #define MPWLDECTRL0	0x80c
 #define MPWLDECTRL1	0x810
+#define MPWLHWERR	0x878
 #define MPPDCMPR1	0x88c
 #define MPSWDAR		0x894
 #define MPRDDLCTL	0x848
-- 
2.39.0