* [PATCH 2/2] imx6-mmdc: Revert calibration configuration on failure
2023-01-23 20:18 [PATCH 1/2] imx6-mmdc: Work around ERR050070 John Watts
@ 2023-01-23 20:18 ` John Watts
2023-01-24 8:29 ` Ahmad Fatoum
2023-01-24 8:27 ` [PATCH 1/2] imx6-mmdc: Work around ERR050070 Ahmad Fatoum
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: John Watts @ 2023-01-23 20:18 UTC (permalink / raw)
To: barebox; +Cc: John Watts
When calibration fails it will clobber the existing configuration,
even if the configuration was working but not ideal.
Reverting calibration from a known bad value to a possibly good value
gives a better chance of the memory working.
I've tested this on the Novena board and had good success with it.
U-Boot implements a similar solution in its write level calibration.
Signed-off-by: John Watts <contact@jookia.org>
---
arch/arm/mach-imx/imx6-mmdc.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
index 908771626a..0d50b39566 100644
--- a/arch/arm/mach-imx/imx6-mmdc.c
+++ b/arch/arm/mach-imx/imx6-mmdc.c
@@ -25,11 +25,18 @@ static bool wlcalib_failed(void __iomem *ips)
int mmdc_do_write_level_calibration(void)
{
+ u32 ldectrl[4] = {0};
u32 esdmisc_val, zq_val;
int errorcount = 0;
u32 val;
u32 ddr_mr1 = 0x4;
+ /* Store current calibration data in case of failure */
+ ldectrl[0] = readl(P0_IPS + MPWLDECTRL0);
+ ldectrl[1] = readl(P0_IPS + MPWLDECTRL1);
+ ldectrl[2] = readl(P1_IPS + MPWLDECTRL0);
+ ldectrl[3] = readl(P1_IPS + MPWLDECTRL1);
+
/* disable DDR logic power down timer */
val = readl((P0_IPS + MDPDC));
val &= 0xffff00ff;
@@ -69,8 +76,14 @@ int mmdc_do_write_level_calibration(void)
while (readl(P0_IPS + MPWLGCR) & 0x00000001);
/* check for any errors on both PHYs */
- if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
+ if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS)) {
+ pr_debug("Calibration failed, rolling back calibration data\n");
+ writel(ldectrl[0], P0_IPS + MPWLDECTRL0);
+ writel(ldectrl[1], P0_IPS + MPWLDECTRL1);
+ writel(ldectrl[2], P1_IPS + MPWLDECTRL0);
+ writel(ldectrl[3], P1_IPS + MPWLDECTRL1);
errorcount++;
+ }
pr_debug("Write leveling calibration completed\n");
--
2.39.0
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/2] imx6-mmdc: Revert calibration configuration on failure
2023-01-23 20:18 ` [PATCH 2/2] imx6-mmdc: Revert calibration configuration on failure John Watts
@ 2023-01-24 8:29 ` Ahmad Fatoum
2023-01-24 12:01 ` John Watts
0 siblings, 1 reply; 11+ messages in thread
From: Ahmad Fatoum @ 2023-01-24 8:29 UTC (permalink / raw)
To: John Watts, barebox
On 23.01.23 21:18, John Watts wrote:
> When calibration fails it will clobber the existing configuration,
> even if the configuration was working but not ideal.
>
> Reverting calibration from a known bad value to a possibly good value
> gives a better chance of the memory working.
>
> I've tested this on the Novena board and had good success with it.
> U-Boot implements a similar solution in its write level calibration.
>
> Signed-off-by: John Watts <contact@jookia.org>
> ---
> arch/arm/mach-imx/imx6-mmdc.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
> index 908771626a..0d50b39566 100644
> --- a/arch/arm/mach-imx/imx6-mmdc.c
> +++ b/arch/arm/mach-imx/imx6-mmdc.c
> @@ -25,11 +25,18 @@ static bool wlcalib_failed(void __iomem *ips)
>
> int mmdc_do_write_level_calibration(void)
> {
> + u32 ldectrl[4] = {0};
Initial value never read back.
> u32 esdmisc_val, zq_val;
> int errorcount = 0;
> u32 val;
> u32 ddr_mr1 = 0x4;
>
> + /* Store current calibration data in case of failure */
> + ldectrl[0] = readl(P0_IPS + MPWLDECTRL0);
> + ldectrl[1] = readl(P0_IPS + MPWLDECTRL1);
> + ldectrl[2] = readl(P1_IPS + MPWLDECTRL0);
> + ldectrl[3] = readl(P1_IPS + MPWLDECTRL1);
> +
> /* disable DDR logic power down timer */
> val = readl((P0_IPS + MDPDC));
> val &= 0xffff00ff;
> @@ -69,8 +76,14 @@ int mmdc_do_write_level_calibration(void)
> while (readl(P0_IPS + MPWLGCR) & 0x00000001);
>
> /* check for any errors on both PHYs */
> - if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
> + if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS)) {
> + pr_debug("Calibration failed, rolling back calibration data\n");
Still you only restore P0 calibration data, even if it succeeded,
but P1 failed. Is this intended?
> + writel(ldectrl[0], P0_IPS + MPWLDECTRL0);
> + writel(ldectrl[1], P0_IPS + MPWLDECTRL1);
> + writel(ldectrl[2], P1_IPS + MPWLDECTRL0);
> + writel(ldectrl[3], P1_IPS + MPWLDECTRL1);
> errorcount++;
> + }
>
> pr_debug("Write leveling calibration completed\n");
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/2] imx6-mmdc: Revert calibration configuration on failure
2023-01-24 8:29 ` Ahmad Fatoum
@ 2023-01-24 12:01 ` John Watts
2023-01-24 12:07 ` Ahmad Fatoum
0 siblings, 1 reply; 11+ messages in thread
From: John Watts @ 2023-01-24 12:01 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Tue, Jan 24, 2023 at 09:29:02AM +0100, Ahmad Fatoum wrote:
> > int mmdc_do_write_level_calibration(void)
> > {
> > + u32 ldectrl[4] = {0};
>
> Initial value never read back.
>
Remove the = {0}?
> > /* check for any errors on both PHYs */
> > - if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
> > + if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS)) {
> > + pr_debug("Calibration failed, rolling back calibration data\n");
>
> Still you only restore P0 calibration data, even if it succeeded,
> but P1 failed. Is this intended?
Not quite sure what you mean. I restore both P0 and P1 calibration data I
think?
If you're asking whether it is correct behaviour to REVERT all calibration
data, instead of for each channel, I'm not sure. It seems like the safest
thing to do to me since it's unclear why the calibration process has failed.
This is the behaviour U-Boot does and seems to work in the wild.
John.
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 2/2] imx6-mmdc: Revert calibration configuration on failure
2023-01-24 12:01 ` John Watts
@ 2023-01-24 12:07 ` Ahmad Fatoum
0 siblings, 0 replies; 11+ messages in thread
From: Ahmad Fatoum @ 2023-01-24 12:07 UTC (permalink / raw)
To: John Watts; +Cc: barebox
On 24.01.23 13:01, John Watts wrote:
> On Tue, Jan 24, 2023 at 09:29:02AM +0100, Ahmad Fatoum wrote:
>>> int mmdc_do_write_level_calibration(void)
>>> {
>>> + u32 ldectrl[4] = {0};
>>
>> Initial value never read back.
>>
>
> Remove the = {0}?
Ye.
>
>>> /* check for any errors on both PHYs */
>>> - if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
>>> + if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS)) {
>>> + pr_debug("Calibration failed, rolling back calibration data\n");
>>
>> Still you only restore P0 calibration data, even if it succeeded,
>> but P1 failed. Is this intended?
>
> Not quite sure what you mean. I restore both P0 and P1 calibration data I
> think?
Was a bit too early for me. I overlooked this somwhow.
>
> If you're asking whether it is correct behaviour to REVERT all calibration
> data, instead of for each channel, I'm not sure. It seems like the safest
> thing to do to me since it's unclear why the calibration process has failed.
>
> This is the behaviour U-Boot does and seems to work in the wild.
Sorry for the noise,
Ahmad
>
> John.
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] imx6-mmdc: Work around ERR050070
2023-01-23 20:18 [PATCH 1/2] imx6-mmdc: Work around ERR050070 John Watts
2023-01-23 20:18 ` [PATCH 2/2] imx6-mmdc: Revert calibration configuration on failure John Watts
@ 2023-01-24 8:27 ` Ahmad Fatoum
2023-01-24 11:48 ` John Watts
2023-01-24 17:41 ` [PATCH v2 " John Watts
2023-01-24 17:41 ` [PATCH v2 2/2] imx6-mmdc: Revert calibration configuration on failure John Watts
3 siblings, 1 reply; 11+ messages in thread
From: Ahmad Fatoum @ 2023-01-24 8:27 UTC (permalink / raw)
To: John Watts, barebox
On 23.01.23 21:18, John Watts wrote:
> The MPWLGCR registers clear the error bits before software can read them,
> so rely on the MPWLHWERR registers for error reporting instead.
>
> This errata was announced in 2019 and seems to apply to all chip revisions.
>
> U-Boot contains a different workaround where it checks the calibration data
> for the result 0x001F001F (maximum delay) and flag that as a failure.
> This workaround seems to first publicly appear in the Novena U-Boot code
> and originate from Freescale internal code or documentation.
>
> While we're at it, fix the comment implying this code only checks PHY0 in x32
> configuration. This is wrong and misleading.
>
> Signed-off-by: John Watts <contact@jookia.org>
> ---
> arch/arm/mach-imx/imx6-mmdc.c | 18 ++++++++++++++----
> arch/arm/mach-imx/include/mach/imx6-mmdc.h | 1 +
> 2 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
> index 00b8d30d69..908771626a 100644
> --- a/arch/arm/mach-imx/imx6-mmdc.c
> +++ b/arch/arm/mach-imx/imx6-mmdc.c
> @@ -11,6 +11,18 @@
> #include <mach/imx6-regs.h>
> #include <mach/imx6.h>
>
> +static bool wlcalib_failed(void __iomem *ips)
> +{
> + int i;
> +
> + for (i = 0; i < 4; ++i) {
> + if (readb(P0_IPS + MPWLHWERR + i) == 0)
s/P0_OPS/ips/ ?
Also does it need to be bytewise reads? If not, you could rewrite
as return readl(ips + MPWLHWERR) == 0;
> + return true;
Write level calibration has failed when MPWLHWERR == 0 and succeeded
when there is some other value? That sounds odd.
> + }
> +
> + return false;
> +}
> +
> int mmdc_do_write_level_calibration(void)
> {
> u32 esdmisc_val, zq_val;
> @@ -56,11 +68,9 @@ int mmdc_do_write_level_calibration(void)
> /* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */
> while (readl(P0_IPS + MPWLGCR) & 0x00000001);
>
> - /* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */
> - if ((readl(P0_IPS + MPWLGCR) & 0x00000F00) ||
> - (readl(P1_IPS + MPWLGCR) & 0x00000F00)) {
> + /* check for any errors on both PHYs */
> + if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
> errorcount++;
> - }
>
> pr_debug("Write leveling calibration completed\n");
>
> diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
> index bda20aba17..098ba4f5bf 100644
> --- a/arch/arm/mach-imx/include/mach/imx6-mmdc.h
> +++ b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
> @@ -18,6 +18,7 @@
> #define MPWLGCR 0x808
> #define MPWLDECTRL0 0x80c
> #define MPWLDECTRL1 0x810
> +#define MPWLHWERR 0x878
> #define MPPDCMPR1 0x88c
> #define MPSWDAR 0x894
> #define MPRDDLCTL 0x848
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 1/2] imx6-mmdc: Work around ERR050070
2023-01-24 8:27 ` [PATCH 1/2] imx6-mmdc: Work around ERR050070 Ahmad Fatoum
@ 2023-01-24 11:48 ` John Watts
2023-01-24 11:58 ` Ahmad Fatoum
0 siblings, 1 reply; 11+ messages in thread
From: John Watts @ 2023-01-24 11:48 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Tue, Jan 24, 2023 at 09:27:42AM +0100, Ahmad Fatoum wrote:
> > +static bool wlcalib_failed(void __iomem *ips)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < 4; ++i) {
> > + if (readb(P0_IPS + MPWLHWERR + i) == 0)
>
> s/P0_OPS/ips/ ?
Oops, good catch! Will fix in V2.
>
> Also does it need to be bytewise reads? If not, you could rewrite
> as return readl(ips + MPWLHWERR) == 0;
The MPWHLHWERR register contains 4 bytes giving some status for each lane,
that would only fail if all lanes fail which is different behaviour to
the existing behaviour fails if any lanes fail at calibrating.
>
> > + return true;
>
> Write level calibration has failed when MPWLHWERR == 0 and succeeded
> when there is some other value? That sounds odd.
It is odd, but that's what the data sheet says, the errata says and what
and what seem. Maybe I should note it down?
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 1/2] imx6-mmdc: Work around ERR050070
2023-01-24 11:48 ` John Watts
@ 2023-01-24 11:58 ` Ahmad Fatoum
0 siblings, 0 replies; 11+ messages in thread
From: Ahmad Fatoum @ 2023-01-24 11:58 UTC (permalink / raw)
To: John Watts; +Cc: barebox
On 24.01.23 12:48, John Watts wrote:
> On Tue, Jan 24, 2023 at 09:27:42AM +0100, Ahmad Fatoum wrote:
>>> +static bool wlcalib_failed(void __iomem *ips)
>>> +{
>>> + int i;
>>> +
>>> + for (i = 0; i < 4; ++i) {
>>> + if (readb(P0_IPS + MPWLHWERR + i) == 0)
>>
>> s/P0_OPS/ips/ ?
>
> Oops, good catch! Will fix in V2.
>
>>
>> Also does it need to be bytewise reads? If not, you could rewrite
>> as return readl(ips + MPWLHWERR) == 0;
>
> The MPWHLHWERR register contains 4 bytes giving some status for each lane,
> that would only fail if all lanes fail which is different behaviour to
> the existing behaviour fails if any lanes fail at calibrating.
Yes. readl() would've only made sense if 0 was the success, not the
error indicator.
>
>>
>>> + return true;
>>
>> Write level calibration has failed when MPWLHWERR == 0 and succeeded
>> when there is some other value? That sounds odd.
>
> It is odd, but that's what the data sheet says, the errata says and what
> and what seem. Maybe I should note it down?
Yes, a comment would be good.
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/2] imx6-mmdc: Work around ERR050070
2023-01-23 20:18 [PATCH 1/2] imx6-mmdc: Work around ERR050070 John Watts
2023-01-23 20:18 ` [PATCH 2/2] imx6-mmdc: Revert calibration configuration on failure John Watts
2023-01-24 8:27 ` [PATCH 1/2] imx6-mmdc: Work around ERR050070 Ahmad Fatoum
@ 2023-01-24 17:41 ` John Watts
2023-01-25 15:48 ` Sascha Hauer
2023-01-24 17:41 ` [PATCH v2 2/2] imx6-mmdc: Revert calibration configuration on failure John Watts
3 siblings, 1 reply; 11+ messages in thread
From: John Watts @ 2023-01-24 17:41 UTC (permalink / raw)
To: barebox; +Cc: John Watts
The MPWLGCR registers clear the error bits before software can read them,
so rely on the MPWLHWERR registers for error reporting instead.
This errata was announced in 2019 but it seems to apply to all chip revisions.
U-Boot contains a different workaround where it instead checks the calibration
data for the result 0x001F001F (maximum delay) and flag that as a failure.
I can't find the origin of this workaround but I first saw it in the Novena
source code, though I asked Sean Cross and he suggested it was from Freescale.
While we're at it, fix the comment implying this code only checks PHY0 in x32
configuration. This is wrong and misleading.
Signed-off-by: John Watts <contact@jookia.org>
---
Changes v1 -> v2:
- Added a wall of text explaining what the code does and why
- wlcalib_failed now reads from the ips register correctly
---
arch/arm/mach-imx/imx6-mmdc.c | 30 +++++++++++++++++++---
arch/arm/mach-imx/include/mach/imx6-mmdc.h | 1 +
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
index 00b8d30d69..45e1b030d3 100644
--- a/arch/arm/mach-imx/imx6-mmdc.c
+++ b/arch/arm/mach-imx/imx6-mmdc.c
@@ -11,6 +11,30 @@
#include <mach/imx6-regs.h>
#include <mach/imx6.h>
+static bool wlcalib_failed(void __iomem *ips)
+{
+ /*
+ * The i.MX 6 reference manual specifies that an MMDC flags reports
+ * write calibration errors in the MPWLGCR register's HW_WL_ERR field.
+ *
+ * ERR050070 specifies that this doesn't work and we should check
+ * the MPWLHWERR register instead which reports which write leveling
+ * steps succeeded or failed on a per-byte basis.
+ *
+ * Check each byte to see which steps succeeded. If no steps succeeded
+ * then declare the calibration a failure.
+ */
+
+ int i;
+
+ for (i = 0; i < 4; ++i) {
+ if (readb(ips + MPWLHWERR + i) == 0)
+ return true;
+ }
+
+ return false;
+}
+
int mmdc_do_write_level_calibration(void)
{
u32 esdmisc_val, zq_val;
@@ -56,11 +80,9 @@ int mmdc_do_write_level_calibration(void)
/* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */
while (readl(P0_IPS + MPWLGCR) & 0x00000001);
- /* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */
- if ((readl(P0_IPS + MPWLGCR) & 0x00000F00) ||
- (readl(P1_IPS + MPWLGCR) & 0x00000F00)) {
+ /* check for any errors on both PHYs */
+ if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
errorcount++;
- }
pr_debug("Write leveling calibration completed\n");
diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
index bda20aba17..098ba4f5bf 100644
--- a/arch/arm/mach-imx/include/mach/imx6-mmdc.h
+++ b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
@@ -18,6 +18,7 @@
#define MPWLGCR 0x808
#define MPWLDECTRL0 0x80c
#define MPWLDECTRL1 0x810
+#define MPWLHWERR 0x878
#define MPPDCMPR1 0x88c
#define MPSWDAR 0x894
#define MPRDDLCTL 0x848
--
2.39.0
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2 1/2] imx6-mmdc: Work around ERR050070
2023-01-24 17:41 ` [PATCH v2 " John Watts
@ 2023-01-25 15:48 ` Sascha Hauer
0 siblings, 0 replies; 11+ messages in thread
From: Sascha Hauer @ 2023-01-25 15:48 UTC (permalink / raw)
To: John Watts; +Cc: barebox
On Wed, Jan 25, 2023 at 04:41:15AM +1100, John Watts wrote:
> The MPWLGCR registers clear the error bits before software can read them,
> so rely on the MPWLHWERR registers for error reporting instead.
>
> This errata was announced in 2019 but it seems to apply to all chip revisions.
>
> U-Boot contains a different workaround where it instead checks the calibration
> data for the result 0x001F001F (maximum delay) and flag that as a failure.
> I can't find the origin of this workaround but I first saw it in the Novena
> source code, though I asked Sean Cross and he suggested it was from Freescale.
>
> While we're at it, fix the comment implying this code only checks PHY0 in x32
> configuration. This is wrong and misleading.
>
> Signed-off-by: John Watts <contact@jookia.org>
> ---
> Changes v1 -> v2:
> - Added a wall of text explaining what the code does and why
> - wlcalib_failed now reads from the ips register correctly
> ---
> arch/arm/mach-imx/imx6-mmdc.c | 30 +++++++++++++++++++---
> arch/arm/mach-imx/include/mach/imx6-mmdc.h | 1 +
> 2 files changed, 27 insertions(+), 4 deletions(-)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
> index 00b8d30d69..45e1b030d3 100644
> --- a/arch/arm/mach-imx/imx6-mmdc.c
> +++ b/arch/arm/mach-imx/imx6-mmdc.c
> @@ -11,6 +11,30 @@
> #include <mach/imx6-regs.h>
> #include <mach/imx6.h>
>
> +static bool wlcalib_failed(void __iomem *ips)
> +{
> + /*
> + * The i.MX 6 reference manual specifies that an MMDC flags reports
> + * write calibration errors in the MPWLGCR register's HW_WL_ERR field.
> + *
> + * ERR050070 specifies that this doesn't work and we should check
> + * the MPWLHWERR register instead which reports which write leveling
> + * steps succeeded or failed on a per-byte basis.
> + *
> + * Check each byte to see which steps succeeded. If no steps succeeded
> + * then declare the calibration a failure.
> + */
> +
> + int i;
> +
> + for (i = 0; i < 4; ++i) {
> + if (readb(ips + MPWLHWERR + i) == 0)
> + return true;
> + }
> +
> + return false;
> +}
> +
> int mmdc_do_write_level_calibration(void)
> {
> u32 esdmisc_val, zq_val;
> @@ -56,11 +80,9 @@ int mmdc_do_write_level_calibration(void)
> /* Upon completion of this process the MMDC de-asserts the MPWLGCR[HW_WL_EN] */
> while (readl(P0_IPS + MPWLGCR) & 0x00000001);
>
> - /* check for any errors: check both PHYs for x64 configuration, if x32, check only PHY0 */
> - if ((readl(P0_IPS + MPWLGCR) & 0x00000F00) ||
> - (readl(P1_IPS + MPWLGCR) & 0x00000F00)) {
> + /* check for any errors on both PHYs */
> + if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
> errorcount++;
> - }
>
> pr_debug("Write leveling calibration completed\n");
>
> diff --git a/arch/arm/mach-imx/include/mach/imx6-mmdc.h b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
> index bda20aba17..098ba4f5bf 100644
> --- a/arch/arm/mach-imx/include/mach/imx6-mmdc.h
> +++ b/arch/arm/mach-imx/include/mach/imx6-mmdc.h
> @@ -18,6 +18,7 @@
> #define MPWLGCR 0x808
> #define MPWLDECTRL0 0x80c
> #define MPWLDECTRL1 0x810
> +#define MPWLHWERR 0x878
> #define MPPDCMPR1 0x88c
> #define MPSWDAR 0x894
> #define MPRDDLCTL 0x848
> --
> 2.39.0
>
>
>
--
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 2/2] imx6-mmdc: Revert calibration configuration on failure
2023-01-23 20:18 [PATCH 1/2] imx6-mmdc: Work around ERR050070 John Watts
` (2 preceding siblings ...)
2023-01-24 17:41 ` [PATCH v2 " John Watts
@ 2023-01-24 17:41 ` John Watts
3 siblings, 0 replies; 11+ messages in thread
From: John Watts @ 2023-01-24 17:41 UTC (permalink / raw)
To: barebox; +Cc: John Watts
When calibration fails it's possible the existing configuration will
work fine. At least, this is the case on my board.
This patch also fixes a comment that incorrectly states that only
PHY0 is checked when in reality both always are.
Signed-off-by: John Watts <contact@jookia.org>
---
Changes v1 -> v2:
- No longer initialized ldectrl with zeroes
---
arch/arm/mach-imx/imx6-mmdc.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
index 45e1b030d3..e0497071d1 100644
--- a/arch/arm/mach-imx/imx6-mmdc.c
+++ b/arch/arm/mach-imx/imx6-mmdc.c
@@ -37,11 +37,18 @@ static bool wlcalib_failed(void __iomem *ips)
int mmdc_do_write_level_calibration(void)
{
+ u32 ldectrl[4];
u32 esdmisc_val, zq_val;
int errorcount = 0;
u32 val;
u32 ddr_mr1 = 0x4;
+ /* Store current calibration data in case of failure */
+ ldectrl[0] = readl(P0_IPS + MPWLDECTRL0);
+ ldectrl[1] = readl(P0_IPS + MPWLDECTRL1);
+ ldectrl[2] = readl(P1_IPS + MPWLDECTRL0);
+ ldectrl[3] = readl(P1_IPS + MPWLDECTRL1);
+
/* disable DDR logic power down timer */
val = readl((P0_IPS + MDPDC));
val &= 0xffff00ff;
@@ -81,8 +88,14 @@ int mmdc_do_write_level_calibration(void)
while (readl(P0_IPS + MPWLGCR) & 0x00000001);
/* check for any errors on both PHYs */
- if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS))
+ if (wlcalib_failed(P0_IPS) || wlcalib_failed(P1_IPS)) {
+ pr_debug("Calibration failed, rolling back calibration data\n");
+ writel(ldectrl[0], P0_IPS + MPWLDECTRL0);
+ writel(ldectrl[1], P0_IPS + MPWLDECTRL1);
+ writel(ldectrl[2], P1_IPS + MPWLDECTRL0);
+ writel(ldectrl[3], P1_IPS + MPWLDECTRL1);
errorcount++;
+ }
pr_debug("Write leveling calibration completed\n");
--
2.39.0
^ permalink raw reply [flat|nested] 11+ messages in thread