[PATCH v2 1/3] ARM: i.MX8M: esdctl: limit i.MX8MP early memory size

[PATCH v2 1/3] ARM: i.MX8M: esdctl: limit i.MX8MP early memory size

[Lucas Stach]

Limit detected early memory size to 1GB on i.MX8MP, as the default DT
has a reserved memory region at 0x92400000, which will conflict with
our malloc area in some configurations. Until we can properly parse
and exclude the reserved memory regions in the PBL, just avoid getting
near that DRAM address by limiting the detected size.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/esdctl.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index a704250297bb..043de477a77d 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -947,7 +947,17 @@ void __noreturn imx8mn_barebox_entry(void *boarddata)
 
 void __noreturn imx8mp_barebox_entry(void *boarddata)
 {
-	imx8m_barebox_entry(boarddata, 32);
+	/*
+	 * Limit detected early memory size to 1GB on i.MX8MP, as the default
+	 * DT has a reserved memory region at 0x92400000, which will conflict
+	 * with our malloc area in some configurations. Until we can properly
+	 * parse and exclude the reserved memory regions in the PBL, just avoid
+	 * getting near that DRAM address by limiting the detected size.
+	 */
+	barebox_arm_entry(MX8M_DDR_CSD1_BASE_ADDR,
+			  min_t(resource_size_t, SZ_1G,
+				imx8m_barebox_earlymem_size(32)),
+			  boarddata);
 }
 
 void __noreturn imx8mq_barebox_entry(void *boarddata)
-- 
2.39.1

[PATCH v2 2/3] ARM: i.MX8M: esdctl: use common compatible to detect i.MX8MQ/MM/MP DDRC

[Lucas Stach]

All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
size detection works the same on most of them, with the only exception
being the i.MX8MM, which only has a 16bit data bus, there is no need to
match the more specific compatibles for i.MX8MQ/MM/MP.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/esdctl.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 043de477a77d..fc6db25de9e4 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -652,7 +652,7 @@ static __maybe_unused struct imx_esdctl_data vf610_data = {
 	.add_mem = vf610_ddrmc_add_mem,
 };
 
-static __maybe_unused struct imx_esdctl_data imx8mq_data = {
+static __maybe_unused struct imx_esdctl_data imx8m_data = {
 	.base0 = MX8M_DDR_CSD1_BASE_ADDR,
 	.add_mem = imx8m_ddrc_add_mem,
 };
@@ -732,14 +732,11 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
 		.compatible = "fsl,vf610-ddrmc",
 		.data = &vf610_data
 	}, {
-		.compatible = "fsl,imx8mm-ddrc",
-		.data = &imx8mq_data
+		.compatible = "fsl,imx8m-ddrc",
+		.data = &imx8m_data
 	}, {
 		.compatible = "fsl,imx8mn-ddrc",
 		.data = &imx8mn_data
-	}, {
-		.compatible = "fsl,imx8mq-ddrc",
-		.data = &imx8mq_data
 	}, {
 		.compatible = "fsl,imx7d-ddrc",
 		.data = &imx7d_data
-- 
2.39.1

Re: [PATCH v2 2/3] ARM: i.MX8M: esdctl: use common compatible to detect i.MX8MQ/MM/MP DDRC

[Marco Felsch]

Hi Lucas,

On 23-02-07, Lucas Stach wrote:
> All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
> size detection works the same on most of them, with the only exception
> being the i.MX8MM, which only has a 16bit data bus, there is no need to
		^
	    i.MX8MN

apart of this the whole series lgtm, so feel free to add my

Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>

> match the more specific compatibles for i.MX8MQ/MM/MP.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  arch/arm/mach-imx/esdctl.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
> index 043de477a77d..fc6db25de9e4 100644
> --- a/arch/arm/mach-imx/esdctl.c
> +++ b/arch/arm/mach-imx/esdctl.c
> @@ -652,7 +652,7 @@ static __maybe_unused struct imx_esdctl_data vf610_data = {
>  	.add_mem = vf610_ddrmc_add_mem,
>  };
>  
> -static __maybe_unused struct imx_esdctl_data imx8mq_data = {
> +static __maybe_unused struct imx_esdctl_data imx8m_data = {
>  	.base0 = MX8M_DDR_CSD1_BASE_ADDR,
>  	.add_mem = imx8m_ddrc_add_mem,
>  };
> @@ -732,14 +732,11 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
>  		.compatible = "fsl,vf610-ddrmc",
>  		.data = &vf610_data
>  	}, {
> -		.compatible = "fsl,imx8mm-ddrc",
> -		.data = &imx8mq_data
> +		.compatible = "fsl,imx8m-ddrc",
> +		.data = &imx8m_data
>  	}, {
>  		.compatible = "fsl,imx8mn-ddrc",
>  		.data = &imx8mn_data
> -	}, {
> -		.compatible = "fsl,imx8mq-ddrc",
> -		.data = &imx8mq_data
>  	}, {
>  		.compatible = "fsl,imx7d-ddrc",
>  		.data = &imx7d_data
> -- 
> 2.39.1
> 
> 
> 

[PATCH v2 3/3] ARM: dts: i.MX8MP: add DDRC compatibles

[Lucas Stach]

The upstream DT currently only provides the Synopsis core compatible
for the DDRC node. Extend this with more machine specific compatibles
to allow our memory size detection to work.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/dts/imx8mp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index 5da79f13d339..778e84318ce7 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -10,6 +10,10 @@
 	};
 };
 
+&edacmc {
+	compatible = "fsl,imx8mp-ddrc", "fsl,imx8m-ddrc", "snps,ddrc-3.80a";
+};
+
 feat: &ocotp {
 	#feature-cells = <1>;
 	barebox,feature-controller;
-- 
2.39.1