[PATCH 0/3] Fix MMC clocks on RK3568

[PATCH 0/3] Fix MMC clocks on RK3568

[Sascha Hauer]

We observed that on RK3568 the eMMC does not work when the SD controller
is not registered. This goes down to wrong enable_count when reparenting
composite clocks due to a set_rate call. This series fixes it.

Sascha

Sascha Hauer (3):
  clk: composite: Give mux/div/gate clks names
  clk: composite: Fix enable_count when reparenting mux
  mci: rockchip-dwcmshc-sdhci: Print less errors

 drivers/clk/clk-composite.c          | 10 +++++++++-
 drivers/clk/rockchip/clk.c           |  3 +++
 drivers/mci/rockchip-dwcmshc-sdhci.c |  6 +++---
 3 files changed, 15 insertions(+), 4 deletions(-)

-- 
2.30.2

[PATCH 1/3] clk: composite: Give mux/div/gate clks names

[Sascha Hauer]

The mux/div/gate clks are never registered with the clk framework,
so names are normally not necessary. At least the mux clk might
end up in a call to clk_set_parent() though. This happens when a
mux shall change its rate and then reparents to the most suitable
parent. To get a better clue which being reparented there give the
mux a name and while at it give the other clocks names as well.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/rockchip/clk.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 6e7bba414f..5c074f526a 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -59,6 +59,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
 		mux->width = mux_width;
 		mux->flags = mux_flags;
 		mux->lock = lock;
+		mux->hw.clk.name = basprintf("%s.mux", name);
 		mux->hw.clk.ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
 							: &clk_mux_ops;
 	}
@@ -74,6 +75,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
 		gate->reg = base + gate_offset;
 		gate->shift = gate_shift;
 		gate->lock = lock;
+		gate->hw.clk.name = basprintf("%s.gate", name);
 		gate->hw.clk.ops = &clk_gate_ops;
 	}
 
@@ -93,6 +95,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
 		div->width = div_width;
 		div->lock = lock;
 		div->table = div_table;
+		div->hw.clk.name = basprintf("%s.div", name);
 		div->hw.clk.ops = (div_flags & CLK_DIVIDER_READ_ONLY)
 						? &clk_divider_ro_ops
 						: &clk_divider_ops;
-- 
2.30.2

[PATCH 2/3] clk: composite: Fix enable_count when reparenting mux

[Sascha Hauer]

A mux in a composite clk may implement a set_rate callback which
in the mux results in reparenting the composite clk. clk_set_rate()
is called on the mux inside the composite clk, not on the composite
clk itself. Only the latter has the correct enable_count though,
so transfer the enable_count to the mux before calling its set_rate
op.
Without this patch the clk frameworks sees the enable_count from
the mux (which is 0), so the new parent will never be enabled, even
if the composite clk is enabled.

The wrong behaviour was observed on a RK3568 board:

barebox@Radxa ROCK3 Model A:/ clk_dump cclk_emmc
xin24m (rate 24000000, enable_count: 9, enabled)
    pll_gpll (rate 1188000000, enable_count: 1, enabled)
        gpll (rate 1188000000, enable_count: 5, always enabled)
            gpll_200m (rate 198000000, enable_count: 5, enabled)
                cclk_emmc (rate 198000000, enable_count: 1, enabled)
                    emmc_drv (rate 99000000, enable_count: 0, always enabled)
                    emmc_sample (rate 99000000, enable_count: 0, always enabled)
barebox@Radxa ROCK3 Model A:/ clk_set_rate cclk_emmc 50000000
barebox@Radxa ROCK3 Model A:/ clk_dump cclk_emmc
xin24m (rate 24000000, enable_count: 9, enabled)
    pll_cpll (rate 1000000000, enable_count: 1, enabled)
        cpll (rate 1000000000, enable_count: 2, always enabled)
            cpll_50m (rate 50000000, enable_count: 0, enabled)
                cclk_emmc (rate 50000000, enable_count: 1, enabled)
                    emmc_drv (rate 25000000, enable_count: 0, always enabled)
                    emmc_sample (rate 25000000, enable_count: 0, always enabled)

After the reparenting cclk_emmc has an enable count of 1, but its parent
cpll_50m has an enable count of 0 which must not happen.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/clk-composite.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 45dec790d7..454bfaeb0c 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -89,8 +89,16 @@ static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	if (!(hw->clk.flags & CLK_SET_RATE_NO_REPARENT) &&
 	    mux_clk &&
-	    mux_clk->ops->set_rate)
+	    mux_clk->ops->set_rate) {
+		/*
+		 * We'll call set_rate on the mux clk which in turn results
+		 * in reparenting the mux clk. Make sure the enable count
+		 * (which is stored in the composite clk, not the mux clk)
+		 * is transferred correctly.
+		 */
+		mux_clk->enable_count = hw->clk.enable_count;
 		return mux_clk->ops->set_rate(clk_to_clk_hw(mux_clk), rate, parent_rate);
+	}
 
 	return 0;
 }
-- 
2.30.2

[PATCH 3/3] mci: rockchip-dwcmshc-sdhci: Print less errors

[Sascha Hauer]

Some commands are expected to return errors, for example when a non
SDIO card is tested for being an SDIO card. Lower the priority of
these error messages to dev_dbg().

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/rockchip-dwcmshc-sdhci.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mci/rockchip-dwcmshc-sdhci.c b/drivers/mci/rockchip-dwcmshc-sdhci.c
index 87cbe9836c..4b4e8b7bd6 100644
--- a/drivers/mci/rockchip-dwcmshc-sdhci.c
+++ b/drivers/mci/rockchip-dwcmshc-sdhci.c
@@ -224,7 +224,7 @@ static int rk_sdhci_wait_for_done(struct rk_sdhci_host *host, u32 mask)
 	do {
 		stat = sdhci_read16(&host->sdhci, SDHCI_INT_NORMAL_STATUS);
 		if (stat & SDHCI_INT_ERROR) {
-			dev_err(host->mci.hw_dev, "SDHCI_INT_ERROR: 0x%08x\n",
+			dev_dbg(host->mci.hw_dev, "SDHCI_INT_ERROR: 0x%08x\n",
 				sdhci_read16(&host->sdhci, SDHCI_INT_ERROR_STATUS));
 			return -EPERM;
 		}
@@ -241,9 +241,9 @@ static int rk_sdhci_wait_for_done(struct rk_sdhci_host *host, u32 mask)
 
 static void print_error(struct rk_sdhci_host *host, int cmdidx)
 {
-	dev_err(host->mci.hw_dev,
+	dev_dbg(host->mci.hw_dev,
 		"error while transfering data for command %d\n", cmdidx);
-	dev_err(host->mci.hw_dev, "state = 0x%08x , interrupt = 0x%08x\n",
+	dev_dbg(host->mci.hw_dev, "state = 0x%08x , interrupt = 0x%08x\n",
 		sdhci_read32(&host->sdhci, SDHCI_PRESENT_STATE),
 		sdhci_read32(&host->sdhci, SDHCI_INT_NORMAL_STATUS));
 }
-- 
2.30.2