[PATCH 0/5] ARM: Rockchip: Read amount of memory from DDR controller

[PATCH 0/5] ARM: Rockchip: Read amount of memory from DDR controller

[Sascha Hauer]

This series adds support for reading the amount of memory from
the DDR controller. This helps on boards which come with
different amounts of memory like the Radxa Rock3a.

This series also fixes issues with an upstream TF-A firmware. With this
the IRAM where the bootsource is stored is no longer accessible in
normal mode. We have to read its contents before starting the TF-A.
For this it became necessary to add a common barebox entry function
for rk3568, to get a common place to read the IRAM contents.

Sascha

Ahmad Fatoum (2):
  ARM: Rockchip: implement memory read out from controller
  ARM: Rockchip: make bootsource logic generic to all SoCs

Sascha Hauer (3):
  ARM: dts: rk356x: Add DMC controller node
  ARM: Rockchip: Add rk3568 specific barebox entry function
  ARM: Rockchip: rk3568: use rk3568_barebox_entry()

 arch/arm/boards/pine64-quartz64/lowlevel.c    |  31 +--
 arch/arm/boards/radxa-rock3/lowlevel.c        |  32 +--
 .../rockchip-rk3568-bpi-r2pro/lowlevel.c      |  32 +--
 .../arm/boards/rockchip-rk3568-evb/lowlevel.c |  33 +--
 arch/arm/dts/rk356x.dtsi                      |   5 +
 arch/arm/mach-rockchip/Makefile               |   3 +-
 arch/arm/mach-rockchip/atf.c                  |  25 ++
 arch/arm/mach-rockchip/bootrom.c              |  51 ++++
 arch/arm/mach-rockchip/dmc.c                  | 232 ++++++++++++++++++
 arch/arm/mach-rockchip/rk3568.c               |  29 +--
 include/bootsource.h                          |   1 +
 include/linux/sizes.h                         |   3 +
 include/mach/rockchip/atf.h                   |   2 +
 include/mach/rockchip/bootrom.h               |  32 +++
 include/mach/rockchip/dmc.h                   |  86 +++++++
 include/mach/rockchip/rk3399-regs.h           |   1 +
 include/mach/rockchip/rk3568-regs.h           |   1 +
 17 files changed, 456 insertions(+), 143 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/bootrom.c
 create mode 100644 arch/arm/mach-rockchip/dmc.c
 create mode 100644 include/mach/rockchip/bootrom.h
 create mode 100644 include/mach/rockchip/dmc.h

-- 
2.30.2

[PATCH 1/5] ARM: dts: rk356x: Add DMC controller node

[Sascha Hauer]

There's currently no DMC controller node in the upstream dtsi file.
Add one until it's there.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/rk356x.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 6a9cd14d2d..4de2404b50 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -6,4 +6,9 @@
 		barebox,bootsource-mmc1 = &sdmmc0;
 		barebox,bootsource-mmc2 = &sdmmc1;
 	};
+
+	dmc: memory-controller {
+		compatible = "rockchip,rk3568-dmc";
+		rockchip,pmu = <&pmugrf>;
+	};
 };
-- 
2.30.2

[PATCH 2/5] ARM: Rockchip: implement memory read out from controller

[Sascha Hauer]

From: Ahmad Fatoum <ahmad@a3f.at>

Add a driver to read out the amount of memory from the DDR controller.
The decoding of the registers has been taken from U-Boot. Currently
supported are the RK3399 and the RK3568, but decoding should work on
other Rockchip SoCs as well.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-rockchip/Makefile     |   1 +
 arch/arm/mach-rockchip/dmc.c        | 232 ++++++++++++++++++++++++++++
 include/linux/sizes.h               |   3 +
 include/mach/rockchip/dmc.h         |  86 +++++++++++
 include/mach/rockchip/rk3399-regs.h |   1 +
 include/mach/rockchip/rk3568-regs.h |   1 +
 6 files changed, 324 insertions(+)
 create mode 100644 arch/arm/mach-rockchip/dmc.c
 create mode 100644 include/mach/rockchip/dmc.h

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 2529af7c7e..f6c575854e 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_ARCH_RK3188) += rk3188.o
 obj-$(CONFIG_ARCH_RK3288) += rk3288.o
 obj-pbl-$(CONFIG_ARCH_RK3568) += rk3568.o
 obj-$(CONFIG_ARCH_ROCKCHIP_V8) += bootm.o
+obj-pbl-$(CONFIG_ARCH_ROCKCHIP_V8) += dmc.o
 obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
new file mode 100644
index 0000000000..3a0d835689
--- /dev/null
+++ b/arch/arm/mach-rockchip/dmc.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#define pr_fmt(fmt) "rockchip-dmc: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <asm/barebox-arm.h>
+#include <asm/memory.h>
+#include <pbl.h>
+#include <io.h>
+#include <regmap.h>
+#include <mfd/syscon.h>
+#include <mach/rockchip/dmc.h>
+#include <mach/rockchip/rk3399-regs.h>
+#include <mach/rockchip/rk3568-regs.h>
+
+#define RK3399_PMUGRF_OS_REG2		0x308
+#define RK3399_PMUGRF_OS_REG3		0x30C
+
+#define RK3568_PMUGRF_OS_REG2           0x208
+#define RK3568_PMUGRF_OS_REG3           0x20c
+
+struct rockchip_dmc_region {
+	resource_size_t base, size;
+};
+
+struct rockchip_dmc_drvdata {
+	unsigned int os_reg2;
+	unsigned int os_reg3;
+	const struct rockchip_dmc_region *regions;
+};
+
+static resource_size_t rockchip_sdram_size(u32 sys_reg2, u32 sys_reg3)
+{
+	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
+	resource_size_t chipsize_mb, size_mb = 0;
+	u32 ch;
+	u32 cs1_col;
+	u32 bg = 0;
+	u32 dbw, dram_type;
+	u32 ch_num = 1 + FIELD_GET(SYS_REG_NUM_CH, sys_reg2);
+	u32 version = FIELD_GET(SYS_REG_VERSION, sys_reg3);
+
+	pr_debug("%s(reg2=%x, reg3=%x)\n", __func__, sys_reg2, sys_reg3);
+
+	dram_type = FIELD_GET(SYS_REG_DDRTYPE, sys_reg2);
+
+	if (version >= 3)
+		dram_type |= FIELD_GET(SYS_REG_EXTEND_DDRTYPE, sys_reg3) << 3;
+
+	for (ch = 0; ch < ch_num; ch++) {
+		rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK);
+		cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
+		cs1_col = cs0_col;
+
+		bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+
+		cs0_row = sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK;
+		cs1_row = sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK;
+
+		if (version >= 2) {
+			cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
+				  SYS_REG_CS1_COL_MASK);
+
+			cs0_row |= (sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
+					SYS_REG_EXTEND_CS0_ROW_MASK) << 2;
+
+			if (cs0_row == 7)
+				cs0_row = 12;
+			else
+				cs0_row += 13;
+
+			cs1_row |= (sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
+					SYS_REG_EXTEND_CS1_ROW_MASK) << 2;
+
+			if (cs1_row == 7)
+				cs1_row = 12;
+			else
+				cs1_row += 13;
+		} else {
+			cs0_row += 13;
+			cs1_row += 13;
+		}
+
+		bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & SYS_REG_BW_MASK));
+		row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK;
+
+		if (dram_type == DDR4) {
+			dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & SYS_REG_DBW_MASK;
+			bg = (dbw == 2) ? 2 : 1;
+		}
+
+		chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
+
+		if (rank > 1)
+			chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
+				       (cs0_col - cs1_col));
+		if (row_3_4)
+			chipsize_mb = chipsize_mb * 3 / 4;
+
+		size_mb += chipsize_mb;
+
+		if (rank > 1)
+			pr_debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d "
+				 "cs1_row %d bw %d row_3_4 %d\n",
+				 rank, cs0_col, cs1_col, bk, cs0_row,
+				 cs1_row, bw, row_3_4);
+		else
+			pr_debug("rank %d cs0_col %d bk %d cs0_row %d "
+				 "bw %d row_3_4 %d\n",
+				 rank, cs0_col, bk, cs0_row,
+				 bw, row_3_4);
+	}
+
+	return (resource_size_t)size_mb << 20;
+}
+
+resource_size_t rk3399_ram0_size(void)
+{
+	void __iomem *pmugrf = IOMEM(RK3399_PMUGRF_BASE);
+	u32 sys_reg2, sys_reg3;
+	resource_size_t size;
+
+	sys_reg2 = readl(pmugrf + RK3399_PMUGRF_OS_REG2);
+	sys_reg3 = readl(pmugrf + RK3399_PMUGRF_OS_REG3);
+
+	size = rockchip_sdram_size(sys_reg2, sys_reg3);
+	size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
+
+	pr_debug("%s() = %llu\n", __func__, (u64)size);
+
+	return size;
+}
+
+resource_size_t rk3568_ram0_size(void)
+{
+	void __iomem *pmugrf = IOMEM(RK3568_PMUGRF_BASE);
+	u32 sys_reg2, sys_reg3;
+	resource_size_t size;
+
+	sys_reg2 = readl(pmugrf + RK3568_PMUGRF_OS_REG2);
+	sys_reg3 = readl(pmugrf + RK3568_PMUGRF_OS_REG3);
+
+	size = rockchip_sdram_size(sys_reg2, sys_reg3);
+	size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
+
+	pr_debug("%s() = %llu\n", __func__, (u64)size);
+
+	return size;
+}
+
+static int rockchip_dmc_probe(struct device *dev)
+{
+	const struct rockchip_dmc_drvdata *drvdata;
+	const struct rockchip_dmc_region *region;
+	resource_size_t membase, memsize;
+	struct regmap *regmap;
+	u32 sys_reg2, sys_reg3;
+
+	regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	drvdata = device_get_match_data(dev);
+	if (!drvdata)
+		return -ENOENT;
+
+	regmap_read(regmap, drvdata->os_reg2, &sys_reg2);
+	regmap_read(regmap, drvdata->os_reg3, &sys_reg3);
+
+	memsize = rockchip_sdram_size(sys_reg2, sys_reg3);
+
+	dev_info(dev, "Detected memory size: %pa\n", &memsize);
+
+	region = drvdata->regions;
+
+	if (memsize >= region[0].size) {
+		if (region[1].size)
+			arm_add_mem_device("ram1", region[1].base,
+					   memsize - region[0].size);
+		memsize = region[0].size;
+	}
+
+	/* lowest 10M are shaved off for secure world firmware */
+	membase = 0xa00000;
+
+	return arm_add_mem_device("ram0", membase, memsize - membase);
+}
+
+static const struct rockchip_dmc_region rk3399_regions[] = {
+	{
+		.base = 0x0,
+		.size = SZ_4G - SZ_128M,
+	}, {
+		.base = SZ_4G,
+		.size = SZ_32G,
+	}
+};
+
+static const struct rockchip_dmc_drvdata rk3399_drvdata = {
+	.os_reg2 = RK3399_PMUGRF_OS_REG2,
+	.os_reg3 = RK3399_PMUGRF_OS_REG3,
+	.regions = rk3399_regions,
+};
+
+static const struct rockchip_dmc_drvdata rk3568_drvdata = {
+	.os_reg2 = RK3568_PMUGRF_OS_REG2,
+	.os_reg3 = RK3568_PMUGRF_OS_REG3,
+	.regions = rk3399_regions,
+};
+
+static struct of_device_id rockchip_dmc_dt_ids[] = {
+	{
+		.compatible = "rockchip,rk3399-dmc",
+		.data = &rk3399_drvdata,
+	},
+	{
+		.compatible = "rockchip,rk3568-dmc",
+		.data = &rk3568_drvdata,
+	},
+	{ /* sentinel */ }
+};
+
+static struct driver rockchip_dmc_driver = {
+	.name   = "rockchip-dmc",
+	.probe  = rockchip_dmc_probe,
+	.of_compatible = rockchip_dmc_dt_ids,
+};
+mem_platform_driver(rockchip_dmc_driver);
diff --git a/include/linux/sizes.h b/include/linux/sizes.h
index fbde0bc7e8..1d222daeab 100644
--- a/include/linux/sizes.h
+++ b/include/linux/sizes.h
@@ -47,5 +47,8 @@
 #define SZ_2G				0x80000000
 
 #define SZ_4G				_AC(0x100000000, ULL)
+#define SZ_8G				_AC(0x200000000, ULL)
+#define SZ_16G				_AC(0x400000000, ULL)
+#define SZ_32G				_AC(0x800000000, ULL)
 
 #endif /* __LINUX_SIZES_H__ */
diff --git a/include/mach/rockchip/dmc.h b/include/mach/rockchip/dmc.h
new file mode 100644
index 0000000000..ff197d50a0
--- /dev/null
+++ b/include/mach/rockchip/dmc.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _MACH_ROCKCHIP_DMC_H
+#define _MACH_ROCKCHIP_DMC_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/bitfield.h>
+
+enum {
+	DDR4 = 0,
+	DDR3 = 0x3,
+	LPDDR2 = 0x5,
+	LPDDR3 = 0x6,
+	LPDDR4 = 0x7,
+	UNUSED = 0xFF
+};
+
+/*
+ * sys_reg2 bitfield struct
+ * [31]		row_3_4_ch1
+ * [30]		row_3_4_ch0
+ * [29:28]	chinfo
+ * [27]		rank_ch1
+ * [26:25]	col_ch1
+ * [24]		bk_ch1
+ * [23:22]	low bits of cs0_row_ch1
+ * [21:20]	low bits of cs1_row_ch1
+ * [19:18]	bw_ch1
+ * [17:16]	dbw_ch1;
+ * [15:13]	ddrtype
+ * [12]		channelnum
+ * [11]		rank_ch0
+ * [10:9]	col_ch0,
+ * [8]		bk_ch0
+ * [7:6]	low bits of cs0_row_ch0
+ * [5:4]	low bits of cs1_row_ch0
+ * [3:2]	bw_ch0
+ * [1:0]	dbw_ch0
+ */
+
+#define SYS_REG_DDRTYPE			GENMASK(15, 13)
+#define SYS_REG_NUM_CH			BIT(12)
+#define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
+#define SYS_REG_ROW_3_4_MASK		1
+#define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
+#define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
+#define SYS_REG_RANK_MASK		1
+#define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
+#define SYS_REG_COL_MASK		3
+#define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
+#define SYS_REG_BK_MASK			1
+#define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
+#define SYS_REG_CS0_ROW_MASK		3
+#define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
+#define SYS_REG_CS1_ROW_MASK		3
+#define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
+#define SYS_REG_BW_MASK			3
+#define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
+#define SYS_REG_DBW_MASK		3
+
+/*
+ * sys_reg3 bitfield struct
+ * [7]		high bit of cs0_row_ch1
+ * [6]		high bit of cs1_row_ch1
+ * [5]		high bit of cs0_row_ch0
+ * [4]		high bit of cs1_row_ch0
+ * [3:2]	cs1_col_ch1
+ * [1:0]	cs1_col_ch0
+ */
+#define SYS_REG_VERSION				GENMASK(31, 28)
+#define SYS_REG_EXTEND_DDRTYPE			GENMASK(13, 12)
+#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch)	(5 + (ch) * 2)
+#define SYS_REG_EXTEND_CS0_ROW_MASK		1
+#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch)	(4 + (ch) * 2)
+#define SYS_REG_EXTEND_CS1_ROW_MASK		1
+#define SYS_REG_CS1_COL_SHIFT(ch)		(0 + (ch) * 2)
+#define SYS_REG_CS1_COL_MASK			3
+
+resource_size_t rk3399_ram0_size(void);
+resource_size_t rk3568_ram0_size(void);
+
+#endif
diff --git a/include/mach/rockchip/rk3399-regs.h b/include/mach/rockchip/rk3399-regs.h
index 57033b6510..6db082da9b 100644
--- a/include/mach/rockchip/rk3399-regs.h
+++ b/include/mach/rockchip/rk3399-regs.h
@@ -10,6 +10,7 @@
 #define RK3399_UART3_BASE	0xff1b0000
 #define RK3399_UART4_BASE	0xff370000
 
+#define RK3399_PMUGRF_BASE	0xff320000
 #define RK3399_IRAM_BASE	0xff8c0000
 #define RK3399_STIMER_BASE	0xff8680a0
 
diff --git a/include/mach/rockchip/rk3568-regs.h b/include/mach/rockchip/rk3568-regs.h
index edd5ee268d..55d28790dd 100644
--- a/include/mach/rockchip/rk3568-regs.h
+++ b/include/mach/rockchip/rk3568-regs.h
@@ -16,5 +16,6 @@
 #define RK3568_UART9_BASE	0xfe6d0000
 
 #define RK3568_IRAM_BASE	0xfdcc0000
+#define RK3568_PMUGRF_BASE	0xfdc20000
 
 #endif /* __MACH_RK3568_REGS_H */
-- 
2.30.2

[PATCH 3/5] ARM: Rockchip: Add rk3568 specific barebox entry function

[Sascha Hauer]

Add a rk3568 specific barebox entry function to simplify board
code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-rockchip/atf.c | 22 ++++++++++++++++++++++
 include/mach/rockchip/atf.h  |  2 ++
 2 files changed, 24 insertions(+)

diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
index 93025faf68..a7d626226e 100644
--- a/arch/arm/mach-rockchip/atf.c
+++ b/arch/arm/mach-rockchip/atf.c
@@ -5,6 +5,9 @@
 #include <mach/rockchip/atf.h>
 #include <elf.h>
 #include <asm/atf_common.h>
+#include <asm/barebox-arm.h>
+#include <mach/rockchip/dmc.h>
+#include <mach/rockchip/rockchip.h>
 
 static unsigned long load_elf64_image_phdr(const void *elf)
 {
@@ -69,3 +72,22 @@ void rk3568_atf_load_bl31(void *fdt)
 {
 	rockchip_atf_load_bl31(RK3568, rk3568_bl31_bin, rk3568_op_tee_bin, fdt);
 }
+
+void __noreturn rk3568_barebox_entry(void *fdt)
+{
+	unsigned long membase, memsize;
+
+	membase = RK3568_DRAM_BOTTOM;
+	memsize = rk3568_ram0_size() - RK3568_DRAM_BOTTOM;
+
+	if (current_el() == 3) {
+		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
+		setup_c();
+
+		rk3568_lowlevel_init();
+		rk3568_atf_load_bl31(fdt);
+		/* not reached when CONFIG_ARCH_ROCKCHIP_ATF */
+	}
+
+	barebox_arm_entry(membase, memsize, fdt);
+}
diff --git a/include/mach/rockchip/atf.h b/include/mach/rockchip/atf.h
index e5d55af3d7..e1e68825d1 100644
--- a/include/mach/rockchip/atf.h
+++ b/include/mach/rockchip/atf.h
@@ -28,4 +28,6 @@ static inline void rk3568_atf_load_bl31(void *fdt) { }
 #endif
 #endif
 
+void __noreturn rk3568_barebox_entry(void *fdt);
+
 #endif /* __MACH_ATF_H */
-- 
2.30.2

[PATCH 4/5] ARM: Rockchip: rk3568: use rk3568_barebox_entry()

[Sascha Hauer]

There is a rk3568 specific entry function for barebox now, switch
the existing boards over to use it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/pine64-quartz64/lowlevel.c    | 31 ++---------------
 arch/arm/boards/radxa-rock3/lowlevel.c        | 32 +++---------------
 .../rockchip-rk3568-bpi-r2pro/lowlevel.c      | 32 ++----------------
 .../arm/boards/rockchip-rk3568-evb/lowlevel.c | 33 ++-----------------
 4 files changed, 13 insertions(+), 115 deletions(-)

diff --git a/arch/arm/boards/pine64-quartz64/lowlevel.c b/arch/arm/boards/pine64-quartz64/lowlevel.c
index 1e63c0e698..6e9448c517 100644
--- a/arch/arm/boards/pine64-quartz64/lowlevel.c
+++ b/arch/arm/boards/pine64-quartz64/lowlevel.c
@@ -1,41 +1,16 @@
 // SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/hardware.h>
 #include <mach/rockchip/atf.h>
 #include <debug_ll.h>
-#include <mach/rockchip/rockchip.h>
 
 extern char __dtb_rk3566_quartz64_a_start[];
 
-static noinline void start_quartz64(void)
-{
-	void *fdt = __dtb_rk3566_quartz64_a_start;
-
-	if (current_el() == 3) {
-		rk3568_lowlevel_init();
-		rk3568_atf_load_bl31(fdt);
-		/* not reached */
-	}
-
-	barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM,
-			  fdt);
-}
-
 ENTRY_FUNCTION(start_quartz64a, r0, r1, r2)
 {
-	/*
-	 * Image execution starts at 0x0, but this is used for ATF and
-	 * OP-TEE later, so move away from here.
-	 */
-	if (current_el() == 3)
-		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
-	else
-		relocate_to_current_adr();
-
-	setup_c();
+	putc_ll('>');
 
-	start_quartz64();
+	rk3568_barebox_entry(runtime_address(__dtb_rk3566_quartz64_a_start));
 }
diff --git a/arch/arm/boards/radxa-rock3/lowlevel.c b/arch/arm/boards/radxa-rock3/lowlevel.c
index a8226749d4..f7648cd1dc 100644
--- a/arch/arm/boards/radxa-rock3/lowlevel.c
+++ b/arch/arm/boards/radxa-rock3/lowlevel.c
@@ -1,19 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/hardware.h>
 #include <mach/rockchip/atf.h>
 #include <debug_ll.h>
-#include <mach/rockchip/rockchip.h>
 
 extern char __dtb_rk3568_rock_3a_start[];
 
-static noinline void rk3568_start(void)
+ENTRY_FUNCTION(start_rock3a, r0, r1, r2)
 {
-	void *fdt = __dtb_rk3568_rock_3a_start;
-
 	/*
 	 * Enable vccio4 1.8V and vccio6 1.8V
 	 * Needed for GMAC to work.
@@ -24,27 +20,7 @@ static noinline void rk3568_start(void)
 	 */
 	writel(RK_SETBITS(0x50), 0xfdc20140);
 
-	if (current_el() == 3) {
-		rk3568_lowlevel_init();
-		rk3568_atf_load_bl31(fdt);
-		/* not reached */
-	}
-
-	barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM, fdt);
-}
-
-ENTRY_FUNCTION(start_rock3a, r0, r1, r2)
-{
-	/*
-	 * Image execution starts at 0x0, but this is used for ATF and
-	 * OP-TEE later, so move away from here.
-	 */
-	if (current_el() == 3)
-		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
-	else
-		relocate_to_current_adr();
-
-	setup_c();
+	putc_ll('>');
 
-	rk3568_start();
+	rk3568_barebox_entry(runtime_address(__dtb_rk3568_rock_3a_start));
 }
diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c
index 23bacc91d9..76aac83c17 100644
--- a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c
+++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c
@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 #include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/hardware.h>
 #include <mach/rockchip/atf.h>
@@ -11,9 +9,9 @@
 
 extern char __dtb_rk3568_bpi_r2_pro_start[];
 
-static noinline void rk3568_start(void)
+ENTRY_FUNCTION(start_rk3568_bpi_r2pro, r0, r1, r2)
 {
-	void *fdt;
+	putc_ll('>');
 
 	/*
 	 * set iodomain vccio6 to 1.8V needed for GMAC1 to work.
@@ -28,29 +26,5 @@ static noinline void rk3568_start(void)
 	//clear bit 6 for 3v3 as it was set to 1v8
 	writel(RK_CLRBITS(BIT(6)), PMU_GRF_IO_VSEL1);
 
-	fdt = __dtb_rk3568_bpi_r2_pro_start;
-
-	if (current_el() == 3) {
-		rk3568_lowlevel_init();
-		rk3568_atf_load_bl31(fdt);
-		/* not reached */
-	}
-
-	barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM, fdt);
-}
-
-ENTRY_FUNCTION(start_rk3568_bpi_r2pro, r0, r1, r2)
-{
-	/*
-	 * Image execution starts at 0x0, but this is used for ATF and
-	 * OP-TEE later, so move away from here.
-	 */
-	if (current_el() == 3)
-		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
-	else
-		relocate_to_current_adr();
-
-	setup_c();
-
-	rk3568_start();
+	rk3568_barebox_entry(runtime_address(__dtb_rk3568_bpi_r2_pro_start));
 }
diff --git a/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c
index 8720e6d9ae..66af456648 100644
--- a/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c
+++ b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c
@@ -1,20 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 #include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/hardware.h>
 #include <mach/rockchip/atf.h>
 #include <debug_ll.h>
-#include <mach/rockchip/rockchip.h>
 
 extern char __dtb_rk3568_evb1_v10_start[];
 
-static noinline void rk3568_start(void)
+ENTRY_FUNCTION(start_rk3568_evb, r0, r1, r2)
 {
-	void *fdt;
-
 	/*
 	 * Enable vccio4 1.8V and vccio6 1.8V
 	 * Needed for GMAC to work.
@@ -25,29 +20,7 @@ static noinline void rk3568_start(void)
 	 */
 	writel(RK_SETBITS(0x50), 0xfdc20140);
 
-	fdt = __dtb_rk3568_evb1_v10_start;
-
-	if (current_el() == 3) {
-		rk3568_lowlevel_init();
-		rk3568_atf_load_bl31(fdt);
-		/* not reached */
-	}
-
-	barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM, fdt);
-}
-
-ENTRY_FUNCTION(start_rk3568_evb, r0, r1, r2)
-{
-	/*
-	 * Image execution starts at 0x0, but this is used for ATF and
-	 * OP-TEE later, so move away from here.
-	 */
-	if (current_el() == 3)
-		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
-	else
-		relocate_to_current_adr();
-
-	setup_c();
+	putc_ll('>');
 
-	rk3568_start();
+	rk3568_barebox_entry(runtime_address(__dtb_rk3568_evb1_v10_start));
 }
-- 
2.30.2

[PATCH 5/5] ARM: Rockchip: make bootsource logic generic to all SoCs

[Sascha Hauer]

From: Ahmad Fatoum <ahmad@a3f.at>

Decoding of the bootsource from the register value can be shared across
multiple Rockchip SoCs. Move the code to a common place to allow for
that.
At least with some TF-A versions the IRAM where the bootsource is stored
cannot not be accessed in normal mode, so read it out before we start
the TF-A. For this the scratch space is used.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-rockchip/Makefile  |  2 +-
 arch/arm/mach-rockchip/atf.c     |  3 ++
 arch/arm/mach-rockchip/bootrom.c | 51 ++++++++++++++++++++++++++++++++
 arch/arm/mach-rockchip/rk3568.c  | 29 ++----------------
 include/bootsource.h             |  1 +
 include/mach/rockchip/bootrom.h  | 32 ++++++++++++++++++++
 6 files changed, 90 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/bootrom.c
 create mode 100644 include/mach/rockchip/bootrom.h

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index f6c575854e..04d75ce287 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-obj-y += rockchip.o
+obj-y += rockchip.o bootrom.o
 pbl-$(CONFIG_ARCH_ROCKCHIP_ATF) += atf.o
 obj-$(CONFIG_ARCH_RK3188) += rk3188.o
 obj-$(CONFIG_ARCH_RK3288) += rk3288.o
diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
index a7d626226e..4c76273020 100644
--- a/arch/arm/mach-rockchip/atf.c
+++ b/arch/arm/mach-rockchip/atf.c
@@ -8,6 +8,8 @@
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/dmc.h>
 #include <mach/rockchip/rockchip.h>
+#include <mach/rockchip/bootrom.h>
+#include <mach/rockchip/rk3568-regs.h>
 
 static unsigned long load_elf64_image_phdr(const void *elf)
 {
@@ -85,6 +87,7 @@ void __noreturn rk3568_barebox_entry(void *fdt)
 		setup_c();
 
 		rk3568_lowlevel_init();
+		rockchip_store_bootrom_iram(membase, memsize, IOMEM(RK3568_IRAM_BASE));
 		rk3568_atf_load_bl31(fdt);
 		/* not reached when CONFIG_ARCH_ROCKCHIP_ATF */
 	}
diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
new file mode 100644
index 0000000000..cdd0536cda
--- /dev/null
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <mach/rockchip/bootrom.h>
+#include <io.h>
+#include <bootsource.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <errno.h>
+
+#define BROM_BOOTSOURCE_ID	0x10
+#define BROM_BOOTSOURCE_SLOT	0x14
+#define	BROM_BOOTSOURCE_SLOT_ACTIVE	GENMASK(12, 10)
+
+static const void __iomem *rk_iram;
+
+int rockchip_bootsource_get_active_slot(void)
+{
+	if (!rk_iram)
+		return -EINVAL;
+
+	return FIELD_GET(BROM_BOOTSOURCE_SLOT_ACTIVE,
+			 readl(IOMEM(rk_iram) + BROM_BOOTSOURCE_SLOT));
+}
+
+struct rk_bootsource {
+	enum bootsource src;
+	int instance;
+};
+
+static struct rk_bootsource bootdev_map[] = {
+	[0x1] = { .src = BOOTSOURCE_NAND, .instance = 0 },
+	[0x2] = { .src = BOOTSOURCE_MMC, .instance = 0 },
+	[0x3] = { .src = BOOTSOURCE_SPI_NOR, .instance = 0 },
+	[0x4] = { .src = BOOTSOURCE_SPI_NAND, .instance = 0 },
+	[0x5] = { .src = BOOTSOURCE_MMC, .instance = 1 },
+	[0xa] = { .src = BOOTSOURCE_USB, .instance = 0 },
+};
+
+void rockchip_parse_bootrom_iram(const void *iram)
+{
+	u32 v;
+
+	rk_iram = iram;
+
+	v = readl(iram + BROM_BOOTSOURCE_ID);
+
+	if (v >= ARRAY_SIZE(bootdev_map))
+		return;
+
+	bootsource_set(bootdev_map[v].src, bootdev_map[v].instance);
+}
diff --git a/arch/arm/mach-rockchip/rk3568.c b/arch/arm/mach-rockchip/rk3568.c
index 39bd4772a6..c0453ea0c4 100644
--- a/arch/arm/mach-rockchip/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568.c
@@ -2,6 +2,7 @@
 #include <common.h>
 #include <io.h>
 #include <bootsource.h>
+#include <mach/rockchip/bootrom.h>
 #include <mach/rockchip/rk3568-regs.h>
 #include <mach/rockchip/rockchip.h>
 
@@ -137,35 +138,9 @@ void rk3568_lowlevel_init(void)
 	qos_priority_init();
 }
 
-struct rk_bootsource {
-	enum bootsource src;
-	int instance;
-};
-
-static struct rk_bootsource bootdev_map[] = {
-	[0x1] = { .src = BOOTSOURCE_NAND, .instance = 0 },
-	[0x2] = { .src = BOOTSOURCE_MMC, .instance = 0 },
-	[0x3] = { .src = BOOTSOURCE_SPI_NOR, .instance = 0 },
-	[0x4] = { .src = BOOTSOURCE_SPI_NAND, .instance = 0 },
-	[0x5] = { .src = BOOTSOURCE_MMC, .instance = 1 },
-	[0xa] = { .src = BOOTSOURCE_USB, .instance = 0 },
-};
-
-static void rk3568_bootsource(void)
-{
-	u32 v;
-
-	v = readl(RK3568_IRAM_BASE + 0x10);
-
-	if (v >= ARRAY_SIZE(bootdev_map))
-		return;
-
-	bootsource_set(bootdev_map[v].src, bootdev_map[v].instance);
-}
-
 int rk3568_init(void)
 {
-	rk3568_bootsource();
+	rockchip_parse_bootrom_iram(rockchip_scratch_space());
 
 	return 0;
 }
diff --git a/include/bootsource.h b/include/bootsource.h
index 05935b64a7..f2ab3a2ad4 100644
--- a/include/bootsource.h
+++ b/include/bootsource.h
@@ -26,6 +26,7 @@ enum bootsource {
 #define BOOTSOURCE_INSTANCE_UNKNOWN	-1
 
 enum bootsource bootsource_get(void);
+enum bootsource bootsource_get_device(void);
 int bootsource_get_instance(void);
 void bootsource_set_alias_name(const char *name);
 char *bootsource_get_alias_name(void);
diff --git a/include/mach/rockchip/bootrom.h b/include/mach/rockchip/bootrom.h
new file mode 100644
index 0000000000..96eb147ae4
--- /dev/null
+++ b/include/mach/rockchip/bootrom.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MACH_ROCKCHIP_BOOTROM_H
+#define __MACH_ROCKCHIP_BOOTROM_H
+
+#include <linux/compiler.h>
+#include <linux/string.h>
+#include <asm/barebox-arm.h>
+
+struct rockchip_scratch_space {
+	u32 irom[16];
+};
+
+static inline void rockchip_store_bootrom_iram(ulong membase,
+                                               ulong memsize,
+                                               const void *iram)
+{
+	void *dst = (void *)__arm_mem_scratch(membase + memsize);
+	memcpy(dst, iram, sizeof(struct rockchip_scratch_space));
+}
+
+static inline const struct rockchip_scratch_space *rockchip_scratch_space(void)
+{
+	return arm_mem_scratch_get();
+}
+
+void rockchip_parse_bootrom_iram(const void *iram);
+
+int rockchip_bootsource_get_active_slot(void);
+
+
+#endif
-- 
2.30.2

Re: [PATCH 2/5] ARM: Rockchip: implement memory read out from controller

[Rouven Czerwinski]

Hi,

On Fri, 2023-03-24 at 15:03 +0100, Sascha Hauer wrote:
> From: Ahmad Fatoum <ahmad@a3f.at>
> 
> Add a driver to read out the amount of memory from the DDR controller.
> The decoding of the registers has been taken from U-Boot. Currently
> supported are the RK3399 and the RK3568, but decoding should work on
> other Rockchip SoCs as well.
> 
> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/mach-rockchip/Makefile     |   1 +
>  arch/arm/mach-rockchip/dmc.c        | 232 ++++++++++++++++++++++++++++
>  include/linux/sizes.h               |   3 +
>  include/mach/rockchip/dmc.h         |  86 +++++++++++
>  include/mach/rockchip/rk3399-regs.h |   1 +
>  include/mach/rockchip/rk3568-regs.h |   1 +
>  6 files changed, 324 insertions(+)
>  create mode 100644 arch/arm/mach-rockchip/dmc.c
>  create mode 100644 include/mach/rockchip/dmc.h
> 
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 2529af7c7e..f6c575854e 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -6,4 +6,5 @@ obj-$(CONFIG_ARCH_RK3188) += rk3188.o
>  obj-$(CONFIG_ARCH_RK3288) += rk3288.o
>  obj-pbl-$(CONFIG_ARCH_RK3568) += rk3568.o
>  obj-$(CONFIG_ARCH_ROCKCHIP_V8) += bootm.o
> +obj-pbl-$(CONFIG_ARCH_ROCKCHIP_V8) += dmc.o
>  obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
> diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
> new file mode 100644
> index 0000000000..3a0d835689
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/dmc.c
> @@ -0,0 +1,232 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + */
> +
> +#define pr_fmt(fmt) "rockchip-dmc: " fmt
> +
> +#include <common.h>
> +#include <init.h>
> +#include <asm/barebox-arm.h>
> +#include <asm/memory.h>
> +#include <pbl.h>
> +#include <io.h>
> +#include <regmap.h>
> +#include <mfd/syscon.h>
> +#include <mach/rockchip/dmc.h>
> +#include <mach/rockchip/rk3399-regs.h>
> +#include <mach/rockchip/rk3568-regs.h>
> +
> +#define RK3399_PMUGRF_OS_REG2          0x308
> +#define RK3399_PMUGRF_OS_REG3          0x30C
> +
> +#define RK3568_PMUGRF_OS_REG2           0x208
> +#define RK3568_PMUGRF_OS_REG3           0x20c
> +
> +struct rockchip_dmc_region {
> +       resource_size_t base, size;
> +};
> +
> +struct rockchip_dmc_drvdata {
> +       unsigned int os_reg2;
> +       unsigned int os_reg3;
> +       const struct rockchip_dmc_region *regions;
> +};
> +
> +static resource_size_t rockchip_sdram_size(u32 sys_reg2, u32 sys_reg3)
> +{
> +       u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
> +       resource_size_t chipsize_mb, size_mb = 0;
> +       u32 ch;
> +       u32 cs1_col;
> +       u32 bg = 0;
> +       u32 dbw, dram_type;
> +       u32 ch_num = 1 + FIELD_GET(SYS_REG_NUM_CH, sys_reg2);
> +       u32 version = FIELD_GET(SYS_REG_VERSION, sys_reg3);
> +
> +       pr_debug("%s(reg2=%x, reg3=%x)\n", __func__, sys_reg2, sys_reg3);
> +
> +       dram_type = FIELD_GET(SYS_REG_DDRTYPE, sys_reg2);
> +
> +       if (version >= 3)
> +               dram_type |= FIELD_GET(SYS_REG_EXTEND_DDRTYPE, sys_reg3) << 3;
> +
> +       for (ch = 0; ch < ch_num; ch++) {
> +               rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK);
> +               cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
> +               cs1_col = cs0_col;
> +
> +               bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
> +
> +               cs0_row = sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK;
> +               cs1_row = sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK;
> +
> +               if (version >= 2) {
> +                       cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
> +                                 SYS_REG_CS1_COL_MASK);
> +
> +                       cs0_row |= (sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
> +                                       SYS_REG_EXTEND_CS0_ROW_MASK) << 2;
> +
> +                       if (cs0_row == 7)
> +                               cs0_row = 12;
> +                       else
> +                               cs0_row += 13;
> +
> +                       cs1_row |= (sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
> +                                       SYS_REG_EXTEND_CS1_ROW_MASK) << 2;
> +
> +                       if (cs1_row == 7)
> +                               cs1_row = 12;
> +                       else
> +                               cs1_row += 13;
> +               } else {
> +                       cs0_row += 13;
> +                       cs1_row += 13;
> +               }
> +
> +               bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & SYS_REG_BW_MASK));
> +               row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK;
> +
> +               if (dram_type == DDR4) {
> +                       dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & SYS_REG_DBW_MASK;
> +                       bg = (dbw == 2) ? 2 : 1;
> +               }
> +
> +               chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
> +
> +               if (rank > 1)
> +                       chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
> +                                      (cs0_col - cs1_col));
> +               if (row_3_4)
> +                       chipsize_mb = chipsize_mb * 3 / 4;
> +
> +               size_mb += chipsize_mb;
> +
> +               if (rank > 1)
> +                       pr_debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d "
> +                                "cs1_row %d bw %d row_3_4 %d\n",
> +                                rank, cs0_col, cs1_col, bk, cs0_row,
> +                                cs1_row, bw, row_3_4);
> +               else
> +                       pr_debug("rank %d cs0_col %d bk %d cs0_row %d "
> +                                "bw %d row_3_4 %d\n",
> +                                rank, cs0_col, bk, cs0_row,
> +                                bw, row_3_4);
> +       }
> +
> +       return (resource_size_t)size_mb << 20;
> +}
> +
> +resource_size_t rk3399_ram0_size(void)
> +{
> +       void __iomem *pmugrf = IOMEM(RK3399_PMUGRF_BASE);
> +       u32 sys_reg2, sys_reg3;
> +       resource_size_t size;
> +
> +       sys_reg2 = readl(pmugrf + RK3399_PMUGRF_OS_REG2);
> +       sys_reg3 = readl(pmugrf + RK3399_PMUGRF_OS_REG3);
> +
> +       size = rockchip_sdram_size(sys_reg2, sys_reg3);
> +       size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
> +
> +       pr_debug("%s() = %llu\n", __func__, (u64)size);
> +
> +       return size;
> +}
> +
> +resource_size_t rk3568_ram0_size(void)
> +{
> +       void __iomem *pmugrf = IOMEM(RK3568_PMUGRF_BASE);
> +       u32 sys_reg2, sys_reg3;
> +       resource_size_t size;
> +
> +       sys_reg2 = readl(pmugrf + RK3568_PMUGRF_OS_REG2);
> +       sys_reg3 = readl(pmugrf + RK3568_PMUGRF_OS_REG3);
> +
> +       size = rockchip_sdram_size(sys_reg2, sys_reg3);
> +       size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
                                           this ^
Should be SZ_256M, The frist memory region for RK356x is from 0x0 to
0xf000_0000, not 0xf800_0000. Tested on Radxa CM3 RK3566.

> +
> +       pr_debug("%s() = %llu\n", __func__, (u64)size);
> +
> +       return size;
> +}
> +
> +static int rockchip_dmc_probe(struct device *dev)
> +{
> +       const struct rockchip_dmc_drvdata *drvdata;
> +       const struct rockchip_dmc_region *region;
> +       resource_size_t membase, memsize;
> +       struct regmap *regmap;
> +       u32 sys_reg2, sys_reg3;
> +
> +       regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
> +       if (IS_ERR(regmap))
> +               return PTR_ERR(regmap);
> +
> +       drvdata = device_get_match_data(dev);
> +       if (!drvdata)
> +               return -ENOENT;
> +
> +       regmap_read(regmap, drvdata->os_reg2, &sys_reg2);
> +       regmap_read(regmap, drvdata->os_reg3, &sys_reg3);
> +
> +       memsize = rockchip_sdram_size(sys_reg2, sys_reg3);
> +
> +       dev_info(dev, "Detected memory size: %pa\n", &memsize);
> +
> +       region = drvdata->regions;
> +
> +       if (memsize >= region[0].size) {
> +               if (region[1].size)
> +                       arm_add_mem_device("ram1", region[1].base,
> +                                          memsize - region[0].size);
> +               memsize = region[0].size;
> +       }
> +
> +       /* lowest 10M are shaved off for secure world firmware */
> +       membase = 0xa00000;
> +
> +       return arm_add_mem_device("ram0", membase, memsize - membase);
> +}
> +
> +static const struct rockchip_dmc_region rk3399_regions[] = {
> +       {
> +               .base = 0x0,
> +               .size = SZ_4G - SZ_128M,
> +       }, {
> +               .base = SZ_4G,
> +               .size = SZ_32G,
> +       }
> +};
> +
> +static const struct rockchip_dmc_drvdata rk3399_drvdata = {
> +       .os_reg2 = RK3399_PMUGRF_OS_REG2,
> +       .os_reg3 = RK3399_PMUGRF_OS_REG3,
> +       .regions = rk3399_regions,
> +};
> +
> +static const struct rockchip_dmc_drvdata rk3568_drvdata = {
> +       .os_reg2 = RK3568_PMUGRF_OS_REG2,
> +       .os_reg3 = RK3568_PMUGRF_OS_REG3,
> +       .regions = rk3399_regions,
> +};
> +
> +static struct of_device_id rockchip_dmc_dt_ids[] = {
> +       {
> +               .compatible = "rockchip,rk3399-dmc",
> +               .data = &rk3399_drvdata,
> +       },
> +       {
> +               .compatible = "rockchip,rk3568-dmc",
> +               .data = &rk3568_drvdata,
> +       },
> +       { /* sentinel */ }
> +};
> +
> +static struct driver rockchip_dmc_driver = {
> +       .name   = "rockchip-dmc",
> +       .probe  = rockchip_dmc_probe,
> +       .of_compatible = rockchip_dmc_dt_ids,
> +};
> +mem_platform_driver(rockchip_dmc_driver);
> diff --git a/include/linux/sizes.h b/include/linux/sizes.h
> index fbde0bc7e8..1d222daeab 100644
> --- a/include/linux/sizes.h
> +++ b/include/linux/sizes.h
> @@ -47,5 +47,8 @@
>  #define SZ_2G                          0x80000000
>  
>  #define SZ_4G                          _AC(0x100000000, ULL)
> +#define SZ_8G                          _AC(0x200000000, ULL)
> +#define SZ_16G                         _AC(0x400000000, ULL)
> +#define SZ_32G                         _AC(0x800000000, ULL)
>  
>  #endif /* __LINUX_SIZES_H__ */
> diff --git a/include/mach/rockchip/dmc.h b/include/mach/rockchip/dmc.h
> new file mode 100644
> index 0000000000..ff197d50a0
> --- /dev/null
> +++ b/include/mach/rockchip/dmc.h
> @@ -0,0 +1,86 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + */
> +
> +#ifndef _MACH_ROCKCHIP_DMC_H
> +#define _MACH_ROCKCHIP_DMC_H
> +
> +#include <linux/compiler.h>
> +#include <linux/types.h>
> +#include <linux/bitfield.h>
> +
> +enum {
> +       DDR4 = 0,
> +       DDR3 = 0x3,
> +       LPDDR2 = 0x5,
> +       LPDDR3 = 0x6,
> +       LPDDR4 = 0x7,
> +       UNUSED = 0xFF
> +};
> +
> +/*
> + * sys_reg2 bitfield struct
> + * [31]                row_3_4_ch1
> + * [30]                row_3_4_ch0
> + * [29:28]     chinfo
> + * [27]                rank_ch1
> + * [26:25]     col_ch1
> + * [24]                bk_ch1
> + * [23:22]     low bits of cs0_row_ch1
> + * [21:20]     low bits of cs1_row_ch1
> + * [19:18]     bw_ch1
> + * [17:16]     dbw_ch1;
> + * [15:13]     ddrtype
> + * [12]                channelnum
> + * [11]                rank_ch0
> + * [10:9]      col_ch0,
> + * [8]         bk_ch0
> + * [7:6]       low bits of cs0_row_ch0
> + * [5:4]       low bits of cs1_row_ch0
> + * [3:2]       bw_ch0
> + * [1:0]       dbw_ch0
> + */
> +
> +#define SYS_REG_DDRTYPE                        GENMASK(15, 13)
> +#define SYS_REG_NUM_CH                 BIT(12)
> +#define SYS_REG_ROW_3_4_SHIFT(ch)      (30 + (ch))
> +#define SYS_REG_ROW_3_4_MASK           1
> +#define SYS_REG_CHINFO_SHIFT(ch)       (28 + (ch))
> +#define SYS_REG_RANK_SHIFT(ch)         (11 + (ch) * 16)
> +#define SYS_REG_RANK_MASK              1
> +#define SYS_REG_COL_SHIFT(ch)          (9 + (ch) * 16)
> +#define SYS_REG_COL_MASK               3
> +#define SYS_REG_BK_SHIFT(ch)           (8 + (ch) * 16)
> +#define SYS_REG_BK_MASK                        1
> +#define SYS_REG_CS0_ROW_SHIFT(ch)      (6 + (ch) * 16)
> +#define SYS_REG_CS0_ROW_MASK           3
> +#define SYS_REG_CS1_ROW_SHIFT(ch)      (4 + (ch) * 16)
> +#define SYS_REG_CS1_ROW_MASK           3
> +#define SYS_REG_BW_SHIFT(ch)           (2 + (ch) * 16)
> +#define SYS_REG_BW_MASK                        3
> +#define SYS_REG_DBW_SHIFT(ch)          ((ch) * 16)
> +#define SYS_REG_DBW_MASK               3
> +
> +/*
> + * sys_reg3 bitfield struct
> + * [7]         high bit of cs0_row_ch1
> + * [6]         high bit of cs1_row_ch1
> + * [5]         high bit of cs0_row_ch0
> + * [4]         high bit of cs1_row_ch0
> + * [3:2]       cs1_col_ch1
> + * [1:0]       cs1_col_ch0
> + */
> +#define SYS_REG_VERSION                                GENMASK(31, 28)
> +#define SYS_REG_EXTEND_DDRTYPE                 GENMASK(13, 12)
> +#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch)       (5 + (ch) * 2)
> +#define SYS_REG_EXTEND_CS0_ROW_MASK            1
> +#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch)       (4 + (ch) * 2)
> +#define SYS_REG_EXTEND_CS1_ROW_MASK            1
> +#define SYS_REG_CS1_COL_SHIFT(ch)              (0 + (ch) * 2)
> +#define SYS_REG_CS1_COL_MASK                   3
> +
> +resource_size_t rk3399_ram0_size(void);
> +resource_size_t rk3568_ram0_size(void);
> +
> +#endif
> diff --git a/include/mach/rockchip/rk3399-regs.h b/include/mach/rockchip/rk3399-regs.h
> index 57033b6510..6db082da9b 100644
> --- a/include/mach/rockchip/rk3399-regs.h
> +++ b/include/mach/rockchip/rk3399-regs.h
> @@ -10,6 +10,7 @@
>  #define RK3399_UART3_BASE      0xff1b0000
>  #define RK3399_UART4_BASE      0xff370000
>  
> +#define RK3399_PMUGRF_BASE     0xff320000
>  #define RK3399_IRAM_BASE       0xff8c0000
>  #define RK3399_STIMER_BASE     0xff8680a0
>  
> diff --git a/include/mach/rockchip/rk3568-regs.h b/include/mach/rockchip/rk3568-regs.h
> index edd5ee268d..55d28790dd 100644
> --- a/include/mach/rockchip/rk3568-regs.h
> +++ b/include/mach/rockchip/rk3568-regs.h
> @@ -16,5 +16,6 @@
>  #define RK3568_UART9_BASE      0xfe6d0000
>  
>  #define RK3568_IRAM_BASE       0xfdcc0000
> +#define RK3568_PMUGRF_BASE     0xfdc20000
>  
>  #endif /* __MACH_RK3568_REGS_H */

Re: [PATCH 3/5] ARM: Rockchip: Add rk3568 specific barebox entry function

[Rouven Czerwinski]

Hi,

On Fri, 2023-03-24 at 15:03 +0100, Sascha Hauer wrote:
> Add a rk3568 specific barebox entry function to simplify board
> code.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/mach-rockchip/atf.c | 22 ++++++++++++++++++++++
>  include/mach/rockchip/atf.h  |  2 ++
>  2 files changed, 24 insertions(+)
> 
> diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-
> rockchip/atf.c
> index 93025faf68..a7d626226e 100644
> --- a/arch/arm/mach-rockchip/atf.c
> +++ b/arch/arm/mach-rockchip/atf.c
> @@ -5,6 +5,9 @@
>  #include <mach/rockchip/atf.h>
>  #include <elf.h>
>  #include <asm/atf_common.h>
> +#include <asm/barebox-arm.h>
> +#include <mach/rockchip/dmc.h>
> +#include <mach/rockchip/rockchip.h>
>  
>  static unsigned long load_elf64_image_phdr(const void *elf)
>  {
> @@ -69,3 +72,22 @@ void rk3568_atf_load_bl31(void *fdt)
>  {
>         rockchip_atf_load_bl31(RK3568, rk3568_bl31_bin,
> rk3568_op_tee_bin, fdt);
>  }
> +
> +void __noreturn rk3568_barebox_entry(void *fdt)
> +{
> +       unsigned long membase, memsize;
> +
> +       membase = RK3568_DRAM_BOTTOM;
> +       memsize = rk3568_ram0_size() - RK3568_DRAM_BOTTOM;
> +
> +       if (current_el() == 3) {
> +               relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
> +               setup_c();
> +
> +               rk3568_lowlevel_init();
> +               rk3568_atf_load_bl31(fdt);

At least on my board I have to replace the fdt with a NULL pointer to
get the downstream TF-A to work. What is the intention for barebox
here? Do we want to support both upstream and downstream? Or do we need
an fdt size check in the PBL to decide whether we want to pass the
pointer?

> +               /* not reached when CONFIG_ARCH_ROCKCHIP_ATF */
> +       }
> +
> +       barebox_arm_entry(membase, memsize, fdt);
> +}
> diff --git a/include/mach/rockchip/atf.h
> b/include/mach/rockchip/atf.h
> index e5d55af3d7..e1e68825d1 100644
> --- a/include/mach/rockchip/atf.h
> +++ b/include/mach/rockchip/atf.h
> @@ -28,4 +28,6 @@ static inline void rk3568_atf_load_bl31(void *fdt)
> { }
>  #endif
>  #endif
>  
> +void __noreturn rk3568_barebox_entry(void *fdt);
> +
>  #endif /* __MACH_ATF_H */

Best regards,
Rouven Czerwinski

Re: [PATCH 2/5] ARM: Rockchip: implement memory read out from controller

[Sascha Hauer]

On Sun, Mar 26, 2023 at 10:34:55AM +0200, Rouven Czerwinski wrote:
> Hi,
> 
> On Fri, 2023-03-24 at 15:03 +0100, Sascha Hauer wrote:
> > From: Ahmad Fatoum <ahmad@a3f.at>
> > 
> > Add a driver to read out the amount of memory from the DDR controller.
> > The decoding of the registers has been taken from U-Boot. Currently
> > supported are the RK3399 and the RK3568, but decoding should work on
> > other Rockchip SoCs as well.
> > 
> > Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  arch/arm/mach-rockchip/Makefile     |   1 +
> >  arch/arm/mach-rockchip/dmc.c        | 232 ++++++++++++++++++++++++++++
> >  include/linux/sizes.h               |   3 +
> >  include/mach/rockchip/dmc.h         |  86 +++++++++++
> >  include/mach/rockchip/rk3399-regs.h |   1 +
> >  include/mach/rockchip/rk3568-regs.h |   1 +
> >  6 files changed, 324 insertions(+)
> >  create mode 100644 arch/arm/mach-rockchip/dmc.c
> >  create mode 100644 include/mach/rockchip/dmc.h
> > 

[...]

> > +
> > +resource_size_t rk3568_ram0_size(void)
> > +{
> > +       void __iomem *pmugrf = IOMEM(RK3568_PMUGRF_BASE);
> > +       u32 sys_reg2, sys_reg3;
> > +       resource_size_t size;
> > +
> > +       sys_reg2 = readl(pmugrf + RK3568_PMUGRF_OS_REG2);
> > +       sys_reg3 = readl(pmugrf + RK3568_PMUGRF_OS_REG3);
> > +
> > +       size = rockchip_sdram_size(sys_reg2, sys_reg3);
> > +       size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
>                                            this ^
> Should be SZ_256M, The frist memory region for RK356x is from 0x0 to
> 0xf000_0000, not 0xf800_0000. Tested on Radxa CM3 RK3566.

True. Maybe we should better write 0xf0000000, because that's the
address value where the DDR stops.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 3/5] ARM: Rockchip: Add rk3568 specific barebox entry function

[Sascha Hauer]

On Sun, Mar 26, 2023 at 10:36:19AM +0200, Rouven Czerwinski wrote:
> Hi,
> 
> On Fri, 2023-03-24 at 15:03 +0100, Sascha Hauer wrote:
> > Add a rk3568 specific barebox entry function to simplify board
> > code.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  arch/arm/mach-rockchip/atf.c | 22 ++++++++++++++++++++++
> >  include/mach/rockchip/atf.h  |  2 ++
> >  2 files changed, 24 insertions(+)
> > 
> > diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-
> > rockchip/atf.c
> > index 93025faf68..a7d626226e 100644
> > --- a/arch/arm/mach-rockchip/atf.c
> > +++ b/arch/arm/mach-rockchip/atf.c
> > @@ -5,6 +5,9 @@
> >  #include <mach/rockchip/atf.h>
> >  #include <elf.h>
> >  #include <asm/atf_common.h>
> > +#include <asm/barebox-arm.h>
> > +#include <mach/rockchip/dmc.h>
> > +#include <mach/rockchip/rockchip.h>
> >  
> >  static unsigned long load_elf64_image_phdr(const void *elf)
> >  {
> > @@ -69,3 +72,22 @@ void rk3568_atf_load_bl31(void *fdt)
> >  {
> >         rockchip_atf_load_bl31(RK3568, rk3568_bl31_bin,
> > rk3568_op_tee_bin, fdt);
> >  }
> > +
> > +void __noreturn rk3568_barebox_entry(void *fdt)
> > +{
> > +       unsigned long membase, memsize;
> > +
> > +       membase = RK3568_DRAM_BOTTOM;
> > +       memsize = rk3568_ram0_size() - RK3568_DRAM_BOTTOM;
> > +
> > +       if (current_el() == 3) {
> > +               relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
> > +               setup_c();
> > +
> > +               rk3568_lowlevel_init();
> > +               rk3568_atf_load_bl31(fdt);
> 
> At least on my board I have to replace the fdt with a NULL pointer to
> get the downstream TF-A to work. What is the intention for barebox
> here? Do we want to support both upstream and downstream? Or do we need
> an fdt size check in the PBL to decide whether we want to pass the
> pointer?

There are two problems here. First one is that the downstream TF-A
cannot handle device trees that exceed a certain size. That is triggered
with enabling CONFIG_OF_OVERLAY_LIVE.

The second one comes with this patch. Without the common barebox entry
we had:

	relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
	fdt = __dtb_rk3566_quartz64_a_start;

That means the device tree is taken from the place we have just
relocated to. With the common barebox entry the above is done the other
way round which means the device tree is used from the binary we just
relocated away from. It is overwritten by the TF-A.

There are some possible solutions to this, I haven't sorted out yet what
might be best.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |