[PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller

mail archive of the barebox mailing list
 help / color / mirror / Atom feed

* [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller
@ 2023-03-28  7:40 Sascha Hauer
  2023-03-28  7:40 ` [PATCH v2 1/6] ARM: dts: rk356x: Add DMC controller node Sascha Hauer
                   ` (6 more replies)
  0 siblings, 7 replies; 14+ messages in thread
From: Sascha Hauer @ 2023-03-28  7:40 UTC (permalink / raw)
  To: Barebox List

This series adds support for reading the amount of memory from
the DDR controller. This helps on boards which come with
different amounts of memory like the Radxa Rock3a.

This series also fixes issues with an upstream TF-A firmware. With this
the IRAM where the bootsource is stored is no longer accessible in
normal mode. We have to read its contents before starting the TF-A.
For this it became necessary to add a common barebox entry function
for rk3568, to get a common place to read the IRAM contents.

Sascha

Changes since v1:
- Call relocate_to_adr_full() from board code to make sure the
  fdt from the relocated binary is used, not from the original
  binary
- Add patch to pass a NULL fdt to TF-A

Ahmad Fatoum (2):
  ARM: Rockchip: implement memory read out from controller
  ARM: Rockchip: make bootsource logic generic to all SoCs

Sascha Hauer (4):
  ARM: dts: rk356x: Add DMC controller node
  ARM: Rockchip: Add rk3568 specific barebox entry function
  ARM: Rockchip: rk3568: use rk3568_barebox_entry()
  ARM: Rockchip: Do not pass device tree to TF-A

 arch/arm/boards/pine64-quartz64/lowlevel.c    |  30 +--
 arch/arm/boards/radxa-rock3/lowlevel.c        |  31 +--
 .../rockchip-rk3568-bpi-r2pro/lowlevel.c      |  31 +--
 .../arm/boards/rockchip-rk3568-evb/lowlevel.c |  32 +--
 arch/arm/dts/rk356x.dtsi                      |   5 +
 arch/arm/mach-rockchip/Makefile               |   3 +-
 arch/arm/mach-rockchip/atf.c                  |  34 +++
 arch/arm/mach-rockchip/bootrom.c              |  51 ++++
 arch/arm/mach-rockchip/dmc.c                  | 232 ++++++++++++++++++
 arch/arm/mach-rockchip/rk3568.c               |  29 +--
 include/bootsource.h                          |   1 +
 include/linux/sizes.h                         |   3 +
 include/mach/rockchip/atf.h                   |   2 +
 include/mach/rockchip/bootrom.h               |  32 +++
 include/mach/rockchip/dmc.h                   |  86 +++++++
 include/mach/rockchip/rk3399-regs.h           |   1 +
 include/mach/rockchip/rk3568-regs.h           |   1 +
 17 files changed, 469 insertions(+), 135 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/bootrom.c
 create mode 100644 arch/arm/mach-rockchip/dmc.c
 create mode 100644 include/mach/rockchip/bootrom.h
 create mode 100644 include/mach/rockchip/dmc.h

-- 
2.39.2




^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 1/6] ARM: dts: rk356x: Add DMC controller node
  2023-03-28  7:40 [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Sascha Hauer
@ 2023-03-28  7:40 ` Sascha Hauer
  2023-03-28  7:40 ` [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller Sascha Hauer
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2023-03-28  7:40 UTC (permalink / raw)
  To: Barebox List

There's currently no DMC controller node in the upstream dtsi file.
Add one until it's there.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/rk356x.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi
index 6a9cd14d2d..4de2404b50 100644
--- a/arch/arm/dts/rk356x.dtsi
+++ b/arch/arm/dts/rk356x.dtsi
@@ -6,4 +6,9 @@
 		barebox,bootsource-mmc1 = &sdmmc0;
 		barebox,bootsource-mmc2 = &sdmmc1;
 	};
+
+	dmc: memory-controller {
+		compatible = "rockchip,rk3568-dmc";
+		rockchip,pmu = <&pmugrf>;
+	};
 };
-- 
2.39.2




^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller
  2023-03-28  7:40 [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Sascha Hauer
  2023-03-28  7:40 ` [PATCH v2 1/6] ARM: dts: rk356x: Add DMC controller node Sascha Hauer
@ 2023-03-28  7:40 ` Sascha Hauer
  2023-03-28  8:18   ` Sascha Hauer
  2023-04-03 19:43   ` Sascha Hauer
  2023-03-28  7:40 ` [PATCH v2 3/6] ARM: Rockchip: Add rk3568 specific barebox entry function Sascha Hauer
                   ` (4 subsequent siblings)
  6 siblings, 2 replies; 14+ messages in thread
From: Sascha Hauer @ 2023-03-28  7:40 UTC (permalink / raw)
  To: Barebox List; +Cc: Ahmad Fatoum

From: Ahmad Fatoum <ahmad@a3f.at>

Add a driver to read out the amount of memory from the DDR controller.
The decoding of the registers has been taken from U-Boot. Currently
supported are the RK3399 and the RK3568, but decoding should work on
other Rockchip SoCs as well.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-rockchip/Makefile     |   1 +
 arch/arm/mach-rockchip/dmc.c        | 232 ++++++++++++++++++++++++++++
 include/linux/sizes.h               |   3 +
 include/mach/rockchip/dmc.h         |  86 +++++++++++
 include/mach/rockchip/rk3399-regs.h |   1 +
 include/mach/rockchip/rk3568-regs.h |   1 +
 6 files changed, 324 insertions(+)
 create mode 100644 arch/arm/mach-rockchip/dmc.c
 create mode 100644 include/mach/rockchip/dmc.h

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 2529af7c7e..f6c575854e 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_ARCH_RK3188) += rk3188.o
 obj-$(CONFIG_ARCH_RK3288) += rk3288.o
 obj-pbl-$(CONFIG_ARCH_RK3568) += rk3568.o
 obj-$(CONFIG_ARCH_ROCKCHIP_V8) += bootm.o
+obj-pbl-$(CONFIG_ARCH_ROCKCHIP_V8) += dmc.o
 obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
new file mode 100644
index 0000000000..97968b0544
--- /dev/null
+++ b/arch/arm/mach-rockchip/dmc.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#define pr_fmt(fmt) "rockchip-dmc: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <asm/barebox-arm.h>
+#include <asm/memory.h>
+#include <pbl.h>
+#include <io.h>
+#include <regmap.h>
+#include <mfd/syscon.h>
+#include <mach/rockchip/dmc.h>
+#include <mach/rockchip/rk3399-regs.h>
+#include <mach/rockchip/rk3568-regs.h>
+
+#define RK3399_PMUGRF_OS_REG2		0x308
+#define RK3399_PMUGRF_OS_REG3		0x30C
+
+#define RK3568_PMUGRF_OS_REG2           0x208
+#define RK3568_PMUGRF_OS_REG3           0x20c
+
+struct rockchip_dmc_region {
+	resource_size_t base, size;
+};
+
+struct rockchip_dmc_drvdata {
+	unsigned int os_reg2;
+	unsigned int os_reg3;
+	const struct rockchip_dmc_region *regions;
+};
+
+static resource_size_t rockchip_sdram_size(u32 sys_reg2, u32 sys_reg3)
+{
+	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
+	resource_size_t chipsize_mb, size_mb = 0;
+	u32 ch;
+	u32 cs1_col;
+	u32 bg = 0;
+	u32 dbw, dram_type;
+	u32 ch_num = 1 + FIELD_GET(SYS_REG_NUM_CH, sys_reg2);
+	u32 version = FIELD_GET(SYS_REG_VERSION, sys_reg3);
+
+	pr_debug("%s(reg2=%x, reg3=%x)\n", __func__, sys_reg2, sys_reg3);
+
+	dram_type = FIELD_GET(SYS_REG_DDRTYPE, sys_reg2);
+
+	if (version >= 3)
+		dram_type |= FIELD_GET(SYS_REG_EXTEND_DDRTYPE, sys_reg3) << 3;
+
+	for (ch = 0; ch < ch_num; ch++) {
+		rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK);
+		cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
+		cs1_col = cs0_col;
+
+		bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+
+		cs0_row = sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK;
+		cs1_row = sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK;
+
+		if (version >= 2) {
+			cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
+				  SYS_REG_CS1_COL_MASK);
+
+			cs0_row |= (sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
+					SYS_REG_EXTEND_CS0_ROW_MASK) << 2;
+
+			if (cs0_row == 7)
+				cs0_row = 12;
+			else
+				cs0_row += 13;
+
+			cs1_row |= (sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
+					SYS_REG_EXTEND_CS1_ROW_MASK) << 2;
+
+			if (cs1_row == 7)
+				cs1_row = 12;
+			else
+				cs1_row += 13;
+		} else {
+			cs0_row += 13;
+			cs1_row += 13;
+		}
+
+		bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & SYS_REG_BW_MASK));
+		row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK;
+
+		if (dram_type == DDR4) {
+			dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & SYS_REG_DBW_MASK;
+			bg = (dbw == 2) ? 2 : 1;
+		}
+
+		chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
+
+		if (rank > 1)
+			chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
+				       (cs0_col - cs1_col));
+		if (row_3_4)
+			chipsize_mb = chipsize_mb * 3 / 4;
+
+		size_mb += chipsize_mb;
+
+		if (rank > 1)
+			pr_debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d "
+				 "cs1_row %d bw %d row_3_4 %d\n",
+				 rank, cs0_col, cs1_col, bk, cs0_row,
+				 cs1_row, bw, row_3_4);
+		else
+			pr_debug("rank %d cs0_col %d bk %d cs0_row %d "
+				 "bw %d row_3_4 %d\n",
+				 rank, cs0_col, bk, cs0_row,
+				 bw, row_3_4);
+	}
+
+	return (resource_size_t)size_mb << 20;
+}
+
+resource_size_t rk3399_ram0_size(void)
+{
+	void __iomem *pmugrf = IOMEM(RK3399_PMUGRF_BASE);
+	u32 sys_reg2, sys_reg3;
+	resource_size_t size;
+
+	sys_reg2 = readl(pmugrf + RK3399_PMUGRF_OS_REG2);
+	sys_reg3 = readl(pmugrf + RK3399_PMUGRF_OS_REG3);
+
+	size = rockchip_sdram_size(sys_reg2, sys_reg3);
+	size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
+
+	pr_debug("%s() = %llu\n", __func__, (u64)size);
+
+	return size;
+}
+
+resource_size_t rk3568_ram0_size(void)
+{
+	void __iomem *pmugrf = IOMEM(RK3568_PMUGRF_BASE);
+	u32 sys_reg2, sys_reg3;
+	resource_size_t size;
+
+	sys_reg2 = readl(pmugrf + RK3568_PMUGRF_OS_REG2);
+	sys_reg3 = readl(pmugrf + RK3568_PMUGRF_OS_REG3);
+
+	size = rockchip_sdram_size(sys_reg2, sys_reg3);
+	size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
+
+	pr_debug("%s() = %llu\n", __func__, (u64)size);
+
+	return size;
+}
+
+static int rockchip_dmc_probe(struct device *dev)
+{
+	const struct rockchip_dmc_drvdata *drvdata;
+	const struct rockchip_dmc_region *region;
+	resource_size_t membase, memsize;
+	struct regmap *regmap;
+	u32 sys_reg2, sys_reg3;
+
+	regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	drvdata = device_get_match_data(dev);
+	if (!drvdata)
+		return -ENOENT;
+
+	regmap_read(regmap, drvdata->os_reg2, &sys_reg2);
+	regmap_read(regmap, drvdata->os_reg3, &sys_reg3);
+
+	memsize = rockchip_sdram_size(sys_reg2, sys_reg3);
+
+	dev_info(dev, "Detected memory size: %pa\n", &memsize);
+
+	region = drvdata->regions;
+
+	if (memsize >= region[0].size) {
+		if (region[1].size)
+			arm_add_mem_device("ram1", region[1].base,
+					   memsize - region[0].size);
+		memsize = region[0].size;
+	}
+
+	/* lowest 10M are shaved off for secure world firmware */
+	membase = 0xa00000;
+
+	return arm_add_mem_device("ram0", membase, memsize - membase);
+}
+
+static const struct rockchip_dmc_region rk3399_regions[] = {
+	{
+		.base = 0x0,
+		.size = 0xf0000000,
+	}, {
+		.base = SZ_4G,
+		.size = SZ_32G,
+	}
+};
+
+static const struct rockchip_dmc_drvdata rk3399_drvdata = {
+	.os_reg2 = RK3399_PMUGRF_OS_REG2,
+	.os_reg3 = RK3399_PMUGRF_OS_REG3,
+	.regions = rk3399_regions,
+};
+
+static const struct rockchip_dmc_drvdata rk3568_drvdata = {
+	.os_reg2 = RK3568_PMUGRF_OS_REG2,
+	.os_reg3 = RK3568_PMUGRF_OS_REG3,
+	.regions = rk3399_regions,
+};
+
+static struct of_device_id rockchip_dmc_dt_ids[] = {
+	{
+		.compatible = "rockchip,rk3399-dmc",
+		.data = &rk3399_drvdata,
+	},
+	{
+		.compatible = "rockchip,rk3568-dmc",
+		.data = &rk3568_drvdata,
+	},
+	{ /* sentinel */ }
+};
+
+static struct driver rockchip_dmc_driver = {
+	.name   = "rockchip-dmc",
+	.probe  = rockchip_dmc_probe,
+	.of_compatible = rockchip_dmc_dt_ids,
+};
+mem_platform_driver(rockchip_dmc_driver);
diff --git a/include/linux/sizes.h b/include/linux/sizes.h
index fbde0bc7e8..1d222daeab 100644
--- a/include/linux/sizes.h
+++ b/include/linux/sizes.h
@@ -47,5 +47,8 @@
 #define SZ_2G				0x80000000
 
 #define SZ_4G				_AC(0x100000000, ULL)
+#define SZ_8G				_AC(0x200000000, ULL)
+#define SZ_16G				_AC(0x400000000, ULL)
+#define SZ_32G				_AC(0x800000000, ULL)
 
 #endif /* __LINUX_SIZES_H__ */
diff --git a/include/mach/rockchip/dmc.h b/include/mach/rockchip/dmc.h
new file mode 100644
index 0000000000..ff197d50a0
--- /dev/null
+++ b/include/mach/rockchip/dmc.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _MACH_ROCKCHIP_DMC_H
+#define _MACH_ROCKCHIP_DMC_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/bitfield.h>
+
+enum {
+	DDR4 = 0,
+	DDR3 = 0x3,
+	LPDDR2 = 0x5,
+	LPDDR3 = 0x6,
+	LPDDR4 = 0x7,
+	UNUSED = 0xFF
+};
+
+/*
+ * sys_reg2 bitfield struct
+ * [31]		row_3_4_ch1
+ * [30]		row_3_4_ch0
+ * [29:28]	chinfo
+ * [27]		rank_ch1
+ * [26:25]	col_ch1
+ * [24]		bk_ch1
+ * [23:22]	low bits of cs0_row_ch1
+ * [21:20]	low bits of cs1_row_ch1
+ * [19:18]	bw_ch1
+ * [17:16]	dbw_ch1;
+ * [15:13]	ddrtype
+ * [12]		channelnum
+ * [11]		rank_ch0
+ * [10:9]	col_ch0,
+ * [8]		bk_ch0
+ * [7:6]	low bits of cs0_row_ch0
+ * [5:4]	low bits of cs1_row_ch0
+ * [3:2]	bw_ch0
+ * [1:0]	dbw_ch0
+ */
+
+#define SYS_REG_DDRTYPE			GENMASK(15, 13)
+#define SYS_REG_NUM_CH			BIT(12)
+#define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
+#define SYS_REG_ROW_3_4_MASK		1
+#define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
+#define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
+#define SYS_REG_RANK_MASK		1
+#define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
+#define SYS_REG_COL_MASK		3
+#define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
+#define SYS_REG_BK_MASK			1
+#define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
+#define SYS_REG_CS0_ROW_MASK		3
+#define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
+#define SYS_REG_CS1_ROW_MASK		3
+#define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
+#define SYS_REG_BW_MASK			3
+#define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
+#define SYS_REG_DBW_MASK		3
+
+/*
+ * sys_reg3 bitfield struct
+ * [7]		high bit of cs0_row_ch1
+ * [6]		high bit of cs1_row_ch1
+ * [5]		high bit of cs0_row_ch0
+ * [4]		high bit of cs1_row_ch0
+ * [3:2]	cs1_col_ch1
+ * [1:0]	cs1_col_ch0
+ */
+#define SYS_REG_VERSION				GENMASK(31, 28)
+#define SYS_REG_EXTEND_DDRTYPE			GENMASK(13, 12)
+#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch)	(5 + (ch) * 2)
+#define SYS_REG_EXTEND_CS0_ROW_MASK		1
+#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch)	(4 + (ch) * 2)
+#define SYS_REG_EXTEND_CS1_ROW_MASK		1
+#define SYS_REG_CS1_COL_SHIFT(ch)		(0 + (ch) * 2)
+#define SYS_REG_CS1_COL_MASK			3
+
+resource_size_t rk3399_ram0_size(void);
+resource_size_t rk3568_ram0_size(void);
+
+#endif
diff --git a/include/mach/rockchip/rk3399-regs.h b/include/mach/rockchip/rk3399-regs.h
index 57033b6510..6db082da9b 100644
--- a/include/mach/rockchip/rk3399-regs.h
+++ b/include/mach/rockchip/rk3399-regs.h
@@ -10,6 +10,7 @@
 #define RK3399_UART3_BASE	0xff1b0000
 #define RK3399_UART4_BASE	0xff370000
 
+#define RK3399_PMUGRF_BASE	0xff320000
 #define RK3399_IRAM_BASE	0xff8c0000
 #define RK3399_STIMER_BASE	0xff8680a0
 
diff --git a/include/mach/rockchip/rk3568-regs.h b/include/mach/rockchip/rk3568-regs.h
index edd5ee268d..55d28790dd 100644
--- a/include/mach/rockchip/rk3568-regs.h
+++ b/include/mach/rockchip/rk3568-regs.h
@@ -16,5 +16,6 @@
 #define RK3568_UART9_BASE	0xfe6d0000
 
 #define RK3568_IRAM_BASE	0xfdcc0000
+#define RK3568_PMUGRF_BASE	0xfdc20000
 
 #endif /* __MACH_RK3568_REGS_H */
-- 
2.39.2




^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 3/6] ARM: Rockchip: Add rk3568 specific barebox entry function
  2023-03-28  7:40 [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Sascha Hauer
  2023-03-28  7:40 ` [PATCH v2 1/6] ARM: dts: rk356x: Add DMC controller node Sascha Hauer
  2023-03-28  7:40 ` [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller Sascha Hauer
@ 2023-03-28  7:40 ` Sascha Hauer
  2023-03-28  7:40 ` [PATCH v2 4/6] ARM: Rockchip: rk3568: use rk3568_barebox_entry() Sascha Hauer
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2023-03-28  7:40 UTC (permalink / raw)
  To: Barebox List

Add a rk3568 specific barebox entry function to simplify board
code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-rockchip/atf.c | 19 +++++++++++++++++++
 include/mach/rockchip/atf.h  |  2 ++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
index 93025faf68..9735cb8ef3 100644
--- a/arch/arm/mach-rockchip/atf.c
+++ b/arch/arm/mach-rockchip/atf.c
@@ -5,6 +5,9 @@
 #include <mach/rockchip/atf.h>
 #include <elf.h>
 #include <asm/atf_common.h>
+#include <asm/barebox-arm.h>
+#include <mach/rockchip/dmc.h>
+#include <mach/rockchip/rockchip.h>
 
 static unsigned long load_elf64_image_phdr(const void *elf)
 {
@@ -69,3 +72,19 @@ void rk3568_atf_load_bl31(void *fdt)
 {
 	rockchip_atf_load_bl31(RK3568, rk3568_bl31_bin, rk3568_op_tee_bin, fdt);
 }
+
+void __noreturn rk3568_barebox_entry(void *fdt)
+{
+	unsigned long membase, memsize;
+
+	membase = RK3568_DRAM_BOTTOM;
+	memsize = rk3568_ram0_size() - RK3568_DRAM_BOTTOM;
+
+	if (current_el() == 3) {
+		rk3568_lowlevel_init();
+		rk3568_atf_load_bl31(fdt);
+		/* not reached when CONFIG_ARCH_ROCKCHIP_ATF */
+	}
+
+	barebox_arm_entry(membase, memsize, fdt);
+}
diff --git a/include/mach/rockchip/atf.h b/include/mach/rockchip/atf.h
index e5d55af3d7..e1e68825d1 100644
--- a/include/mach/rockchip/atf.h
+++ b/include/mach/rockchip/atf.h
@@ -28,4 +28,6 @@ static inline void rk3568_atf_load_bl31(void *fdt) { }
 #endif
 #endif
 
+void __noreturn rk3568_barebox_entry(void *fdt);
+
 #endif /* __MACH_ATF_H */
-- 
2.39.2




^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 4/6] ARM: Rockchip: rk3568: use rk3568_barebox_entry()
  2023-03-28  7:40 [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Sascha Hauer
                   ` (2 preceding siblings ...)
  2023-03-28  7:40 ` [PATCH v2 3/6] ARM: Rockchip: Add rk3568 specific barebox entry function Sascha Hauer
@ 2023-03-28  7:40 ` Sascha Hauer
  2023-04-05  6:48   ` Sascha Hauer
  2023-03-28  7:40 ` [PATCH v2 5/6] ARM: Rockchip: make bootsource logic generic to all SoCs Sascha Hauer
                   ` (2 subsequent siblings)
  6 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2023-03-28  7:40 UTC (permalink / raw)
  To: Barebox List

There is a rk3568 specific entry function for barebox now, switch
the existing boards over to use it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/pine64-quartz64/lowlevel.c    | 30 +++--------------
 arch/arm/boards/radxa-rock3/lowlevel.c        | 31 +++---------------
 .../rockchip-rk3568-bpi-r2pro/lowlevel.c      | 31 +++---------------
 .../arm/boards/rockchip-rk3568-evb/lowlevel.c | 32 +++----------------
 4 files changed, 17 insertions(+), 107 deletions(-)

diff --git a/arch/arm/boards/pine64-quartz64/lowlevel.c b/arch/arm/boards/pine64-quartz64/lowlevel.c
index 1e63c0e698..975f8aa51c 100644
--- a/arch/arm/boards/pine64-quartz64/lowlevel.c
+++ b/arch/arm/boards/pine64-quartz64/lowlevel.c
@@ -1,41 +1,19 @@
 // SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/hardware.h>
 #include <mach/rockchip/atf.h>
 #include <debug_ll.h>
-#include <mach/rockchip/rockchip.h>
 
 extern char __dtb_rk3566_quartz64_a_start[];
 
-static noinline void start_quartz64(void)
-{
-	void *fdt = __dtb_rk3566_quartz64_a_start;
-
-	if (current_el() == 3) {
-		rk3568_lowlevel_init();
-		rk3568_atf_load_bl31(fdt);
-		/* not reached */
-	}
-
-	barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM,
-			  fdt);
-}
-
 ENTRY_FUNCTION(start_quartz64a, r0, r1, r2)
 {
-	/*
-	 * Image execution starts at 0x0, but this is used for ATF and
-	 * OP-TEE later, so move away from here.
-	 */
-	if (current_el() == 3)
-		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
-	else
-		relocate_to_current_adr();
+	putc_ll('>');
 
+	relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
 	setup_c();
 
-	start_quartz64();
+	rk3568_barebox_entry(__dtb_rk3566_quartz64_a_start);
 }
diff --git a/arch/arm/boards/radxa-rock3/lowlevel.c b/arch/arm/boards/radxa-rock3/lowlevel.c
index a8226749d4..866abd8bcb 100644
--- a/arch/arm/boards/radxa-rock3/lowlevel.c
+++ b/arch/arm/boards/radxa-rock3/lowlevel.c
@@ -1,19 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0-only
+
 #include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/hardware.h>
 #include <mach/rockchip/atf.h>
 #include <debug_ll.h>
-#include <mach/rockchip/rockchip.h>
 
 extern char __dtb_rk3568_rock_3a_start[];
 
-static noinline void rk3568_start(void)
+ENTRY_FUNCTION(start_rock3a, r0, r1, r2)
 {
-	void *fdt = __dtb_rk3568_rock_3a_start;
-
 	/*
 	 * Enable vccio4 1.8V and vccio6 1.8V
 	 * Needed for GMAC to work.
@@ -24,27 +20,10 @@ static noinline void rk3568_start(void)
 	 */
 	writel(RK_SETBITS(0x50), 0xfdc20140);
 
-	if (current_el() == 3) {
-		rk3568_lowlevel_init();
-		rk3568_atf_load_bl31(fdt);
-		/* not reached */
-	}
-
-	barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM, fdt);
-}
-
-ENTRY_FUNCTION(start_rock3a, r0, r1, r2)
-{
-	/*
-	 * Image execution starts at 0x0, but this is used for ATF and
-	 * OP-TEE later, so move away from here.
-	 */
-	if (current_el() == 3)
-		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
-	else
-		relocate_to_current_adr();
+	putc_ll('>');
 
+	relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
 	setup_c();
 
-	rk3568_start();
+	rk3568_barebox_entry(__dtb_rk3568_rock_3a_start);
 }
diff --git a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c
index 23bacc91d9..468d0f1ac3 100644
--- a/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c
+++ b/arch/arm/boards/rockchip-rk3568-bpi-r2pro/lowlevel.c
@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 #include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/hardware.h>
 #include <mach/rockchip/atf.h>
@@ -11,9 +9,9 @@
 
 extern char __dtb_rk3568_bpi_r2_pro_start[];
 
-static noinline void rk3568_start(void)
+ENTRY_FUNCTION(start_rk3568_bpi_r2pro, r0, r1, r2)
 {
-	void *fdt;
+	putc_ll('>');
 
 	/*
 	 * set iodomain vccio6 to 1.8V needed for GMAC1 to work.
@@ -28,29 +26,8 @@ static noinline void rk3568_start(void)
 	//clear bit 6 for 3v3 as it was set to 1v8
 	writel(RK_CLRBITS(BIT(6)), PMU_GRF_IO_VSEL1);
 
-	fdt = __dtb_rk3568_bpi_r2_pro_start;
-
-	if (current_el() == 3) {
-		rk3568_lowlevel_init();
-		rk3568_atf_load_bl31(fdt);
-		/* not reached */
-	}
-
-	barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM, fdt);
-}
-
-ENTRY_FUNCTION(start_rk3568_bpi_r2pro, r0, r1, r2)
-{
-	/*
-	 * Image execution starts at 0x0, but this is used for ATF and
-	 * OP-TEE later, so move away from here.
-	 */
-	if (current_el() == 3)
-		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
-	else
-		relocate_to_current_adr();
-
+	relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
 	setup_c();
 
-	rk3568_start();
+	rk3568_barebox_entry(__dtb_rk3568_bpi_r2_pro_start);
 }
diff --git a/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c
index 8720e6d9ae..100e6b0098 100644
--- a/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c
+++ b/arch/arm/boards/rockchip-rk3568-evb/lowlevel.c
@@ -1,20 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 #include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm-head.h>
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/hardware.h>
 #include <mach/rockchip/atf.h>
 #include <debug_ll.h>
-#include <mach/rockchip/rockchip.h>
 
 extern char __dtb_rk3568_evb1_v10_start[];
 
-static noinline void rk3568_start(void)
+ENTRY_FUNCTION(start_rk3568_evb, r0, r1, r2)
 {
-	void *fdt;
-
 	/*
 	 * Enable vccio4 1.8V and vccio6 1.8V
 	 * Needed for GMAC to work.
@@ -25,29 +20,10 @@ static noinline void rk3568_start(void)
 	 */
 	writel(RK_SETBITS(0x50), 0xfdc20140);
 
-	fdt = __dtb_rk3568_evb1_v10_start;
-
-	if (current_el() == 3) {
-		rk3568_lowlevel_init();
-		rk3568_atf_load_bl31(fdt);
-		/* not reached */
-	}
-
-	barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM, fdt);
-}
-
-ENTRY_FUNCTION(start_rk3568_evb, r0, r1, r2)
-{
-	/*
-	 * Image execution starts at 0x0, but this is used for ATF and
-	 * OP-TEE later, so move away from here.
-	 */
-	if (current_el() == 3)
-		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
-	else
-		relocate_to_current_adr();
+	putc_ll('>');
 
+	relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
 	setup_c();
 
-	rk3568_start();
+	rk3568_barebox_entry(__dtb_rk3568_evb1_v10_start);
 }
-- 
2.39.2




^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 5/6] ARM: Rockchip: make bootsource logic generic to all SoCs
  2023-03-28  7:40 [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Sascha Hauer
                   ` (3 preceding siblings ...)
  2023-03-28  7:40 ` [PATCH v2 4/6] ARM: Rockchip: rk3568: use rk3568_barebox_entry() Sascha Hauer
@ 2023-03-28  7:40 ` Sascha Hauer
  2023-03-28  7:40 ` [PATCH v2 6/6] ARM: Rockchip: Do not pass device tree to TF-A Sascha Hauer
  2023-03-31 15:42 ` [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Michael Riesch
  6 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2023-03-28  7:40 UTC (permalink / raw)
  To: Barebox List; +Cc: Ahmad Fatoum

From: Ahmad Fatoum <ahmad@a3f.at>

Decoding of the bootsource from the register value can be shared across
multiple Rockchip SoCs. Move the code to a common place to allow for
that.
At least with some TF-A versions the IRAM where the bootsource is stored
cannot not be accessed in normal mode, so read it out before we start
the TF-A. For this the scratch space is used.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-rockchip/Makefile  |  2 +-
 arch/arm/mach-rockchip/atf.c     |  3 ++
 arch/arm/mach-rockchip/bootrom.c | 51 ++++++++++++++++++++++++++++++++
 arch/arm/mach-rockchip/rk3568.c  | 29 ++----------------
 include/bootsource.h             |  1 +
 include/mach/rockchip/bootrom.h  | 32 ++++++++++++++++++++
 6 files changed, 90 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/bootrom.c
 create mode 100644 include/mach/rockchip/bootrom.h

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index f6c575854e..04d75ce287 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-obj-y += rockchip.o
+obj-y += rockchip.o bootrom.o
 pbl-$(CONFIG_ARCH_ROCKCHIP_ATF) += atf.o
 obj-$(CONFIG_ARCH_RK3188) += rk3188.o
 obj-$(CONFIG_ARCH_RK3288) += rk3288.o
diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
index 9735cb8ef3..f3fb50b990 100644
--- a/arch/arm/mach-rockchip/atf.c
+++ b/arch/arm/mach-rockchip/atf.c
@@ -8,6 +8,8 @@
 #include <asm/barebox-arm.h>
 #include <mach/rockchip/dmc.h>
 #include <mach/rockchip/rockchip.h>
+#include <mach/rockchip/bootrom.h>
+#include <mach/rockchip/rk3568-regs.h>
 
 static unsigned long load_elf64_image_phdr(const void *elf)
 {
@@ -82,6 +84,7 @@ void __noreturn rk3568_barebox_entry(void *fdt)
 
 	if (current_el() == 3) {
 		rk3568_lowlevel_init();
+		rockchip_store_bootrom_iram(membase, memsize, IOMEM(RK3568_IRAM_BASE));
 		rk3568_atf_load_bl31(fdt);
 		/* not reached when CONFIG_ARCH_ROCKCHIP_ATF */
 	}
diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
new file mode 100644
index 0000000000..cdd0536cda
--- /dev/null
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <mach/rockchip/bootrom.h>
+#include <io.h>
+#include <bootsource.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <errno.h>
+
+#define BROM_BOOTSOURCE_ID	0x10
+#define BROM_BOOTSOURCE_SLOT	0x14
+#define	BROM_BOOTSOURCE_SLOT_ACTIVE	GENMASK(12, 10)
+
+static const void __iomem *rk_iram;
+
+int rockchip_bootsource_get_active_slot(void)
+{
+	if (!rk_iram)
+		return -EINVAL;
+
+	return FIELD_GET(BROM_BOOTSOURCE_SLOT_ACTIVE,
+			 readl(IOMEM(rk_iram) + BROM_BOOTSOURCE_SLOT));
+}
+
+struct rk_bootsource {
+	enum bootsource src;
+	int instance;
+};
+
+static struct rk_bootsource bootdev_map[] = {
+	[0x1] = { .src = BOOTSOURCE_NAND, .instance = 0 },
+	[0x2] = { .src = BOOTSOURCE_MMC, .instance = 0 },
+	[0x3] = { .src = BOOTSOURCE_SPI_NOR, .instance = 0 },
+	[0x4] = { .src = BOOTSOURCE_SPI_NAND, .instance = 0 },
+	[0x5] = { .src = BOOTSOURCE_MMC, .instance = 1 },
+	[0xa] = { .src = BOOTSOURCE_USB, .instance = 0 },
+};
+
+void rockchip_parse_bootrom_iram(const void *iram)
+{
+	u32 v;
+
+	rk_iram = iram;
+
+	v = readl(iram + BROM_BOOTSOURCE_ID);
+
+	if (v >= ARRAY_SIZE(bootdev_map))
+		return;
+
+	bootsource_set(bootdev_map[v].src, bootdev_map[v].instance);
+}
diff --git a/arch/arm/mach-rockchip/rk3568.c b/arch/arm/mach-rockchip/rk3568.c
index 39bd4772a6..c0453ea0c4 100644
--- a/arch/arm/mach-rockchip/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568.c
@@ -2,6 +2,7 @@
 #include <common.h>
 #include <io.h>
 #include <bootsource.h>
+#include <mach/rockchip/bootrom.h>
 #include <mach/rockchip/rk3568-regs.h>
 #include <mach/rockchip/rockchip.h>
 
@@ -137,35 +138,9 @@ void rk3568_lowlevel_init(void)
 	qos_priority_init();
 }
 
-struct rk_bootsource {
-	enum bootsource src;
-	int instance;
-};
-
-static struct rk_bootsource bootdev_map[] = {
-	[0x1] = { .src = BOOTSOURCE_NAND, .instance = 0 },
-	[0x2] = { .src = BOOTSOURCE_MMC, .instance = 0 },
-	[0x3] = { .src = BOOTSOURCE_SPI_NOR, .instance = 0 },
-	[0x4] = { .src = BOOTSOURCE_SPI_NAND, .instance = 0 },
-	[0x5] = { .src = BOOTSOURCE_MMC, .instance = 1 },
-	[0xa] = { .src = BOOTSOURCE_USB, .instance = 0 },
-};
-
-static void rk3568_bootsource(void)
-{
-	u32 v;
-
-	v = readl(RK3568_IRAM_BASE + 0x10);
-
-	if (v >= ARRAY_SIZE(bootdev_map))
-		return;
-
-	bootsource_set(bootdev_map[v].src, bootdev_map[v].instance);
-}
-
 int rk3568_init(void)
 {
-	rk3568_bootsource();
+	rockchip_parse_bootrom_iram(rockchip_scratch_space());
 
 	return 0;
 }
diff --git a/include/bootsource.h b/include/bootsource.h
index 05935b64a7..f2ab3a2ad4 100644
--- a/include/bootsource.h
+++ b/include/bootsource.h
@@ -26,6 +26,7 @@ enum bootsource {
 #define BOOTSOURCE_INSTANCE_UNKNOWN	-1
 
 enum bootsource bootsource_get(void);
+enum bootsource bootsource_get_device(void);
 int bootsource_get_instance(void);
 void bootsource_set_alias_name(const char *name);
 char *bootsource_get_alias_name(void);
diff --git a/include/mach/rockchip/bootrom.h b/include/mach/rockchip/bootrom.h
new file mode 100644
index 0000000000..96eb147ae4
--- /dev/null
+++ b/include/mach/rockchip/bootrom.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __MACH_ROCKCHIP_BOOTROM_H
+#define __MACH_ROCKCHIP_BOOTROM_H
+
+#include <linux/compiler.h>
+#include <linux/string.h>
+#include <asm/barebox-arm.h>
+
+struct rockchip_scratch_space {
+	u32 irom[16];
+};
+
+static inline void rockchip_store_bootrom_iram(ulong membase,
+                                               ulong memsize,
+                                               const void *iram)
+{
+	void *dst = (void *)__arm_mem_scratch(membase + memsize);
+	memcpy(dst, iram, sizeof(struct rockchip_scratch_space));
+}
+
+static inline const struct rockchip_scratch_space *rockchip_scratch_space(void)
+{
+	return arm_mem_scratch_get();
+}
+
+void rockchip_parse_bootrom_iram(const void *iram);
+
+int rockchip_bootsource_get_active_slot(void);
+
+
+#endif
-- 
2.39.2




^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 6/6] ARM: Rockchip: Do not pass device tree to TF-A
  2023-03-28  7:40 [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Sascha Hauer
                   ` (4 preceding siblings ...)
  2023-03-28  7:40 ` [PATCH v2 5/6] ARM: Rockchip: make bootsource logic generic to all SoCs Sascha Hauer
@ 2023-03-28  7:40 ` Sascha Hauer
  2023-03-31 15:42 ` [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Michael Riesch
  6 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2023-03-28  7:40 UTC (permalink / raw)
  To: Barebox List

The downstream TF-A doesn't cope with our device tree when
CONFIG_OF_OVERLAY_LIVE is enabled, supposedly because it is
too big for some reason. Otherwise it doesn't have any visible
effect if we pass a device tree or not, except that the TF-A
fills in the ethernet MAC address into the device tree.
The upstream TF-A doesn't use the device tree at all.

Pass NULL for now until we have a good reason to pass a real
device tree.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-rockchip/atf.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/atf.c b/arch/arm/mach-rockchip/atf.c
index f3fb50b990..d1431cc526 100644
--- a/arch/arm/mach-rockchip/atf.c
+++ b/arch/arm/mach-rockchip/atf.c
@@ -85,7 +85,19 @@ void __noreturn rk3568_barebox_entry(void *fdt)
 	if (current_el() == 3) {
 		rk3568_lowlevel_init();
 		rockchip_store_bootrom_iram(membase, memsize, IOMEM(RK3568_IRAM_BASE));
-		rk3568_atf_load_bl31(fdt);
+
+		/*
+		 * The downstream TF-A doesn't cope with our device tree when
+		 * CONFIG_OF_OVERLAY_LIVE is enabled, supposedly because it is
+		 * too big for some reason. Otherwise it doesn't have any visible
+		 * effect if we pass a device tree or not, except that the TF-A
+		 * fills in the ethernet MAC address into the device tree.
+		 * The upstream TF-A doesn't use the device tree at all.
+		 *
+		 * Pass NULL for now until we have a good reason to pass a real
+		 * device tree.
+		 */
+		rk3568_atf_load_bl31(NULL);
 		/* not reached when CONFIG_ARCH_ROCKCHIP_ATF */
 	}
 
-- 
2.39.2




^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller
  2023-03-28  7:40 ` [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller Sascha Hauer
@ 2023-03-28  8:18   ` Sascha Hauer
  2023-04-03 19:43   ` Sascha Hauer
  1 sibling, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2023-03-28  8:18 UTC (permalink / raw)
  To: Barebox List; +Cc: Ahmad Fatoum

On Tue, Mar 28, 2023 at 09:40:33AM +0200, Sascha Hauer wrote:
> From: Ahmad Fatoum <ahmad@a3f.at>
> 
> Add a driver to read out the amount of memory from the DDR controller.
> The decoding of the registers has been taken from U-Boot. Currently
> supported are the RK3399 and the RK3568, but decoding should work on
> other Rockchip SoCs as well.
> 
> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/mach-rockchip/Makefile     |   1 +
>  arch/arm/mach-rockchip/dmc.c        | 232 ++++++++++++++++++++++++++++
>  include/linux/sizes.h               |   3 +
>  include/mach/rockchip/dmc.h         |  86 +++++++++++
>  include/mach/rockchip/rk3399-regs.h |   1 +
>  include/mach/rockchip/rk3568-regs.h |   1 +
>  6 files changed, 324 insertions(+)
>  create mode 100644 arch/arm/mach-rockchip/dmc.c
>  create mode 100644 include/mach/rockchip/dmc.h
> 
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 2529af7c7e..f6c575854e 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -6,4 +6,5 @@ obj-$(CONFIG_ARCH_RK3188) += rk3188.o
>  obj-$(CONFIG_ARCH_RK3288) += rk3288.o
>  obj-pbl-$(CONFIG_ARCH_RK3568) += rk3568.o
>  obj-$(CONFIG_ARCH_ROCKCHIP_V8) += bootm.o
> +obj-pbl-$(CONFIG_ARCH_ROCKCHIP_V8) += dmc.o
>  obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
> diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
> new file mode 100644
> index 0000000000..97968b0544
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/dmc.c
> @@ -0,0 +1,232 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + */
> +
> +#define pr_fmt(fmt) "rockchip-dmc: " fmt
> +
> +#include <common.h>
> +#include <init.h>
> +#include <asm/barebox-arm.h>
> +#include <asm/memory.h>
> +#include <pbl.h>
> +#include <io.h>
> +#include <regmap.h>
> +#include <mfd/syscon.h>
> +#include <mach/rockchip/dmc.h>
> +#include <mach/rockchip/rk3399-regs.h>
> +#include <mach/rockchip/rk3568-regs.h>
> +
> +#define RK3399_PMUGRF_OS_REG2		0x308
> +#define RK3399_PMUGRF_OS_REG3		0x30C
> +
> +#define RK3568_PMUGRF_OS_REG2           0x208
> +#define RK3568_PMUGRF_OS_REG3           0x20c
> +
> +struct rockchip_dmc_region {
> +	resource_size_t base, size;
> +};
> +
> +struct rockchip_dmc_drvdata {
> +	unsigned int os_reg2;
> +	unsigned int os_reg3;
> +	const struct rockchip_dmc_region *regions;
> +};
> +
> +static resource_size_t rockchip_sdram_size(u32 sys_reg2, u32 sys_reg3)
> +{
> +	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
> +	resource_size_t chipsize_mb, size_mb = 0;
> +	u32 ch;
> +	u32 cs1_col;
> +	u32 bg = 0;
> +	u32 dbw, dram_type;
> +	u32 ch_num = 1 + FIELD_GET(SYS_REG_NUM_CH, sys_reg2);
> +	u32 version = FIELD_GET(SYS_REG_VERSION, sys_reg3);
> +
> +	pr_debug("%s(reg2=%x, reg3=%x)\n", __func__, sys_reg2, sys_reg3);
> +
> +	dram_type = FIELD_GET(SYS_REG_DDRTYPE, sys_reg2);
> +
> +	if (version >= 3)
> +		dram_type |= FIELD_GET(SYS_REG_EXTEND_DDRTYPE, sys_reg3) << 3;
> +
> +	for (ch = 0; ch < ch_num; ch++) {
> +		rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK);
> +		cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
> +		cs1_col = cs0_col;
> +
> +		bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
> +
> +		cs0_row = sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK;
> +		cs1_row = sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK;
> +
> +		if (version >= 2) {
> +			cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
> +				  SYS_REG_CS1_COL_MASK);
> +
> +			cs0_row |= (sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
> +					SYS_REG_EXTEND_CS0_ROW_MASK) << 2;
> +
> +			if (cs0_row == 7)
> +				cs0_row = 12;
> +			else
> +				cs0_row += 13;
> +
> +			cs1_row |= (sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
> +					SYS_REG_EXTEND_CS1_ROW_MASK) << 2;
> +
> +			if (cs1_row == 7)
> +				cs1_row = 12;
> +			else
> +				cs1_row += 13;
> +		} else {
> +			cs0_row += 13;
> +			cs1_row += 13;
> +		}
> +
> +		bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & SYS_REG_BW_MASK));
> +		row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK;
> +
> +		if (dram_type == DDR4) {
> +			dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & SYS_REG_DBW_MASK;
> +			bg = (dbw == 2) ? 2 : 1;
> +		}
> +
> +		chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
> +
> +		if (rank > 1)
> +			chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
> +				       (cs0_col - cs1_col));
> +		if (row_3_4)
> +			chipsize_mb = chipsize_mb * 3 / 4;
> +
> +		size_mb += chipsize_mb;
> +
> +		if (rank > 1)
> +			pr_debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d "
> +				 "cs1_row %d bw %d row_3_4 %d\n",
> +				 rank, cs0_col, cs1_col, bk, cs0_row,
> +				 cs1_row, bw, row_3_4);
> +		else
> +			pr_debug("rank %d cs0_col %d bk %d cs0_row %d "
> +				 "bw %d row_3_4 %d\n",
> +				 rank, cs0_col, bk, cs0_row,
> +				 bw, row_3_4);
> +	}
> +
> +	return (resource_size_t)size_mb << 20;
> +}
> +
> +resource_size_t rk3399_ram0_size(void)
> +{
> +	void __iomem *pmugrf = IOMEM(RK3399_PMUGRF_BASE);
> +	u32 sys_reg2, sys_reg3;
> +	resource_size_t size;
> +
> +	sys_reg2 = readl(pmugrf + RK3399_PMUGRF_OS_REG2);
> +	sys_reg3 = readl(pmugrf + RK3399_PMUGRF_OS_REG3);
> +
> +	size = rockchip_sdram_size(sys_reg2, sys_reg3);
> +	size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
> +
> +	pr_debug("%s() = %llu\n", __func__, (u64)size);
> +
> +	return size;
> +}
> +
> +resource_size_t rk3568_ram0_size(void)
> +{
> +	void __iomem *pmugrf = IOMEM(RK3568_PMUGRF_BASE);
> +	u32 sys_reg2, sys_reg3;
> +	resource_size_t size;
> +
> +	sys_reg2 = readl(pmugrf + RK3568_PMUGRF_OS_REG2);
> +	sys_reg3 = readl(pmugrf + RK3568_PMUGRF_OS_REG3);
> +
> +	size = rockchip_sdram_size(sys_reg2, sys_reg3);
> +	size = min_t(resource_size_t, SZ_4G - SZ_128M, size);

I should have added a define immediately when I first noticed this value
is used multiple times in this patch.

Sascha

-------------------------8<----------------------------

>From 13751c530ea4fe6c9f3f85afde0be290383491fa Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Tue, 28 Mar 2023 10:14:28 +0200
Subject: [PATCH] fixup! ARM: Rockchip: implement memory read out from
 controller

---
 arch/arm/mach-rockchip/dmc.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
index 97968b0544..02dc26b7b5 100644
--- a/arch/arm/mach-rockchip/dmc.c
+++ b/arch/arm/mach-rockchip/dmc.c
@@ -23,6 +23,9 @@
 #define RK3568_PMUGRF_OS_REG2           0x208
 #define RK3568_PMUGRF_OS_REG3           0x20c
 
+#define RK3399_MEM0_END		0xf0000000
+#define RK3568_MEM0_END		RK3399_MEM0_END
+
 struct rockchip_dmc_region {
 	resource_size_t base, size;
 };
@@ -128,7 +131,7 @@ resource_size_t rk3399_ram0_size(void)
 	sys_reg3 = readl(pmugrf + RK3399_PMUGRF_OS_REG3);
 
 	size = rockchip_sdram_size(sys_reg2, sys_reg3);
-	size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
+	size = min_t(resource_size_t, RK3399_MEM0_END, size);
 
 	pr_debug("%s() = %llu\n", __func__, (u64)size);
 
@@ -145,7 +148,7 @@ resource_size_t rk3568_ram0_size(void)
 	sys_reg3 = readl(pmugrf + RK3568_PMUGRF_OS_REG3);
 
 	size = rockchip_sdram_size(sys_reg2, sys_reg3);
-	size = min_t(resource_size_t, SZ_4G - SZ_128M, size);
+	size = min_t(resource_size_t, RK3568_MEM0_END, size);
 
 	pr_debug("%s() = %llu\n", __func__, (u64)size);
 
@@ -193,7 +196,7 @@ static int rockchip_dmc_probe(struct device *dev)
 static const struct rockchip_dmc_region rk3399_regions[] = {
 	{
 		.base = 0x0,
-		.size = 0xf0000000,
+		.size = RK3399_MEM0_END,
 	}, {
 		.base = SZ_4G,
 		.size = SZ_32G,
-- 
2.39.2


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller
  2023-03-28  7:40 [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Sascha Hauer
                   ` (5 preceding siblings ...)
  2023-03-28  7:40 ` [PATCH v2 6/6] ARM: Rockchip: Do not pass device tree to TF-A Sascha Hauer
@ 2023-03-31 15:42 ` Michael Riesch
  2023-04-03  7:32   ` Sascha Hauer
  6 siblings, 1 reply; 14+ messages in thread
From: Michael Riesch @ 2023-03-31 15:42 UTC (permalink / raw)
  To: barebox

Hi Sascha,

On 3/28/23 09:40, Sascha Hauer wrote:
> This series adds support for reading the amount of memory from
> the DDR controller. This helps on boards which come with
> different amounts of memory like the Radxa Rock3a.
> 
> This series also fixes issues with an upstream TF-A firmware. With this
> the IRAM where the bootsource is stored is no longer accessible in
> normal mode. We have to read its contents before starting the TF-A.
> For this it became necessary to add a common barebox entry function
> for rk3568, to get a common place to read the IRAM contents.

Nice, thanks for your efforts! Now it should be possible to remove the
memory nodes from arch/arm/dts/rk356*, right?

I tried this on a ROCK3A with 8 GB and the memory calculation returned
the correct result. There are now two ram devices

   `-- mem0
      `-- 0x00000000-0x10fffffff (   4.3 GiB): /dev/ram1
   `-- mem1
      `-- 0x00000000-0xef5fffff (   3.7 GiB): /dev/ram0
   `-- mem2
      `-- 0x00000000-0xffffffffffffffff (   0 Bytes): /dev/mem

that start at SZ_4G and 0xa00000, respectively.

However, after loading the kernel the system hangs:

Loaded kernel to 0x100000000, devicetree at 0x101970000

Is this a bug in barebox or is something special required to boot the
kernel from SZ_4G?

Best regards,
Michael

> 
> Sascha
> 
> Changes since v1:
> - Call relocate_to_adr_full() from board code to make sure the
>   fdt from the relocated binary is used, not from the original
>   binary
> - Add patch to pass a NULL fdt to TF-A
> 
> Ahmad Fatoum (2):
>   ARM: Rockchip: implement memory read out from controller
>   ARM: Rockchip: make bootsource logic generic to all SoCs
> 
> Sascha Hauer (4):
>   ARM: dts: rk356x: Add DMC controller node
>   ARM: Rockchip: Add rk3568 specific barebox entry function
>   ARM: Rockchip: rk3568: use rk3568_barebox_entry()
>   ARM: Rockchip: Do not pass device tree to TF-A
> 
>  arch/arm/boards/pine64-quartz64/lowlevel.c    |  30 +--
>  arch/arm/boards/radxa-rock3/lowlevel.c        |  31 +--
>  .../rockchip-rk3568-bpi-r2pro/lowlevel.c      |  31 +--
>  .../arm/boards/rockchip-rk3568-evb/lowlevel.c |  32 +--
>  arch/arm/dts/rk356x.dtsi                      |   5 +
>  arch/arm/mach-rockchip/Makefile               |   3 +-
>  arch/arm/mach-rockchip/atf.c                  |  34 +++
>  arch/arm/mach-rockchip/bootrom.c              |  51 ++++
>  arch/arm/mach-rockchip/dmc.c                  | 232 ++++++++++++++++++
>  arch/arm/mach-rockchip/rk3568.c               |  29 +--
>  include/bootsource.h                          |   1 +
>  include/linux/sizes.h                         |   3 +
>  include/mach/rockchip/atf.h                   |   2 +
>  include/mach/rockchip/bootrom.h               |  32 +++
>  include/mach/rockchip/dmc.h                   |  86 +++++++
>  include/mach/rockchip/rk3399-regs.h           |   1 +
>  include/mach/rockchip/rk3568-regs.h           |   1 +
>  17 files changed, 469 insertions(+), 135 deletions(-)
>  create mode 100644 arch/arm/mach-rockchip/bootrom.c
>  create mode 100644 arch/arm/mach-rockchip/dmc.c
>  create mode 100644 include/mach/rockchip/bootrom.h
>  create mode 100644 include/mach/rockchip/dmc.h
> 



^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller
  2023-03-31 15:42 ` [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Michael Riesch
@ 2023-04-03  7:32   ` Sascha Hauer
  2023-04-03 10:04     ` Michael Riesch
  0 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2023-04-03  7:32 UTC (permalink / raw)
  To: Michael Riesch; +Cc: barebox

On Fri, Mar 31, 2023 at 05:42:54PM +0200, Michael Riesch wrote:
> Hi Sascha,
> 
> On 3/28/23 09:40, Sascha Hauer wrote:
> > This series adds support for reading the amount of memory from
> > the DDR controller. This helps on boards which come with
> > different amounts of memory like the Radxa Rock3a.
> > 
> > This series also fixes issues with an upstream TF-A firmware. With this
> > the IRAM where the bootsource is stored is no longer accessible in
> > normal mode. We have to read its contents before starting the TF-A.
> > For this it became necessary to add a common barebox entry function
> > for rk3568, to get a common place to read the IRAM contents.
> 
> Nice, thanks for your efforts! Now it should be possible to remove the
> memory nodes from arch/arm/dts/rk356*, right?
> 
> I tried this on a ROCK3A with 8 GB and the memory calculation returned
> the correct result. There are now two ram devices
> 
>    `-- mem0
>       `-- 0x00000000-0x10fffffff (   4.3 GiB): /dev/ram1
>    `-- mem1
>       `-- 0x00000000-0xef5fffff (   3.7 GiB): /dev/ram0
>    `-- mem2
>       `-- 0x00000000-0xffffffffffffffff (   0 Bytes): /dev/mem

At first sight I was a bit puzzled that both memory regions start a 0x0.
That's correct for the devinfo output of course. The output of 'iomem'
would show the situation better here.

> 
> that start at SZ_4G and 0xa00000, respectively.
> 
> However, after loading the kernel the system hangs:
> 
> Loaded kernel to 0x100000000, devicetree at 0x101970000
> 
> Is this a bug in barebox or is something special required to boot the
> kernel from SZ_4G?

I would have guessed that barebox puts the kernel below the malloc area
just as usual. Ok, apparently it doesn't. I haven't found anything in
Documentation/arm64/booting.rst that forbids placing the kernel above
the 32bit boundary. You could verify that the memory nodes barebox
writes meet your expectations by adding some -v to the boot command.
Also earlycon might help to get some output from the kernel.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller
  2023-04-03  7:32   ` Sascha Hauer
@ 2023-04-03 10:04     ` Michael Riesch
  0 siblings, 0 replies; 14+ messages in thread
From: Michael Riesch @ 2023-04-03 10:04 UTC (permalink / raw)
  To: Sascha Hauer; +Cc: barebox

Hi Sascha,

On 4/3/23 09:32, Sascha Hauer wrote:
> On Fri, Mar 31, 2023 at 05:42:54PM +0200, Michael Riesch wrote:
>> Hi Sascha,
>>
>> On 3/28/23 09:40, Sascha Hauer wrote:
>>> This series adds support for reading the amount of memory from
>>> the DDR controller. This helps on boards which come with
>>> different amounts of memory like the Radxa Rock3a.
>>>
>>> This series also fixes issues with an upstream TF-A firmware. With this
>>> the IRAM where the bootsource is stored is no longer accessible in
>>> normal mode. We have to read its contents before starting the TF-A.
>>> For this it became necessary to add a common barebox entry function
>>> for rk3568, to get a common place to read the IRAM contents.
>>
>> Nice, thanks for your efforts! Now it should be possible to remove the
>> memory nodes from arch/arm/dts/rk356*, right?
>>
>> I tried this on a ROCK3A with 8 GB and the memory calculation returned
>> the correct result. There are now two ram devices
>>
>>    `-- mem0
>>       `-- 0x00000000-0x10fffffff (   4.3 GiB): /dev/ram1
>>    `-- mem1
>>       `-- 0x00000000-0xef5fffff (   3.7 GiB): /dev/ram0
>>    `-- mem2
>>       `-- 0x00000000-0xffffffffffffffff (   0 Bytes): /dev/mem
> 
> At first sight I was a bit puzzled that both memory regions start a 0x0.
> That's correct for the devinfo output of course. The output of 'iomem'
> would show the situation better here.

barebox@Radxa ROCK3 Model A:/ iomem
0x0000000000000000 - 0xffffffffffffffff (size 0x0000000000000000) iomem
  0x0000000000a00000 - 0x00000000efffffff (size 0x00000000ef600000) ram0
    0x00000000afcf0e00 - 0x00000000efcf0dff (size 0x0000000040000000)
malloc space
    0x00000000efcf0e00 - 0x00000000efcfffd1 (size 0x000000000000f1d2)
board data
    0x00000000efd00000 - 0x00000000efd99a4f (size 0x0000000000099a50)
barebox
    0x00000000efd99a50 - 0x00000000efde59ff (size 0x000000000004bfb0)
barebox data
    0x00000000efde5a00 - 0x00000000efde8d57 (size 0x0000000000003358) bss
    0x00000000effe8000 - 0x00000000effeffff (size 0x0000000000008000) stack
  0x00000000fd000000 - 0x00000000fd3fffff (size 0x0000000000400000) xHCI0
  0x00000000fdd40000 - 0x00000000fdd40fff (size 0x0000000000001000)
fdd40000.i2c@fdd40000.of
  0x00000000fdd60000 - 0x00000000fdd600ff (size 0x0000000000000100)
pinctrl.of
  0x00000000fe000000 - 0x00000000fe003fff (size 0x0000000000004000)
fe000000.mmc@fe000000.of
  0x00000000fe010000 - 0x00000000fe01ffff (size 0x0000000000010000)
fe010000.ethernet@fe010000.of
  0x00000000fe2b0000 - 0x00000000fe2b3fff (size 0x0000000000004000)
fe2b0000.mmc@fe2b0000.of
  0x00000000fe310000 - 0x00000000fe31ffff (size 0x0000000000010000)
fe310000.mmc@fe310000.of
  0x00000000fe5e0000 - 0x00000000fe5e0fff (size 0x0000000000001000)
fe5e0000.i2c@fe5e0000.of
  0x00000000fe650000 - 0x00000000fe6500ff (size 0x0000000000000100)
fe650000.serial@fe650000.of
  0x00000000fe660000 - 0x00000000fe6600ff (size 0x0000000000000100)
fe660000.serial@fe660000.of
  0x00000000fe720000 - 0x00000000fe7200ff (size 0x0000000000000100)
fe720000.saradc@fe720000.of
  0x00000000fe740000 - 0x00000000fe7400ff (size 0x0000000000000100)
pinctrl.of
  0x00000000fe750000 - 0x00000000fe7500ff (size 0x0000000000000100)
pinctrl.of
  0x00000000fe760000 - 0x00000000fe7600ff (size 0x0000000000000100)
pinctrl.of
  0x00000000fe770000 - 0x00000000fe7700ff (size 0x0000000000000100)
pinctrl.of
  0x00000000fe820000 - 0x00000000fe8200ff (size 0x0000000000000100)
fe820000.phy@fe820000.of
  0x00000000fe830000 - 0x00000000fe8300ff (size 0x0000000000000100)
fe830000.phy@fe830000.of
  0x00000000fe840000 - 0x00000000fe8400ff (size 0x0000000000000100)
fe840000.phy@fe840000.of
  0x00000000fe8a0000 - 0x00000000fe8affff (size 0x0000000000010000)
fe8a0000.usb2phy@fe8a0000.of
  0x00000000fe8b0000 - 0x00000000fe8bffff (size 0x0000000000010000)
fe8b0000.usb2phy@fe8b0000.of
  0x0000000100000000 - 0x000000020fffffff (size 0x0000000110000000) ram1
barebox@Radxa ROCK3 Model A:/

>> that start at SZ_4G and 0xa00000, respectively.
>>
>> However, after loading the kernel the system hangs:
>>
>> Loaded kernel to 0x100000000, devicetree at 0x101970000
>>
>> Is this a bug in barebox or is something special required to boot the
>> kernel from SZ_4G?
> 
> I would have guessed that barebox puts the kernel below the malloc area
> just as usual. Ok, apparently it doesn't. I haven't found anything in
> Documentation/arm64/booting.rst that forbids placing the kernel above
> the 32bit boundary. You could verify that the memory nodes barebox
> writes meet your expectations by adding some -v to the boot command.
> Also earlycon might help to get some output from the kernel.

After having a quick look at booti.c I think that
memory_bank_first_find_space is invoked to determine the start address.
Apparently, this returns the start and end of ram1. I tried to override
the start and end variables with the boundaries of ram0, which caused
the kernel to boot from 0xa00000 but didn't bring any further success.

With the earlycon parameter set, the boot log now shows:

Loaded kernel to 0x00a00000, devicetree at 0x02370000
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
[    0.000000] Linux version 6.3.0-rc2-20230316-1+ (ptxdist@ptxdist)
(aarch64-v8a-linux-gnu-gcc (OSELAS.0
[    0.000000] Machine model: Radxa ROCK3 Model A
[    0.000000] earlycon: uart0 at MMIO32 0x00000000fe660000 (options
'1500000n8')
[    0.000000] printk: bootconsole [uart0] enabled
[    0.000000] SError Interrupt on CPU0, code 0x00000000be000011 -- SError
[    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted
6.3.0-rc2-20230316-1+ #17
[    0.000000] Hardware name: Radxa ROCK3 Model A (DT)
[    0.000000] pstate: 200000c9 (nzCv daIF -PAN -UAO -TCO -DIT -SSBS
BTYPE=--)
[    0.000000] pc : __memset+0x16c/0x188
[    0.000000] lr : early_pgtable_alloc+0xb0/0x130
[    0.000000] sp : ffffffc009753b10
[    0.000000] x29: ffffffc009753b10 x28: 0000000000000000 x27:
0000000000a10000
[    0.000000] x26: ffffffc008c9ffff x25: ffffffc008010000 x24:
0000000000000000
[    0.000000] x23: ffffffc008010000 x22: fffffffdfda36000 x21:
ffffffc0097dd000
[    0.000000] x20: 000000020ffff000 x19: caaead2f6f13289c x18:
0000000000000000
[    0.000000] x17: 386e303030303035 x16: 312720736e6f6974 x15:
0000000000000000
[    0.000000] x14: 0000000000000000 x13: 0000000000000000 x12:
000000000002667a
[    0.000000] x11: 656c6f736e6f6374 x10: ffffffc007600000 x9 :
0000000000000000
[    0.000000] x8 : fffffffdfda39780 x7 : 0000000000000000 x6 :
000000000000003f
[    0.000000] x5 : 0000000000000040 x4 : 0000000000000000 x3 :
0000000000000004
[    0.000000] x2 : 0000000000000840 x1 : 0000000000000000 x0 :
fffffffdfda39000
[    0.000000] Kernel panic - not syncing: Asynchronous SError Interrupt
[    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted
6.3.0-rc2-20230316-1+ #17
[    0.000000] Hardware name: Radxa ROCK3 Model A (DT)
[    0.000000] Call trace:
[    0.000000]  dump_backtrace+0xb4/0x138
[    0.000000]  show_stack+0x30/0x48
[    0.000000]  dump_stack_lvl+0x60/0xb0
[    0.000000]  dump_stack+0x18/0x28
[    0.000000]  panic+0x394/0x3a8
[    0.000000]  nmi_panic+0xbc/0xc8
[    0.000000]  arm64_serror_panic+0x6c/0x88
[    0.000000]  do_serror+0x44/0x88
[    0.000000]  el1h_64_error_handler+0x38/0x50
[    0.000000]  el1h_64_error+0x64/0x68
[    0.000000]  __memset+0x16c/0x188
[    0.000000]  create_kpti_ng_temp_pgd+0x110/0x640
[    0.000000]  map_kernel_segment+0xd0/0x1b0
[    0.000000]  paging_init+0x1c8/0xdb0
[    0.000000]  setup_arch+0x3c8/0xa40
[    0.000000]  start_kernel+0xe0/0xcf8
[    0.000000]  __primary_switched+0xb4/0xc8

and boot -vvvv prints the memory nodes:

        memory@100000000 {
                device_type = "memory";
                reg = <0x1 0x0 0x1 0x10000000>;
        };
        memory@a00000 {
                device_type = "memory";
                reg = <0x0 0xa00000 0x0 0xef600000>;
        };

FWIW: I commented out the arm_add_mem_device call for ram1. With that
change, only the memory@a00000 is appended and the kernel boots normally
on the ROCK3A 8GB.

Thanks and best regards,
Michael



^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller
  2023-03-28  7:40 ` [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller Sascha Hauer
  2023-03-28  8:18   ` Sascha Hauer
@ 2023-04-03 19:43   ` Sascha Hauer
  2023-04-04  6:25     ` Michael Riesch
  1 sibling, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2023-04-03 19:43 UTC (permalink / raw)
  To: Barebox List; +Cc: Ahmad Fatoum, Michael Riesch

On Tue, Mar 28, 2023 at 09:40:33AM +0200, Sascha Hauer wrote:
> From: Ahmad Fatoum <ahmad@a3f.at>
> 
> Add a driver to read out the amount of memory from the DDR controller.
> The decoding of the registers has been taken from U-Boot. Currently
> supported are the RK3399 and the RK3568, but decoding should work on
> other Rockchip SoCs as well.
> 

This patch needs an update. The RAM is divided into two parts, one below
the SoC internal register space and one starting at 4GiB up to the end.
The previous version assumed that the RAM address decoding skips
the internal register space, but it seems the internal register space
shadows the RAM behind it, so a board with 8GiB of memory has the
last address on 0x200000000-1 instead of 0x210000000-1 like the previous
version assumed.

----------------------------------8<----------------------------

>From bc9baa7ac71c4a8e75d000317d85d6bf6a85a8e4 Mon Sep 17 00:00:00 2001
From: Ahmad Fatoum <ahmad@a3f.at>
Date: Thu, 5 Jan 2023 08:34:40 +0100
Subject: [PATCH] ARM: Rockchip: implement memory read out from controller

Add a driver to read out the amount of memory from the DDR controller.
The decoding of the registers has been taken from U-Boot. Currently
supported are the RK3399 and the RK3568, but decoding should work on
other Rockchip SoCs as well.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-rockchip/Makefile     |   1 +
 arch/arm/mach-rockchip/dmc.c        | 219 ++++++++++++++++++++++++++++
 include/linux/sizes.h               |   3 +
 include/mach/rockchip/dmc.h         |  86 +++++++++++
 include/mach/rockchip/rk3399-regs.h |   1 +
 include/mach/rockchip/rk3568-regs.h |   1 +
 6 files changed, 311 insertions(+)
 create mode 100644 arch/arm/mach-rockchip/dmc.c
 create mode 100644 include/mach/rockchip/dmc.h

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 2529af7c7e..f6c575854e 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_ARCH_RK3188) += rk3188.o
 obj-$(CONFIG_ARCH_RK3288) += rk3288.o
 obj-pbl-$(CONFIG_ARCH_RK3568) += rk3568.o
 obj-$(CONFIG_ARCH_ROCKCHIP_V8) += bootm.o
+obj-pbl-$(CONFIG_ARCH_ROCKCHIP_V8) += dmc.o
 obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
new file mode 100644
index 0000000000..dd60db5830
--- /dev/null
+++ b/arch/arm/mach-rockchip/dmc.c
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#define pr_fmt(fmt) "rockchip-dmc: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <asm/barebox-arm.h>
+#include <asm/memory.h>
+#include <pbl.h>
+#include <io.h>
+#include <regmap.h>
+#include <mfd/syscon.h>
+#include <mach/rockchip/dmc.h>
+#include <mach/rockchip/rk3399-regs.h>
+#include <mach/rockchip/rk3568-regs.h>
+
+#define RK3399_PMUGRF_OS_REG2		0x308
+#define RK3399_PMUGRF_OS_REG3		0x30C
+
+#define RK3568_PMUGRF_OS_REG2           0x208
+#define RK3568_PMUGRF_OS_REG3           0x20c
+
+#define RK3399_INT_REG_START		0xf0000000
+#define RK3568_INT_REG_START		RK3399_INT_REG_START
+
+struct rockchip_dmc_drvdata {
+	unsigned int os_reg2;
+	unsigned int os_reg3;
+	resource_size_t internal_registers_start;
+};
+
+static resource_size_t rockchip_sdram_size(u32 sys_reg2, u32 sys_reg3)
+{
+	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
+	resource_size_t chipsize_mb, size_mb = 0;
+	u32 ch;
+	u32 cs1_col;
+	u32 bg = 0;
+	u32 dbw, dram_type;
+	u32 ch_num = 1 + FIELD_GET(SYS_REG_NUM_CH, sys_reg2);
+	u32 version = FIELD_GET(SYS_REG_VERSION, sys_reg3);
+
+	pr_debug("%s(reg2=%x, reg3=%x)\n", __func__, sys_reg2, sys_reg3);
+
+	dram_type = FIELD_GET(SYS_REG_DDRTYPE, sys_reg2);
+
+	if (version >= 3)
+		dram_type |= FIELD_GET(SYS_REG_EXTEND_DDRTYPE, sys_reg3) << 3;
+
+	for (ch = 0; ch < ch_num; ch++) {
+		rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK);
+		cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
+		cs1_col = cs0_col;
+
+		bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
+
+		cs0_row = sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK;
+		cs1_row = sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK;
+
+		if (version >= 2) {
+			cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
+				  SYS_REG_CS1_COL_MASK);
+
+			cs0_row |= (sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
+					SYS_REG_EXTEND_CS0_ROW_MASK) << 2;
+
+			if (cs0_row == 7)
+				cs0_row = 12;
+			else
+				cs0_row += 13;
+
+			cs1_row |= (sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
+					SYS_REG_EXTEND_CS1_ROW_MASK) << 2;
+
+			if (cs1_row == 7)
+				cs1_row = 12;
+			else
+				cs1_row += 13;
+		} else {
+			cs0_row += 13;
+			cs1_row += 13;
+		}
+
+		bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & SYS_REG_BW_MASK));
+		row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK;
+
+		if (dram_type == DDR4) {
+			dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & SYS_REG_DBW_MASK;
+			bg = (dbw == 2) ? 2 : 1;
+		}
+
+		chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
+
+		if (rank > 1)
+			chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
+				       (cs0_col - cs1_col));
+		if (row_3_4)
+			chipsize_mb = chipsize_mb * 3 / 4;
+
+		size_mb += chipsize_mb;
+
+		if (rank > 1)
+			pr_debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d "
+				 "cs1_row %d bw %d row_3_4 %d\n",
+				 rank, cs0_col, cs1_col, bk, cs0_row,
+				 cs1_row, bw, row_3_4);
+		else
+			pr_debug("rank %d cs0_col %d bk %d cs0_row %d "
+				 "bw %d row_3_4 %d\n",
+				 rank, cs0_col, bk, cs0_row,
+				 bw, row_3_4);
+	}
+
+	return (resource_size_t)size_mb << 20;
+}
+
+resource_size_t rk3399_ram0_size(void)
+{
+	void __iomem *pmugrf = IOMEM(RK3399_PMUGRF_BASE);
+	u32 sys_reg2, sys_reg3;
+	resource_size_t size;
+
+	sys_reg2 = readl(pmugrf + RK3399_PMUGRF_OS_REG2);
+	sys_reg3 = readl(pmugrf + RK3399_PMUGRF_OS_REG3);
+
+	size = rockchip_sdram_size(sys_reg2, sys_reg3);
+	size = min_t(resource_size_t, RK3399_INT_REG_START, size);
+
+	pr_debug("%s() = %llu\n", __func__, (u64)size);
+
+	return size;
+}
+
+resource_size_t rk3568_ram0_size(void)
+{
+	void __iomem *pmugrf = IOMEM(RK3568_PMUGRF_BASE);
+	u32 sys_reg2, sys_reg3;
+	resource_size_t size;
+
+	sys_reg2 = readl(pmugrf + RK3568_PMUGRF_OS_REG2);
+	sys_reg3 = readl(pmugrf + RK3568_PMUGRF_OS_REG3);
+
+	size = rockchip_sdram_size(sys_reg2, sys_reg3);
+	size = min_t(resource_size_t, RK3568_INT_REG_START, size);
+
+	pr_debug("%s() = %llu\n", __func__, (u64)size);
+
+	return size;
+}
+
+static int rockchip_dmc_probe(struct device *dev)
+{
+	const struct rockchip_dmc_drvdata *drvdata;
+	resource_size_t membase, memsize;
+	struct regmap *regmap;
+	u32 sys_reg2, sys_reg3;
+
+	regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	drvdata = device_get_match_data(dev);
+	if (!drvdata)
+		return -ENOENT;
+
+	regmap_read(regmap, drvdata->os_reg2, &sys_reg2);
+	regmap_read(regmap, drvdata->os_reg3, &sys_reg3);
+
+	memsize = rockchip_sdram_size(sys_reg2, sys_reg3);
+
+	dev_info(dev, "Detected memory size: %pa\n", &memsize);
+
+	/* lowest 10M are shaved off for secure world firmware */
+	membase = 0xa00000;
+
+	/* ram0, from 0xa00000 up to SoC internal register space start */
+	arm_add_mem_device("ram0", membase,
+		min_t(resource_size_t, drvdata->internal_registers_start, memsize) - membase);
+
+	/* ram1, remaining RAM beyond 32bit space */
+	if (memsize > SZ_4G)
+		arm_add_mem_device("ram1", SZ_4G, memsize - SZ_4G);
+
+	return 0;
+}
+
+static const struct rockchip_dmc_drvdata rk3399_drvdata = {
+	.os_reg2 = RK3399_PMUGRF_OS_REG2,
+	.os_reg3 = RK3399_PMUGRF_OS_REG3,
+	.internal_registers_start = RK3399_INT_REG_START,
+};
+
+static const struct rockchip_dmc_drvdata rk3568_drvdata = {
+	.os_reg2 = RK3568_PMUGRF_OS_REG2,
+	.os_reg3 = RK3568_PMUGRF_OS_REG3,
+	.internal_registers_start = RK3568_INT_REG_START,
+};
+
+static struct of_device_id rockchip_dmc_dt_ids[] = {
+	{
+		.compatible = "rockchip,rk3399-dmc",
+		.data = &rk3399_drvdata,
+	},
+	{
+		.compatible = "rockchip,rk3568-dmc",
+		.data = &rk3568_drvdata,
+	},
+	{ /* sentinel */ }
+};
+
+static struct driver rockchip_dmc_driver = {
+	.name   = "rockchip-dmc",
+	.probe  = rockchip_dmc_probe,
+	.of_compatible = rockchip_dmc_dt_ids,
+};
+mem_platform_driver(rockchip_dmc_driver);
diff --git a/include/linux/sizes.h b/include/linux/sizes.h
index fbde0bc7e8..1d222daeab 100644
--- a/include/linux/sizes.h
+++ b/include/linux/sizes.h
@@ -47,5 +47,8 @@
 #define SZ_2G				0x80000000
 
 #define SZ_4G				_AC(0x100000000, ULL)
+#define SZ_8G				_AC(0x200000000, ULL)
+#define SZ_16G				_AC(0x400000000, ULL)
+#define SZ_32G				_AC(0x800000000, ULL)
 
 #endif /* __LINUX_SIZES_H__ */
diff --git a/include/mach/rockchip/dmc.h b/include/mach/rockchip/dmc.h
new file mode 100644
index 0000000000..ff197d50a0
--- /dev/null
+++ b/include/mach/rockchip/dmc.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _MACH_ROCKCHIP_DMC_H
+#define _MACH_ROCKCHIP_DMC_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/bitfield.h>
+
+enum {
+	DDR4 = 0,
+	DDR3 = 0x3,
+	LPDDR2 = 0x5,
+	LPDDR3 = 0x6,
+	LPDDR4 = 0x7,
+	UNUSED = 0xFF
+};
+
+/*
+ * sys_reg2 bitfield struct
+ * [31]		row_3_4_ch1
+ * [30]		row_3_4_ch0
+ * [29:28]	chinfo
+ * [27]		rank_ch1
+ * [26:25]	col_ch1
+ * [24]		bk_ch1
+ * [23:22]	low bits of cs0_row_ch1
+ * [21:20]	low bits of cs1_row_ch1
+ * [19:18]	bw_ch1
+ * [17:16]	dbw_ch1;
+ * [15:13]	ddrtype
+ * [12]		channelnum
+ * [11]		rank_ch0
+ * [10:9]	col_ch0,
+ * [8]		bk_ch0
+ * [7:6]	low bits of cs0_row_ch0
+ * [5:4]	low bits of cs1_row_ch0
+ * [3:2]	bw_ch0
+ * [1:0]	dbw_ch0
+ */
+
+#define SYS_REG_DDRTYPE			GENMASK(15, 13)
+#define SYS_REG_NUM_CH			BIT(12)
+#define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
+#define SYS_REG_ROW_3_4_MASK		1
+#define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
+#define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
+#define SYS_REG_RANK_MASK		1
+#define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
+#define SYS_REG_COL_MASK		3
+#define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
+#define SYS_REG_BK_MASK			1
+#define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
+#define SYS_REG_CS0_ROW_MASK		3
+#define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
+#define SYS_REG_CS1_ROW_MASK		3
+#define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
+#define SYS_REG_BW_MASK			3
+#define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
+#define SYS_REG_DBW_MASK		3
+
+/*
+ * sys_reg3 bitfield struct
+ * [7]		high bit of cs0_row_ch1
+ * [6]		high bit of cs1_row_ch1
+ * [5]		high bit of cs0_row_ch0
+ * [4]		high bit of cs1_row_ch0
+ * [3:2]	cs1_col_ch1
+ * [1:0]	cs1_col_ch0
+ */
+#define SYS_REG_VERSION				GENMASK(31, 28)
+#define SYS_REG_EXTEND_DDRTYPE			GENMASK(13, 12)
+#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch)	(5 + (ch) * 2)
+#define SYS_REG_EXTEND_CS0_ROW_MASK		1
+#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch)	(4 + (ch) * 2)
+#define SYS_REG_EXTEND_CS1_ROW_MASK		1
+#define SYS_REG_CS1_COL_SHIFT(ch)		(0 + (ch) * 2)
+#define SYS_REG_CS1_COL_MASK			3
+
+resource_size_t rk3399_ram0_size(void);
+resource_size_t rk3568_ram0_size(void);
+
+#endif
diff --git a/include/mach/rockchip/rk3399-regs.h b/include/mach/rockchip/rk3399-regs.h
index 57033b6510..6db082da9b 100644
--- a/include/mach/rockchip/rk3399-regs.h
+++ b/include/mach/rockchip/rk3399-regs.h
@@ -10,6 +10,7 @@
 #define RK3399_UART3_BASE	0xff1b0000
 #define RK3399_UART4_BASE	0xff370000
 
+#define RK3399_PMUGRF_BASE	0xff320000
 #define RK3399_IRAM_BASE	0xff8c0000
 #define RK3399_STIMER_BASE	0xff8680a0
 
diff --git a/include/mach/rockchip/rk3568-regs.h b/include/mach/rockchip/rk3568-regs.h
index edd5ee268d..55d28790dd 100644
--- a/include/mach/rockchip/rk3568-regs.h
+++ b/include/mach/rockchip/rk3568-regs.h
@@ -16,5 +16,6 @@
 #define RK3568_UART9_BASE	0xfe6d0000
 
 #define RK3568_IRAM_BASE	0xfdcc0000
+#define RK3568_PMUGRF_BASE	0xfdc20000
 
 #endif /* __MACH_RK3568_REGS_H */
-- 
2.39.2

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller
  2023-04-03 19:43   ` Sascha Hauer
@ 2023-04-04  6:25     ` Michael Riesch
  0 siblings, 0 replies; 14+ messages in thread
From: Michael Riesch @ 2023-04-04  6:25 UTC (permalink / raw)
  To: Sascha Hauer, Barebox List; +Cc: Ahmad Fatoum

Hi Sascha,

On 4/3/23 21:43, Sascha Hauer wrote:
> On Tue, Mar 28, 2023 at 09:40:33AM +0200, Sascha Hauer wrote:
>> From: Ahmad Fatoum <ahmad@a3f.at>
>>
>> Add a driver to read out the amount of memory from the DDR controller.
>> The decoding of the registers has been taken from U-Boot. Currently
>> supported are the RK3399 and the RK3568, but decoding should work on
>> other Rockchip SoCs as well.
>>
> 
> This patch needs an update. The RAM is divided into two parts, one below
> the SoC internal register space and one starting at 4GiB up to the end.
> The previous version assumed that the RAM address decoding skips
> the internal register space, but it seems the internal register space
> shadows the RAM behind it, so a board with 8GiB of memory has the
> last address on 0x200000000-1 instead of 0x210000000-1 like the previous
> version assumed.
> 
> ----------------------------------8<----------------------------

With this version of the patch Linux boots normally on my ROCK3A 8GB.
Thanks a lot!

Best regards,
Michael

> 
> From bc9baa7ac71c4a8e75d000317d85d6bf6a85a8e4 Mon Sep 17 00:00:00 2001
> From: Ahmad Fatoum <ahmad@a3f.at>
> Date: Thu, 5 Jan 2023 08:34:40 +0100
> Subject: [PATCH] ARM: Rockchip: implement memory read out from controller
> 
> Add a driver to read out the amount of memory from the DDR controller.
> The decoding of the registers has been taken from U-Boot. Currently
> supported are the RK3399 and the RK3568, but decoding should work on
> other Rockchip SoCs as well.
> 
> Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/mach-rockchip/Makefile     |   1 +
>  arch/arm/mach-rockchip/dmc.c        | 219 ++++++++++++++++++++++++++++
>  include/linux/sizes.h               |   3 +
>  include/mach/rockchip/dmc.h         |  86 +++++++++++
>  include/mach/rockchip/rk3399-regs.h |   1 +
>  include/mach/rockchip/rk3568-regs.h |   1 +
>  6 files changed, 311 insertions(+)
>  create mode 100644 arch/arm/mach-rockchip/dmc.c
>  create mode 100644 include/mach/rockchip/dmc.h
> 
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 2529af7c7e..f6c575854e 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -6,4 +6,5 @@ obj-$(CONFIG_ARCH_RK3188) += rk3188.o
>  obj-$(CONFIG_ARCH_RK3288) += rk3288.o
>  obj-pbl-$(CONFIG_ARCH_RK3568) += rk3568.o
>  obj-$(CONFIG_ARCH_ROCKCHIP_V8) += bootm.o
> +obj-pbl-$(CONFIG_ARCH_ROCKCHIP_V8) += dmc.o
>  obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o
> diff --git a/arch/arm/mach-rockchip/dmc.c b/arch/arm/mach-rockchip/dmc.c
> new file mode 100644
> index 0000000000..dd60db5830
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/dmc.c
> @@ -0,0 +1,219 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + */
> +
> +#define pr_fmt(fmt) "rockchip-dmc: " fmt
> +
> +#include <common.h>
> +#include <init.h>
> +#include <asm/barebox-arm.h>
> +#include <asm/memory.h>
> +#include <pbl.h>
> +#include <io.h>
> +#include <regmap.h>
> +#include <mfd/syscon.h>
> +#include <mach/rockchip/dmc.h>
> +#include <mach/rockchip/rk3399-regs.h>
> +#include <mach/rockchip/rk3568-regs.h>
> +
> +#define RK3399_PMUGRF_OS_REG2		0x308
> +#define RK3399_PMUGRF_OS_REG3		0x30C
> +
> +#define RK3568_PMUGRF_OS_REG2           0x208
> +#define RK3568_PMUGRF_OS_REG3           0x20c
> +
> +#define RK3399_INT_REG_START		0xf0000000
> +#define RK3568_INT_REG_START		RK3399_INT_REG_START
> +
> +struct rockchip_dmc_drvdata {
> +	unsigned int os_reg2;
> +	unsigned int os_reg3;
> +	resource_size_t internal_registers_start;
> +};
> +
> +static resource_size_t rockchip_sdram_size(u32 sys_reg2, u32 sys_reg3)
> +{
> +	u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
> +	resource_size_t chipsize_mb, size_mb = 0;
> +	u32 ch;
> +	u32 cs1_col;
> +	u32 bg = 0;
> +	u32 dbw, dram_type;
> +	u32 ch_num = 1 + FIELD_GET(SYS_REG_NUM_CH, sys_reg2);
> +	u32 version = FIELD_GET(SYS_REG_VERSION, sys_reg3);
> +
> +	pr_debug("%s(reg2=%x, reg3=%x)\n", __func__, sys_reg2, sys_reg3);
> +
> +	dram_type = FIELD_GET(SYS_REG_DDRTYPE, sys_reg2);
> +
> +	if (version >= 3)
> +		dram_type |= FIELD_GET(SYS_REG_EXTEND_DDRTYPE, sys_reg3) << 3;
> +
> +	for (ch = 0; ch < ch_num; ch++) {
> +		rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK);
> +		cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
> +		cs1_col = cs0_col;
> +
> +		bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
> +
> +		cs0_row = sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK;
> +		cs1_row = sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK;
> +
> +		if (version >= 2) {
> +			cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
> +				  SYS_REG_CS1_COL_MASK);
> +
> +			cs0_row |= (sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
> +					SYS_REG_EXTEND_CS0_ROW_MASK) << 2;
> +
> +			if (cs0_row == 7)
> +				cs0_row = 12;
> +			else
> +				cs0_row += 13;
> +
> +			cs1_row |= (sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
> +					SYS_REG_EXTEND_CS1_ROW_MASK) << 2;
> +
> +			if (cs1_row == 7)
> +				cs1_row = 12;
> +			else
> +				cs1_row += 13;
> +		} else {
> +			cs0_row += 13;
> +			cs1_row += 13;
> +		}
> +
> +		bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) & SYS_REG_BW_MASK));
> +		row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK;
> +
> +		if (dram_type == DDR4) {
> +			dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & SYS_REG_DBW_MASK;
> +			bg = (dbw == 2) ? 2 : 1;
> +		}
> +
> +		chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
> +
> +		if (rank > 1)
> +			chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
> +				       (cs0_col - cs1_col));
> +		if (row_3_4)
> +			chipsize_mb = chipsize_mb * 3 / 4;
> +
> +		size_mb += chipsize_mb;
> +
> +		if (rank > 1)
> +			pr_debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d "
> +				 "cs1_row %d bw %d row_3_4 %d\n",
> +				 rank, cs0_col, cs1_col, bk, cs0_row,
> +				 cs1_row, bw, row_3_4);
> +		else
> +			pr_debug("rank %d cs0_col %d bk %d cs0_row %d "
> +				 "bw %d row_3_4 %d\n",
> +				 rank, cs0_col, bk, cs0_row,
> +				 bw, row_3_4);
> +	}
> +
> +	return (resource_size_t)size_mb << 20;
> +}
> +
> +resource_size_t rk3399_ram0_size(void)
> +{
> +	void __iomem *pmugrf = IOMEM(RK3399_PMUGRF_BASE);
> +	u32 sys_reg2, sys_reg3;
> +	resource_size_t size;
> +
> +	sys_reg2 = readl(pmugrf + RK3399_PMUGRF_OS_REG2);
> +	sys_reg3 = readl(pmugrf + RK3399_PMUGRF_OS_REG3);
> +
> +	size = rockchip_sdram_size(sys_reg2, sys_reg3);
> +	size = min_t(resource_size_t, RK3399_INT_REG_START, size);
> +
> +	pr_debug("%s() = %llu\n", __func__, (u64)size);
> +
> +	return size;
> +}
> +
> +resource_size_t rk3568_ram0_size(void)
> +{
> +	void __iomem *pmugrf = IOMEM(RK3568_PMUGRF_BASE);
> +	u32 sys_reg2, sys_reg3;
> +	resource_size_t size;
> +
> +	sys_reg2 = readl(pmugrf + RK3568_PMUGRF_OS_REG2);
> +	sys_reg3 = readl(pmugrf + RK3568_PMUGRF_OS_REG3);
> +
> +	size = rockchip_sdram_size(sys_reg2, sys_reg3);
> +	size = min_t(resource_size_t, RK3568_INT_REG_START, size);
> +
> +	pr_debug("%s() = %llu\n", __func__, (u64)size);
> +
> +	return size;
> +}
> +
> +static int rockchip_dmc_probe(struct device *dev)
> +{
> +	const struct rockchip_dmc_drvdata *drvdata;
> +	resource_size_t membase, memsize;
> +	struct regmap *regmap;
> +	u32 sys_reg2, sys_reg3;
> +
> +	regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
> +	if (IS_ERR(regmap))
> +		return PTR_ERR(regmap);
> +
> +	drvdata = device_get_match_data(dev);
> +	if (!drvdata)
> +		return -ENOENT;
> +
> +	regmap_read(regmap, drvdata->os_reg2, &sys_reg2);
> +	regmap_read(regmap, drvdata->os_reg3, &sys_reg3);
> +
> +	memsize = rockchip_sdram_size(sys_reg2, sys_reg3);
> +
> +	dev_info(dev, "Detected memory size: %pa\n", &memsize);
> +
> +	/* lowest 10M are shaved off for secure world firmware */
> +	membase = 0xa00000;
> +
> +	/* ram0, from 0xa00000 up to SoC internal register space start */
> +	arm_add_mem_device("ram0", membase,
> +		min_t(resource_size_t, drvdata->internal_registers_start, memsize) - membase);
> +
> +	/* ram1, remaining RAM beyond 32bit space */
> +	if (memsize > SZ_4G)
> +		arm_add_mem_device("ram1", SZ_4G, memsize - SZ_4G);
> +
> +	return 0;
> +}
> +
> +static const struct rockchip_dmc_drvdata rk3399_drvdata = {
> +	.os_reg2 = RK3399_PMUGRF_OS_REG2,
> +	.os_reg3 = RK3399_PMUGRF_OS_REG3,
> +	.internal_registers_start = RK3399_INT_REG_START,
> +};
> +
> +static const struct rockchip_dmc_drvdata rk3568_drvdata = {
> +	.os_reg2 = RK3568_PMUGRF_OS_REG2,
> +	.os_reg3 = RK3568_PMUGRF_OS_REG3,
> +	.internal_registers_start = RK3568_INT_REG_START,
> +};
> +
> +static struct of_device_id rockchip_dmc_dt_ids[] = {
> +	{
> +		.compatible = "rockchip,rk3399-dmc",
> +		.data = &rk3399_drvdata,
> +	},
> +	{
> +		.compatible = "rockchip,rk3568-dmc",
> +		.data = &rk3568_drvdata,
> +	},
> +	{ /* sentinel */ }
> +};
> +
> +static struct driver rockchip_dmc_driver = {
> +	.name   = "rockchip-dmc",
> +	.probe  = rockchip_dmc_probe,
> +	.of_compatible = rockchip_dmc_dt_ids,
> +};
> +mem_platform_driver(rockchip_dmc_driver);
> diff --git a/include/linux/sizes.h b/include/linux/sizes.h
> index fbde0bc7e8..1d222daeab 100644
> --- a/include/linux/sizes.h
> +++ b/include/linux/sizes.h
> @@ -47,5 +47,8 @@
>  #define SZ_2G				0x80000000
>  
>  #define SZ_4G				_AC(0x100000000, ULL)
> +#define SZ_8G				_AC(0x200000000, ULL)
> +#define SZ_16G				_AC(0x400000000, ULL)
> +#define SZ_32G				_AC(0x800000000, ULL)
>  
>  #endif /* __LINUX_SIZES_H__ */
> diff --git a/include/mach/rockchip/dmc.h b/include/mach/rockchip/dmc.h
> new file mode 100644
> index 0000000000..ff197d50a0
> --- /dev/null
> +++ b/include/mach/rockchip/dmc.h
> @@ -0,0 +1,86 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
> + */
> +
> +#ifndef _MACH_ROCKCHIP_DMC_H
> +#define _MACH_ROCKCHIP_DMC_H
> +
> +#include <linux/compiler.h>
> +#include <linux/types.h>
> +#include <linux/bitfield.h>
> +
> +enum {
> +	DDR4 = 0,
> +	DDR3 = 0x3,
> +	LPDDR2 = 0x5,
> +	LPDDR3 = 0x6,
> +	LPDDR4 = 0x7,
> +	UNUSED = 0xFF
> +};
> +
> +/*
> + * sys_reg2 bitfield struct
> + * [31]		row_3_4_ch1
> + * [30]		row_3_4_ch0
> + * [29:28]	chinfo
> + * [27]		rank_ch1
> + * [26:25]	col_ch1
> + * [24]		bk_ch1
> + * [23:22]	low bits of cs0_row_ch1
> + * [21:20]	low bits of cs1_row_ch1
> + * [19:18]	bw_ch1
> + * [17:16]	dbw_ch1;
> + * [15:13]	ddrtype
> + * [12]		channelnum
> + * [11]		rank_ch0
> + * [10:9]	col_ch0,
> + * [8]		bk_ch0
> + * [7:6]	low bits of cs0_row_ch0
> + * [5:4]	low bits of cs1_row_ch0
> + * [3:2]	bw_ch0
> + * [1:0]	dbw_ch0
> + */
> +
> +#define SYS_REG_DDRTYPE			GENMASK(15, 13)
> +#define SYS_REG_NUM_CH			BIT(12)
> +#define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
> +#define SYS_REG_ROW_3_4_MASK		1
> +#define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
> +#define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
> +#define SYS_REG_RANK_MASK		1
> +#define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
> +#define SYS_REG_COL_MASK		3
> +#define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
> +#define SYS_REG_BK_MASK			1
> +#define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
> +#define SYS_REG_CS0_ROW_MASK		3
> +#define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
> +#define SYS_REG_CS1_ROW_MASK		3
> +#define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
> +#define SYS_REG_BW_MASK			3
> +#define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
> +#define SYS_REG_DBW_MASK		3
> +
> +/*
> + * sys_reg3 bitfield struct
> + * [7]		high bit of cs0_row_ch1
> + * [6]		high bit of cs1_row_ch1
> + * [5]		high bit of cs0_row_ch0
> + * [4]		high bit of cs1_row_ch0
> + * [3:2]	cs1_col_ch1
> + * [1:0]	cs1_col_ch0
> + */
> +#define SYS_REG_VERSION				GENMASK(31, 28)
> +#define SYS_REG_EXTEND_DDRTYPE			GENMASK(13, 12)
> +#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch)	(5 + (ch) * 2)
> +#define SYS_REG_EXTEND_CS0_ROW_MASK		1
> +#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch)	(4 + (ch) * 2)
> +#define SYS_REG_EXTEND_CS1_ROW_MASK		1
> +#define SYS_REG_CS1_COL_SHIFT(ch)		(0 + (ch) * 2)
> +#define SYS_REG_CS1_COL_MASK			3
> +
> +resource_size_t rk3399_ram0_size(void);
> +resource_size_t rk3568_ram0_size(void);
> +
> +#endif
> diff --git a/include/mach/rockchip/rk3399-regs.h b/include/mach/rockchip/rk3399-regs.h
> index 57033b6510..6db082da9b 100644
> --- a/include/mach/rockchip/rk3399-regs.h
> +++ b/include/mach/rockchip/rk3399-regs.h
> @@ -10,6 +10,7 @@
>  #define RK3399_UART3_BASE	0xff1b0000
>  #define RK3399_UART4_BASE	0xff370000
>  
> +#define RK3399_PMUGRF_BASE	0xff320000
>  #define RK3399_IRAM_BASE	0xff8c0000
>  #define RK3399_STIMER_BASE	0xff8680a0
>  
> diff --git a/include/mach/rockchip/rk3568-regs.h b/include/mach/rockchip/rk3568-regs.h
> index edd5ee268d..55d28790dd 100644
> --- a/include/mach/rockchip/rk3568-regs.h
> +++ b/include/mach/rockchip/rk3568-regs.h
> @@ -16,5 +16,6 @@
>  #define RK3568_UART9_BASE	0xfe6d0000
>  
>  #define RK3568_IRAM_BASE	0xfdcc0000
> +#define RK3568_PMUGRF_BASE	0xfdc20000
>  
>  #endif /* __MACH_RK3568_REGS_H */



^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v2 4/6] ARM: Rockchip: rk3568: use rk3568_barebox_entry()
  2023-03-28  7:40 ` [PATCH v2 4/6] ARM: Rockchip: rk3568: use rk3568_barebox_entry() Sascha Hauer
@ 2023-04-05  6:48   ` Sascha Hauer
  0 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2023-04-05  6:48 UTC (permalink / raw)
  To: Barebox List

On Tue, Mar 28, 2023 at 09:40:35AM +0200, Sascha Hauer wrote:
> There is a rk3568 specific entry function for barebox now, switch
> the existing boards over to use it.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/boards/pine64-quartz64/lowlevel.c    | 30 +++--------------
>  arch/arm/boards/radxa-rock3/lowlevel.c        | 31 +++---------------
>  .../rockchip-rk3568-bpi-r2pro/lowlevel.c      | 31 +++---------------
>  .../arm/boards/rockchip-rk3568-evb/lowlevel.c | 32 +++----------------
>  4 files changed, 17 insertions(+), 107 deletions(-)
> 
> diff --git a/arch/arm/boards/pine64-quartz64/lowlevel.c b/arch/arm/boards/pine64-quartz64/lowlevel.c
> index 1e63c0e698..975f8aa51c 100644
> --- a/arch/arm/boards/pine64-quartz64/lowlevel.c
> +++ b/arch/arm/boards/pine64-quartz64/lowlevel.c
> @@ -1,41 +1,19 @@
>  // SPDX-License-Identifier: GPL-2.0-only
> +
>  #include <common.h>
> -#include <linux/sizes.h>
> -#include <asm/barebox-arm-head.h>
>  #include <asm/barebox-arm.h>
>  #include <mach/rockchip/hardware.h>
>  #include <mach/rockchip/atf.h>
>  #include <debug_ll.h>
> -#include <mach/rockchip/rockchip.h>
>  
>  extern char __dtb_rk3566_quartz64_a_start[];
>  
> -static noinline void start_quartz64(void)
> -{
> -	void *fdt = __dtb_rk3566_quartz64_a_start;
> -
> -	if (current_el() == 3) {
> -		rk3568_lowlevel_init();
> -		rk3568_atf_load_bl31(fdt);
> -		/* not reached */
> -	}
> -
> -	barebox_arm_entry(RK3568_DRAM_BOTTOM, 0x80000000 - RK3568_DRAM_BOTTOM,
> -			  fdt);
> -}
> -
>  ENTRY_FUNCTION(start_quartz64a, r0, r1, r2)
>  {
> -	/*
> -	 * Image execution starts at 0x0, but this is used for ATF and
> -	 * OP-TEE later, so move away from here.
> -	 */
> -	if (current_el() == 3)
> -		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
> -	else
> -		relocate_to_current_adr();
> +	putc_ll('>');
>  
> +	relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);

This doesn't work when barebox is started from another barebox, because
it places the new barebox at an address near
RK3568_BAREBOX_LOAD_ADDRESS. Calling relocate_to_adr_full() will
partly overwrite the image. I'll revert this change to what has been
done before:

	if (current_el() == 3)
		relocate_to_adr_full(RK3568_BAREBOX_LOAD_ADDRESS);
	else
		relocate_to_current_adr();

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2023-04-05  6:50 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-28  7:40 [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 1/6] ARM: dts: rk356x: Add DMC controller node Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 2/6] ARM: Rockchip: implement memory read out from controller Sascha Hauer
2023-03-28  8:18   ` Sascha Hauer
2023-04-03 19:43   ` Sascha Hauer
2023-04-04  6:25     ` Michael Riesch
2023-03-28  7:40 ` [PATCH v2 3/6] ARM: Rockchip: Add rk3568 specific barebox entry function Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 4/6] ARM: Rockchip: rk3568: use rk3568_barebox_entry() Sascha Hauer
2023-04-05  6:48   ` Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 5/6] ARM: Rockchip: make bootsource logic generic to all SoCs Sascha Hauer
2023-03-28  7:40 ` [PATCH v2 6/6] ARM: Rockchip: Do not pass device tree to TF-A Sascha Hauer
2023-03-31 15:42 ` [PATCH v2 0/6] ARM: Rockchip: Read amount of memory from DDR controller Michael Riesch
2023-04-03  7:32   ` Sascha Hauer
2023-04-03 10:04     ` Michael Riesch

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox