* [PATCH v2 1/4] spi: add per-driver bits-per-word mask
@ 2023-04-03 11:53 Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 2/4] spi: stm32: support per-transfer bits per word switching Philipp Zabel
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Philipp Zabel @ 2023-04-03 11:53 UTC (permalink / raw)
To: barebox
Allow SPI hosts to signal per-transfer bits-per-word switching
support and drivers to query it with spi_is_bpw_supported().
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
include/spi/spi.h | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/include/spi/spi.h b/include/spi/spi.h
index fa9329b08c80..809ebd8df1a8 100644
--- a/include/spi/spi.h
+++ b/include/spi/spi.h
@@ -131,6 +131,11 @@ struct spi_message;
* SPI slaves, and are numbered from zero to num_chipselects.
* each slave has a chipselect signal, but it's common that not
* every chipselect is connected to a slave.
+ * @bits_per_word_mask: A mask indicating which values of bits_per_word are
+ * supported by the driver. Bit n indicates that a bits_per_word n+1 is
+ * supported. If set, the SPI core will reject any transfer with an
+ * unsupported bits_per_word. If not set, this value is simply ignored,
+ * and it's up to the individual driver to perform any validation.
* @max_speed_hz: Highest supported transfer speed
* @setup: updates the device mode and clocking records used by a
* device's SPI controller; protocol code may call this. This
@@ -165,6 +170,12 @@ struct spi_controller {
/* Optimized handlers for SPI memory-like operations */
const struct spi_controller_mem_ops *mem_ops;
+
+ /* Bitmask of supported bits_per_word for transfers */
+ u32 bits_per_word_mask;
+#define SPI_BPW_MASK(bits) BIT((bits) - 1)
+#define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
+
/*
* on some hardware transfer size may be constrained
* the limit may depend on device transfer settings
@@ -435,6 +446,26 @@ spi_transfer_del(struct spi_transfer *t)
list_del(&t->transfer_list);
}
+/**
+ * spi_is_bpw_supported - Check if bits per word is supported
+ * @spi: SPI device
+ * @bpw: Bits per word
+ *
+ * This function checks to see if the SPI controller supports @bpw.
+ *
+ * Returns:
+ * True if @bpw is supported, false otherwise.
+ */
+static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw)
+{
+ u32 bpw_mask = spi->master->bits_per_word_mask;
+
+ if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw)))
+ return true;
+
+ return false;
+}
+
/* All these synchronous SPI transfer routines are utilities layered
* over the core async transfer primitive. Here, "synchronous" means
* they will sleep uninterruptibly until the async transfer completes.
--
2.39.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/4] spi: stm32: support per-transfer bits per word switching
2023-04-03 11:53 [PATCH v2 1/4] spi: add per-driver bits-per-word mask Philipp Zabel
@ 2023-04-03 11:53 ` Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 3/4] video: mipi_dbi: disable byte swapping if 16-bit SPI transfers are supported Philipp Zabel
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Philipp Zabel @ 2023-04-03 11:53 UTC (permalink / raw)
To: barebox
Allow dynamically switching data size between transfers.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
v2: query max bits-per-word after clk_enable() and device_reset()
---
drivers/spi/stm32_spi.c | 50 ++++++++++++++++++++++++++++++++---------
1 file changed, 39 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c
index 0d7407c279a2..bdaeb6b5d0e5 100644
--- a/drivers/spi/stm32_spi.c
+++ b/drivers/spi/stm32_spi.c
@@ -111,6 +111,24 @@ static inline struct stm32_spi_priv *to_stm32_spi_priv(struct spi_master *master
return container_of(master, struct stm32_spi_priv, master);
}
+static int stm32_spi_get_bpw_mask(struct stm32_spi_priv *priv)
+{
+ u32 cfg1, max_bpw;
+
+ /*
+ * The most significant bit at DSIZE bit field is reserved when the
+ * maximum data size of periperal instances is limited to 16-bit
+ */
+ setbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE);
+
+ cfg1 = readl(priv->base + STM32_SPI_CFG1);
+ max_bpw = FIELD_GET(SPI_CFG1_DSIZE, cfg1) + 1;
+
+ dev_dbg(priv->master.dev, "%d-bit maximum data frame\n", max_bpw);
+
+ return SPI_BPW_RANGE_MASK(4, max_bpw);
+}
+
static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
{
while ((priv->tx_len > 0) &&
@@ -261,19 +279,15 @@ static void stm32_spi_set_mode(struct stm32_spi_priv *priv, unsigned mode)
static void stm32_spi_set_fthlv(struct stm32_spi_priv *priv, u32 xfer_len)
{
- u32 fthlv, half_fifo;
+ u32 fthlv, packet, bpw;
/* data packet should not exceed 1/2 of fifo space */
- half_fifo = (priv->fifo_size / 2);
-
- /* data_packet should not exceed transfer length */
- fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
+ packet = clamp(xfer_len, 1U, priv->fifo_size / 2);
/* align packet size with data registers access */
- fthlv -= (fthlv % 4);
+ bpw = DIV_ROUND_UP(priv->cur_bpw, 8);
+ fthlv = DIV_ROUND_UP(packet, bpw);
- if (!fthlv)
- fthlv = 1;
clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
(fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
}
@@ -344,9 +358,17 @@ static int stm32_spi_transfer_one(struct stm32_spi_priv *priv,
u32 ifcr = 0;
u32 mode;
int xfer_status = 0;
+ int nb_words;
- if (t->len <= SPI_CR2_TSIZE)
- writel(t->len, priv->base + STM32_SPI_CR2);
+ if (t->bits_per_word <= 8)
+ nb_words = t->len;
+ else if (t->bits_per_word <= 16)
+ nb_words = DIV_ROUND_UP(t->len * 8, 16);
+ else
+ nb_words = DIV_ROUND_UP(t->len * 8, 32);
+
+ if (nb_words <= SPI_CR2_TSIZE)
+ writel(nb_words, priv->base + STM32_SPI_CR2);
else
return -EMSGSIZE;
@@ -361,9 +383,11 @@ static int stm32_spi_transfer_one(struct stm32_spi_priv *priv,
else if (!priv->rx_buf)
mode = SPI_SIMPLEX_TX;
- if (priv->cur_xferlen != t->len || priv->cur_mode != mode) {
+ if (priv->cur_xferlen != t->len || priv->cur_mode != mode ||
+ priv->cur_bpw != t->bits_per_word) {
priv->cur_mode = mode;
priv->cur_xferlen = t->len;
+ priv->cur_bpw = t->bits_per_word;
/* Disable the SPI hardware to unlock CFG1/CFG2 registers */
stm32_spi_disable(priv);
@@ -373,6 +397,9 @@ static int stm32_spi_transfer_one(struct stm32_spi_priv *priv,
stm32_spi_set_fthlv(priv, t->len);
+ clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
+ priv->cur_bpw - 1);
+
/* Enable the SPI hardware */
stm32_spi_enable(priv);
}
@@ -560,6 +587,7 @@ static int stm32_spi_probe(struct device *dev)
if (ret)
return ret;
+ master->bits_per_word_mask = stm32_spi_get_bpw_mask(priv);
priv->fifo_size = stm32_spi_get_fifo_size(priv);
priv->cur_mode = SPI_FULL_DUPLEX;
--
2.39.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 3/4] video: mipi_dbi: disable byte swapping if 16-bit SPI transfers are supported
2023-04-03 11:53 [PATCH v2 1/4] spi: add per-driver bits-per-word mask Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 2/4] spi: stm32: support per-transfer bits per word switching Philipp Zabel
@ 2023-04-03 11:53 ` Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 4/4] spi: update spi_board_info FIXME comment Philipp Zabel
2023-04-04 7:04 ` [PATCH v2 1/4] spi: add per-driver bits-per-word mask Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Philipp Zabel @ 2023-04-03 11:53 UTC (permalink / raw)
To: barebox
If the SPI controller supports switching to 16-bit transfers, there
is no need to swap bytes on little-endian architectures. This also
allows to transfer directly from the 16-bit framebuffer.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
drivers/video/mipi_dbi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/video/mipi_dbi.c b/drivers/video/mipi_dbi.c
index 61b0fbcc49c6..aab6b1243954 100644
--- a/drivers/video/mipi_dbi.c
+++ b/drivers/video/mipi_dbi.c
@@ -632,8 +632,7 @@ int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
dbi->command = mipi_dbi_typec3_command;
dbi->dc = dc;
- // TODO: can we just force 16 bit?
- if (mipi_dbi_machine_little_endian() && spi->bits_per_word != 16)
+ if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
dbi->swap_bytes = true;
dev_dbg(dev, "SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
--
2.39.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 4/4] spi: update spi_board_info FIXME comment
2023-04-03 11:53 [PATCH v2 1/4] spi: add per-driver bits-per-word mask Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 2/4] spi: stm32: support per-transfer bits per word switching Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 3/4] video: mipi_dbi: disable byte swapping if 16-bit SPI transfers are supported Philipp Zabel
@ 2023-04-03 11:53 ` Philipp Zabel
2023-04-04 7:04 ` [PATCH v2 1/4] spi: add per-driver bits-per-word mask Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Philipp Zabel @ 2023-04-03 11:53 UTC (permalink / raw)
To: barebox
The spi-stm32 driver now supports the spi_transfer.bits_per_word
override.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
include/spi/spi.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/spi/spi.h b/include/spi/spi.h
index 809ebd8df1a8..d479e4f34f0c 100644
--- a/include/spi/spi.h
+++ b/include/spi/spi.h
@@ -44,7 +44,7 @@ struct spi_board_info {
* This may be changed by the device's driver, or left at the
* default (0) indicating protocol words are eight bit bytes.
* The spi_transfer.bits_per_word can override this for each transfer
- * (FIXME: not currently implemented).
+ * (FIXME: not currently implemented by most drivers).
* @irq: Negative, or the number passed to request_irq() to receive
* interrupts from this device.
* @controller_state: Controller's runtime state
--
2.39.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/4] spi: add per-driver bits-per-word mask
2023-04-03 11:53 [PATCH v2 1/4] spi: add per-driver bits-per-word mask Philipp Zabel
` (2 preceding siblings ...)
2023-04-03 11:53 ` [PATCH v2 4/4] spi: update spi_board_info FIXME comment Philipp Zabel
@ 2023-04-04 7:04 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2023-04-04 7:04 UTC (permalink / raw)
To: Philipp Zabel; +Cc: barebox
On Mon, Apr 03, 2023 at 01:53:37PM +0200, Philipp Zabel wrote:
> Allow SPI hosts to signal per-transfer bits-per-word switching
> support and drivers to query it with spi_is_bpw_supported().
>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
> include/spi/spi.h | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
Applied, thanks
Sascha
>
> diff --git a/include/spi/spi.h b/include/spi/spi.h
> index fa9329b08c80..809ebd8df1a8 100644
> --- a/include/spi/spi.h
> +++ b/include/spi/spi.h
> @@ -131,6 +131,11 @@ struct spi_message;
> * SPI slaves, and are numbered from zero to num_chipselects.
> * each slave has a chipselect signal, but it's common that not
> * every chipselect is connected to a slave.
> + * @bits_per_word_mask: A mask indicating which values of bits_per_word are
> + * supported by the driver. Bit n indicates that a bits_per_word n+1 is
> + * supported. If set, the SPI core will reject any transfer with an
> + * unsupported bits_per_word. If not set, this value is simply ignored,
> + * and it's up to the individual driver to perform any validation.
> * @max_speed_hz: Highest supported transfer speed
> * @setup: updates the device mode and clocking records used by a
> * device's SPI controller; protocol code may call this. This
> @@ -165,6 +170,12 @@ struct spi_controller {
>
> /* Optimized handlers for SPI memory-like operations */
> const struct spi_controller_mem_ops *mem_ops;
> +
> + /* Bitmask of supported bits_per_word for transfers */
> + u32 bits_per_word_mask;
> +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
> +#define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
> +
> /*
> * on some hardware transfer size may be constrained
> * the limit may depend on device transfer settings
> @@ -435,6 +446,26 @@ spi_transfer_del(struct spi_transfer *t)
> list_del(&t->transfer_list);
> }
>
> +/**
> + * spi_is_bpw_supported - Check if bits per word is supported
> + * @spi: SPI device
> + * @bpw: Bits per word
> + *
> + * This function checks to see if the SPI controller supports @bpw.
> + *
> + * Returns:
> + * True if @bpw is supported, false otherwise.
> + */
> +static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw)
> +{
> + u32 bpw_mask = spi->master->bits_per_word_mask;
> +
> + if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw)))
> + return true;
> +
> + return false;
> +}
> +
> /* All these synchronous SPI transfer routines are utilities layered
> * over the core async transfer primitive. Here, "synchronous" means
> * they will sleep uninterruptibly until the async transfer completes.
> --
> 2.39.2
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-04-04 7:06 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-03 11:53 [PATCH v2 1/4] spi: add per-driver bits-per-word mask Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 2/4] spi: stm32: support per-transfer bits per word switching Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 3/4] video: mipi_dbi: disable byte swapping if 16-bit SPI transfers are supported Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 4/4] spi: update spi_board_info FIXME comment Philipp Zabel
2023-04-04 7:04 ` [PATCH v2 1/4] spi: add per-driver bits-per-word mask Sascha Hauer
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox