From: Sascha Hauer <sha@pengutronix.de>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: barebox@lists.infradead.org
Subject: Re: [PATCH v2 1/4] spi: add per-driver bits-per-word mask
Date: Tue, 4 Apr 2023 09:04:54 +0200 [thread overview]
Message-ID: <20230404070454.GU19113@pengutronix.de> (raw)
In-Reply-To: <20230403115340.3416720-1-p.zabel@pengutronix.de>
On Mon, Apr 03, 2023 at 01:53:37PM +0200, Philipp Zabel wrote:
> Allow SPI hosts to signal per-transfer bits-per-word switching
> support and drivers to query it with spi_is_bpw_supported().
>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
> include/spi/spi.h | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
Applied, thanks
Sascha
>
> diff --git a/include/spi/spi.h b/include/spi/spi.h
> index fa9329b08c80..809ebd8df1a8 100644
> --- a/include/spi/spi.h
> +++ b/include/spi/spi.h
> @@ -131,6 +131,11 @@ struct spi_message;
> * SPI slaves, and are numbered from zero to num_chipselects.
> * each slave has a chipselect signal, but it's common that not
> * every chipselect is connected to a slave.
> + * @bits_per_word_mask: A mask indicating which values of bits_per_word are
> + * supported by the driver. Bit n indicates that a bits_per_word n+1 is
> + * supported. If set, the SPI core will reject any transfer with an
> + * unsupported bits_per_word. If not set, this value is simply ignored,
> + * and it's up to the individual driver to perform any validation.
> * @max_speed_hz: Highest supported transfer speed
> * @setup: updates the device mode and clocking records used by a
> * device's SPI controller; protocol code may call this. This
> @@ -165,6 +170,12 @@ struct spi_controller {
>
> /* Optimized handlers for SPI memory-like operations */
> const struct spi_controller_mem_ops *mem_ops;
> +
> + /* Bitmask of supported bits_per_word for transfers */
> + u32 bits_per_word_mask;
> +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
> +#define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
> +
> /*
> * on some hardware transfer size may be constrained
> * the limit may depend on device transfer settings
> @@ -435,6 +446,26 @@ spi_transfer_del(struct spi_transfer *t)
> list_del(&t->transfer_list);
> }
>
> +/**
> + * spi_is_bpw_supported - Check if bits per word is supported
> + * @spi: SPI device
> + * @bpw: Bits per word
> + *
> + * This function checks to see if the SPI controller supports @bpw.
> + *
> + * Returns:
> + * True if @bpw is supported, false otherwise.
> + */
> +static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw)
> +{
> + u32 bpw_mask = spi->master->bits_per_word_mask;
> +
> + if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw)))
> + return true;
> +
> + return false;
> +}
> +
> /* All these synchronous SPI transfer routines are utilities layered
> * over the core async transfer primitive. Here, "synchronous" means
> * they will sleep uninterruptibly until the async transfer completes.
> --
> 2.39.2
>
>
>
--
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prev parent reply other threads:[~2023-04-04 7:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-03 11:53 Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 2/4] spi: stm32: support per-transfer bits per word switching Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 3/4] video: mipi_dbi: disable byte swapping if 16-bit SPI transfers are supported Philipp Zabel
2023-04-03 11:53 ` [PATCH v2 4/4] spi: update spi_board_info FIXME comment Philipp Zabel
2023-04-04 7:04 ` Sascha Hauer [this message]
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