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X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.7 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH] clk: zynq: eval ps-clock-frequency from DT X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) From: Kai Assman Currently the ps_clk_rate is locked to 33.3MHz. The devicetree provides a property "ps-clock-frequency" that specifies this clock. If the property is found, overwrite ps_clk_rate otherwise stay at the default 33.3MHz Signed-off-by: Kai Assmann Signed-off-by: Steffen Trumtrar --- drivers/clk/zynq/clkc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 8e4beda295..37a0fbadb5 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -388,6 +388,9 @@ static int zynq_clock_probe(struct device *dev) return PTR_ERR(parent_res); slcr_offset = parent_res->start; + + of_property_read_u32(dev->device_node, "ps-clock-frequency", + (u32 *)&ps_clk_rate); } iores = request_iomem_region(dev_name(dev), iores->start + slcr_offset, -- 2.39.0