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Wed, 17 May 2023 11:03:46 +0200 Received: from sha by dude02.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1pzD4Q-00Gase-3y; Wed, 17 May 2023 11:03:42 +0200 From: Sascha Hauer To: Barebox List Date: Wed, 17 May 2023 11:03:34 +0200 Message-Id: <20230517090340.3954615-29-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230517090340.3954615-1-s.hauer@pengutronix.de> References: <20230517090340.3954615-1-s.hauer@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230517_100351_750081_5CF819D4 X-CRM114-Status: GOOD ( 13.46 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.9 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH v2 28/34] ARM: mmu32: Add pte_flags_to_pmd() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) Signed-off-by: Sascha Hauer --- arch/arm/cpu/mmu_32.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/mmu_32.c b/arch/arm/cpu/mmu_32.c index 4abaab7d87..0af89ac39c 100644 --- a/arch/arm/cpu/mmu_32.c +++ b/arch/arm/cpu/mmu_32.c @@ -187,30 +187,53 @@ static u32 pmd_flags_to_pte(u32 pmd) return pte; } +static u32 pte_flags_to_pmd(u32 pte) +{ + u32 pmd = 0; + + if (pte & PTE_BUFFERABLE) + pmd |= PMD_SECT_BUFFERABLE; + if (pte & PTE_CACHEABLE) + pmd |= PMD_SECT_CACHEABLE; + + if (cpu_architecture() >= CPU_ARCH_ARMv7) { + if (pte & PTE_EXT_NG) + pmd |= PMD_SECT_nG; + if (pte & PTE_EXT_XN) + pmd |= PMD_SECT_XN; + + /* TEX[2:0] */ + pmd |= ((pte >> 6) & 7) << 12; + /* AP[1:0] */ + pmd |= ((pte >> 4) & 0x3) << 10; + /* AP[2] */ + pmd |= ((pte >> 9) & 0x1) << 15; + } else { + pmd |= PMD_SECT_AP_WRITE | PMD_SECT_AP_READ; + } + + return pmd; +} + int arch_remap_range(void *start, size_t size, unsigned flags) { u32 addr = (u32)start; u32 pte_flags; - u32 pgd_flags; BUG_ON(!IS_ALIGNED(addr, PAGE_SIZE)); switch (flags) { case MAP_CACHED: pte_flags = pte_flags_cached; - pgd_flags = PMD_SECT_DEF_CACHED; break; case MAP_UNCACHED: pte_flags = pte_flags_uncached; - pgd_flags = pgd_flags_uncached; break; case MAP_FAULT: pte_flags = 0x0; - pgd_flags = 0x0; break; case ARCH_MAP_WRITECOMBINE: pte_flags = pte_flags_wc; - pgd_flags = pgd_flags_wc; break; default: return -EINVAL; @@ -228,7 +251,7 @@ int arch_remap_range(void *start, size_t size, unsigned flags) * replace it with a section */ chunk = PGDIR_SIZE; - *pgd = addr | pgd_flags; + *pgd = addr | pte_flags_to_pmd(pte_flags) | PMD_TYPE_SECT; dma_flush_range(pgd, sizeof(*pgd)); } else { unsigned int num_ptes; -- 2.39.2