[PATCH 00/10] ARM: Rockchip rk3588: eMMC/SD support

[PATCH 00/10] ARM: Rockchip rk3588: eMMC/SD support

[Sascha Hauer]

This series brings up eMMC/SD on Rockchip rk3588 SoCs. There were
multiple bugs that prevented them from working.

Additionally the CPU clock is now configured to 816MHz. This is not
particularly fast, but considerably faster than the original 24MHz.

Sascha Hauer (10):
  mci: rockchip-dwcmshc-sdhci: Add rk3588
  firmware: arm_scmi: fix async check
  clk: rockchip: add missing pll_rk3588_core handling
  clk: clk-divider: fix CLK_DIVIDER_HIWORD_MASK flag
  pinctrl: rockchip: fix bias settings
  ARM: dts: rk3588s: Set CPU clock to 816MHz
  mci: rockchip-dwcmshc-sdhci: enable DLL only for clock >= 52MHz
  ARM: rockchip_v8_defconfig: Enable SCMI support
  ARM: multi_v8_defconfig: Enable SCMI support
  ARM: rockchip rock 5b: drop no longer valid comments

 arch/arm/configs/multi_v8_defconfig    |  3 ++
 arch/arm/configs/rockchip_v8_defconfig |  3 ++
 arch/arm/dts/rk3588-rock-5b.dts        |  2 -
 arch/arm/dts/rk3588s.dtsi              |  5 ++-
 drivers/clk/clk-divider.c              |  2 +-
 drivers/clk/rockchip/clk-pll.c         |  3 +-
 drivers/firmware/arm_scmi/clock.c      |  2 +-
 drivers/mci/rockchip-dwcmshc-sdhci.c   | 54 ++++++++++++++++++++------
 drivers/pinctrl/pinctrl-rockchip.c     | 31 +++++++++++++--
 9 files changed, 83 insertions(+), 22 deletions(-)

-- 
2.39.2

[PATCH 01/10] mci: rockchip-dwcmshc-sdhci: Add rk3588

[Sascha Hauer]

rockchip,rk3588-dwcmshc can be supported out of the box, add the
compatible string for it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/rockchip-dwcmshc-sdhci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mci/rockchip-dwcmshc-sdhci.c b/drivers/mci/rockchip-dwcmshc-sdhci.c
index e1eb4fc788..a935e921b1 100644
--- a/drivers/mci/rockchip-dwcmshc-sdhci.c
+++ b/drivers/mci/rockchip-dwcmshc-sdhci.c
@@ -325,6 +325,8 @@ static int rk_sdhci_probe(struct device *dev)
 static __maybe_unused struct of_device_id rk_sdhci_compatible[] = {
 	{
 		.compatible = "rockchip,rk3568-dwcmshc"
+	}, {
+		.compatible = "rockchip,rk3588-dwcmshc"
 	}, {
 		/* sentinel */
 	}
-- 
2.39.2

[PATCH 02/10] firmware: arm_scmi: fix async check

[Sascha Hauer]

Originally the Linux code had atomic_inc_return(&ci->cur_async_req).
atomic_inc_return() returns the new variable value after increasing it,
so the equivalent is ++ci->cur_async_req, not ci->cur_async_req++.

This fixes a case where the code erroneously chose to do an asynchronous
clock rate change on RK3588.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/firmware/arm_scmi/clock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index 8f9017206c..4fd642dad3 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -250,7 +250,7 @@ static int scmi_clock_rate_set(const struct scmi_protocol_handle *ph,
 		return ret;
 
 	if (ci->max_async_req &&
-	    ci->cur_async_req++ < ci->max_async_req)
+	    ++ci->cur_async_req < ci->max_async_req)
 		flags |= CLOCK_SET_ASYNC;
 
 	cfg = t->tx.buf;
-- 
2.39.2

[PATCH 03/10] clk: rockchip: add missing pll_rk3588_core handling

[Sascha Hauer]

According to the reference manual the PLLs of type pll_rk3588_core also
need the CLK_MUX_HIWORD_MASK. Add it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/rockchip/clk-pll.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 68e680d6ea..736b87e32b 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1097,7 +1097,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 	    pll_type == pll_rk3066 ||
 	    pll_type == pll_rk3328 ||
 	    pll_type == pll_rk3399 ||
-	    pll_type == pll_rk3588)
+	    pll_type == pll_rk3588 ||
+	    pll_type == pll_rk3588_core)
 		pll_mux->flags |= CLK_MUX_HIWORD_MASK;
 
 	/* the actual muxing is xin24m, pll-output, xin32k */
-- 
2.39.2

[PATCH 04/10] clk: clk-divider: fix CLK_DIVIDER_HIWORD_MASK flag

[Sascha Hauer]

The CLK_DIVIDER_HIWORD_MASK flag is in divider->flags, not in the
generic clock flags.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/clk-divider.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index e095b40bfa..1eaff1675b 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -288,7 +288,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 	val &= ~(clk_div_mask(divider->width) << divider->shift);
 	val |= value << divider->shift;
 
-	if (clk->flags & CLK_DIVIDER_HIWORD_MASK)
+	if (divider->flags & CLK_DIVIDER_HIWORD_MASK)
 		val |= clk_div_mask(divider->width) << (divider->shift + 16);
 
 	writel(val, divider->reg);
-- 
2.39.2

[PATCH 05/10] pinctrl: rockchip: fix bias settings

[Sascha Hauer]

The RK_BIAS_PULL_* defines do not always directly map to register
values. In some cases they have to be translated according to the
bank->pull_type array. Add the missing translation.

The original Linux driver passes pinctrl generic defines into
rockchip_set_pull() whereas the barebox driver directly passes
RK_BIAS_* values into rockchip_set_pull(), therefore I thought this
translation is not necessary and skipped it. While bringing up
SD on a RK3588 I ended up with wrong bias settings though, this
is fixed with this commit.

Fixes: 018fcba104 ("pinctrl: Update pinctrl-rockchip from kernel")
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/pinctrl/pinctrl-rockchip.c | 31 ++++++++++++++++++++++++++----
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 57d676fc98..d7ae77d52a 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2101,6 +2101,21 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 	return ret;
 }
 
+static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
+	{
+		RK_BIAS_DISABLE,
+		RK_BIAS_PULL_UP,
+		RK_BIAS_PULL_DOWN,
+		RK_BIAS_BUS_HOLD
+	},
+	{
+		RK_BIAS_DISABLE,
+		RK_BIAS_PULL_DOWN,
+		RK_BIAS_DISABLE,
+		RK_BIAS_PULL_UP
+	},
+};
+
 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 					int pin_num, int pull)
 {
@@ -2108,7 +2123,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 	struct rockchip_pin_ctrl *ctrl = info->ctrl;
 	struct device *dev = info->dev;
 	struct regmap *regmap;
-	int reg, ret;
+	int reg, ret, i, pull_type;
 	u8 bit;
 	u32 data, rmask;
 
@@ -2140,19 +2155,27 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 	case RK3399:
 	case RK3568:
 	case RK3588:
+		pull_type = bank->pull_type[pin_num / 8];
+		ret = -EINVAL;
+		for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); i++) {
+			if (rockchip_pull_list[pull_type][i] == pull) {
+				ret = i;
+				break;
+			}
+		}
 		/*
 		 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
 		 * where that pull up value becomes 3.
 		 */
 		if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
-			if (pull == RK_BIAS_PULL_UP)
-				pull = 3;
+			if (ret == RK_BIAS_PULL_UP)
+				ret = 3;
 		}
 
 		/* enable the write to the equivalent lower bits */
 		data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
 		rmask = data | (data >> 16);
-		data |= (pull << bit);
+		data |= (ret << bit);
 
 		ret = regmap_update_bits(regmap, reg, rmask, data);
 		break;
-- 
2.39.2

[PATCH 06/10] ARM: dts: rk3588s: Set CPU clock to 816MHz

[Sascha Hauer]

Originally the Kernel rk3588s.dtsi assigned the CPU clock rates in the
scmi_clk node. We had to remove the assigned-clock-rates properties
because our SCMI clock driver didn't work properly. Now it does, so we
can bring these properties back. In the meantime the assigned-clock-rates
properties were moved to the cpu nodes in the upstream dtsi file in
87810bda8a847 ("arm64: dts: rockchip: Fix SCMI assigned clocks on rk3588s")
We do not have a driver on the CPU nodes (and neither does the kernel),
so the properties do not help us there. Instead, add the
assigned-clock-rates properties to our local rk3588s.dtsi file.

With this the CPU clocks are configured to 816MHz where the SoC
previously came up with only 24MHz.

Note that the CPU could run with 2.4GHz, but I am not sure yet if all
voltages are configured correctly for that frequency, so for now run
with the frequency that has been the default in the dtsi files.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/rk3588s.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi
index ba6561f97e..6f055d826e 100644
--- a/arch/arm/dts/rk3588s.dtsi
+++ b/arch/arm/dts/rk3588s.dtsi
@@ -130,6 +130,7 @@ combphy2_psu: phy@fee20000 {
 };
 
 &scmi_clk {
-	/delete-property/ assigned-clocks;
-	/delete-property/ assigned-clock-rates;
+	assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
+			  <&scmi_clk SCMI_CLK_CPUB23>;
+	assigned-clock-rates = <816000000>, <816000000>;
 };
-- 
2.39.2

[PATCH 07/10] mci: rockchip-dwcmshc-sdhci: enable DLL only for clock >= 52MHz

[Sascha Hauer]

According to the Kernel the DLL should only be enabled for clock
frequencies higher than 52MHz. Do likewise in barebox. Without this
we get

ERROR: rk3568-dwcmshc-sdhci fe2e0000.mmc@fe2e0000.of: DLL lock timeout!

On a RK3588.

The patch is bigger than it actually needs to be. We are updating
register defines with it and move the "Disable cmd conflict check"
block further up to bring the code closer to the corresponding kernel
code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/rockchip-dwcmshc-sdhci.c | 52 ++++++++++++++++++++++------
 1 file changed, 41 insertions(+), 11 deletions(-)

diff --git a/drivers/mci/rockchip-dwcmshc-sdhci.c b/drivers/mci/rockchip-dwcmshc-sdhci.c
index a935e921b1..c44f5731ca 100644
--- a/drivers/mci/rockchip-dwcmshc-sdhci.c
+++ b/drivers/mci/rockchip-dwcmshc-sdhci.c
@@ -25,21 +25,32 @@
 #define DWCMSHC_EMMC_DLL_RXCLK		0x804
 #define DWCMSHC_EMMC_DLL_TXCLK		0x808
 #define DWCMSHC_EMMC_DLL_STRBIN		0x80c
+#define DECMSHC_EMMC_DLL_CMDOUT		0x810
 #define DWCMSHC_EMMC_DLL_STATUS0	0x840
 #define DWCMSHC_EMMC_DLL_START		BIT(0)
+#define DWCMSHC_EMMC_DLL_LOCKED		BIT(8)
+#define DWCMSHC_EMMC_DLL_TIMEOUT	BIT(9)
 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL	29
 #define DWCMSHC_EMMC_DLL_START_POINT	16
 #define DWCMSHC_EMMC_DLL_INC		8
+#define DWCMSHC_EMMC_DLL_BYPASS		BIT(24)
 #define DWCMSHC_EMMC_DLL_DLYENA		BIT(27)
-#define DLL_TXCLK_TAPNUM_DEFAULT	0x8
-#define DLL_STRBIN_TAPNUM_DEFAULT	0x8
+#define DLL_TXCLK_TAPNUM_DEFAULT	0x10
+#define DLL_TXCLK_TAPNUM_90_DEGREES	0xA
 #define DLL_TXCLK_TAPNUM_FROM_SW	BIT(24)
+#define DLL_STRBIN_TAPNUM_DEFAULT	0x8
 #define DLL_STRBIN_TAPNUM_FROM_SW	BIT(24)
-#define DWCMSHC_EMMC_DLL_LOCKED		BIT(8)
-#define DWCMSHC_EMMC_DLL_TIMEOUT	BIT(9)
+#define DLL_STRBIN_DELAY_NUM_SEL	BIT(26)
+#define DLL_STRBIN_DELAY_NUM_OFFSET	16
+#define DLL_STRBIN_DELAY_NUM_DEFAULT	0x16
 #define DLL_RXCLK_NO_INVERTER		1
 #define DLL_RXCLK_INVERTER		0
-#define DWCMSHC_ENHANCED_STROBE		BIT(8)
+#define DLL_CMDOUT_TAPNUM_90_DEGREES	0x8
+#define DLL_RXCLK_ORI_GATE		BIT(31)
+#define DLL_CMDOUT_TAPNUM_FROM_SW	BIT(24)
+#define DLL_CMDOUT_SRC_CLK_NEG		BIT(28)
+#define DLL_CMDOUT_EN_SRC_CLK_NEG	BIT(29)
+
 #define DLL_LOCK_WO_TMOUT(x) \
 	((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
 	(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
@@ -137,8 +148,32 @@ static void rk_sdhci_set_clock(struct rk_sdhci_host *host, unsigned int clock)
 
 	sdhci_set_clock(&host->sdhci, clock, clk_get_rate(host->clks[CLK_CORE].clk));
 
-	if (clock <= 400000)
+	/* Disable cmd conflict check */
+	extra = sdhci_read32(&host->sdhci, DWCMSHC_HOST_CTRL3);
+	extra &= ~BIT(0);
+	sdhci_write32(&host->sdhci, DWCMSHC_HOST_CTRL3, extra);
+
+	if (clock <= 52000000) {
+		/*
+		 * Disable DLL and reset both of sample and drive clock.
+		 * The bypass bit and start bit need to be set if DLL is not locked.
+		 */
+		sdhci_write32(&host->sdhci, DWCMSHC_EMMC_DLL_CTRL,
+			      DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START);
+		sdhci_write32(&host->sdhci, DWCMSHC_EMMC_DLL_RXCLK, DLL_RXCLK_ORI_GATE);
+		sdhci_write32(&host->sdhci, DWCMSHC_EMMC_DLL_TXCLK, 0);
+		sdhci_write32(&host->sdhci, DECMSHC_EMMC_DLL_CMDOUT, 0);
+		/*
+		 * Before switching to hs400es mode, the driver will enable
+		 * enhanced strobe first. PHY needs to configure the parameters
+		 * of enhanced strobe first.
+		 */
+		extra = DWCMSHC_EMMC_DLL_DLYENA |
+			DLL_STRBIN_DELAY_NUM_SEL |
+			DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
+		sdhci_write32(&host->sdhci, DWCMSHC_EMMC_DLL_STRBIN, extra);
 		return;
+        }
 
 	/* Reset DLL */
 	sdhci_write32(&host->sdhci, DWCMSHC_EMMC_DLL_CTRL, BIT(1));
@@ -158,11 +193,6 @@ static void rk_sdhci_set_clock(struct rk_sdhci_host *host, unsigned int clock)
 		return;
 	}
 
-	/* Disable cmd conflict check */
-	extra = sdhci_read32(&host->sdhci, DWCMSHC_HOST_CTRL3);
-	extra &= ~BIT(0);
-	sdhci_write32(&host->sdhci, DWCMSHC_HOST_CTRL3, extra);
-
 	extra = 0x1 << 16 | /* tune clock stop en */
 		0x2 << 17 | /* pre-change delay */
 		0x3 << 19;  /* post-change delay */
-- 
2.39.2

[PATCH 08/10] ARM: rockchip_v8_defconfig: Enable SCMI support

[Sascha Hauer]

SCMI clocks are needed to support the RK3588.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/configs/rockchip_v8_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/configs/rockchip_v8_defconfig b/arch/arm/configs/rockchip_v8_defconfig
index efe6adc9dc..cc3c3c6d48 100644
--- a/arch/arm/configs/rockchip_v8_defconfig
+++ b/arch/arm/configs/rockchip_v8_defconfig
@@ -119,6 +119,7 @@ CONFIG_MCI_MMC_BOOT_PARTITIONS=y
 CONFIG_MCI_DW=y
 CONFIG_MCI_ROCKCHIP_DWCMSHC=y
 CONFIG_MCI_ARASAN=y
+CONFIG_COMMON_CLK_SCMI=y
 CONFIG_MFD_ACT8846=y
 CONFIG_MFD_RK808=y
 CONFIG_LED=y
@@ -129,7 +130,9 @@ CONFIG_WATCHDOG_POLLER=y
 CONFIG_WATCHDOG_DW=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED=y
+CONFIG_REGULATOR_ARM_SCMI=y
 CONFIG_REGULATOR_RK808=y
+CONFIG_ARM_SCMI_PROTOCOL=y
 CONFIG_GENERIC_PHY=y
 CONFIG_USB_NOP_XCEIV=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-- 
2.39.2

[PATCH 09/10] ARM: multi_v8_defconfig: Enable SCMI support

[Sascha Hauer]

SCMI clocks are needed to support the Rockchip RK3588.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/configs/multi_v8_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig
index d30158d7f8..e0ff21641a 100644
--- a/arch/arm/configs/multi_v8_defconfig
+++ b/arch/arm/configs/multi_v8_defconfig
@@ -188,6 +188,7 @@ CONFIG_MCI_DW=y
 CONFIG_MCI_ROCKCHIP_DWCMSHC=y
 CONFIG_MCI_IMX_ESDHC=y
 CONFIG_MCI_ARASAN=y
+CONFIG_COMMON_CLK_SCMI=y
 CONFIG_MFD_ACT8846=y
 CONFIG_RAVE_SP_CORE=y
 CONFIG_MFD_RK808=y
@@ -211,12 +212,14 @@ CONFIG_IMX_OCOTP=y
 CONFIG_RAVE_SP_EEPROM=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED=y
+CONFIG_REGULATOR_ARM_SCMI=y
 CONFIG_REGULATOR_RK808=y
 CONFIG_RESET_IMX7=y
 CONFIG_PCI_ECAM_GENERIC=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_FIRMWARE_ZYNQMP_FPGA=y
+CONFIG_ARM_SCMI_PROTOCOL=y
 CONFIG_GENERIC_PHY=y
 CONFIG_USB_NOP_XCEIV=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-- 
2.39.2

[PATCH 10/10] ARM: rockchip rock 5b: drop no longer valid comments

[Sascha Hauer]

With previous patches both eMMC and SD are now working, so remove
the commments stating that they are not.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/rk3588-rock-5b.dts | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts
index 737498df3d..b0275b0415 100644
--- a/arch/arm/dts/rk3588-rock-5b.dts
+++ b/arch/arm/dts/rk3588-rock-5b.dts
@@ -69,7 +69,6 @@ &pcie2x1l2 {
 	status = "okay";
 };
 
-/* Not yet working in barebox */
 &sdhci {
 	partitions {
 		compatible = "fixed-partitions";
@@ -83,7 +82,6 @@ environment_emmc: partition@408000 {
 	};
 };
 
-/* Not yet working in barebox */
 &sdmmc {
 	max-frequency = <200000000>;
 	no-sdio;
-- 
2.39.2

Re: [PATCH 00/10] ARM: Rockchip rk3588: eMMC/SD support

[Ahmad Fatoum]

On 30.05.23 13:18, Sascha Hauer wrote:
> This series brings up eMMC/SD on Rockchip rk3588 SoCs. There were
> multiple bugs that prevented them from working.
> 
> Additionally the CPU clock is now configured to 816MHz. This is not
> particularly fast, but considerably faster than the original 24MHz.

Which DRAM setup blob have you been using? Which BL31? What version
of these? Can this be added to the documentation?

> 
> Sascha Hauer (10):
>   mci: rockchip-dwcmshc-sdhci: Add rk3588
>   firmware: arm_scmi: fix async check
>   clk: rockchip: add missing pll_rk3588_core handling
>   clk: clk-divider: fix CLK_DIVIDER_HIWORD_MASK flag
>   pinctrl: rockchip: fix bias settings
>   ARM: dts: rk3588s: Set CPU clock to 816MHz
>   mci: rockchip-dwcmshc-sdhci: enable DLL only for clock >= 52MHz
>   ARM: rockchip_v8_defconfig: Enable SCMI support
>   ARM: multi_v8_defconfig: Enable SCMI support
>   ARM: rockchip rock 5b: drop no longer valid comments
> 
>  arch/arm/configs/multi_v8_defconfig    |  3 ++
>  arch/arm/configs/rockchip_v8_defconfig |  3 ++
>  arch/arm/dts/rk3588-rock-5b.dts        |  2 -
>  arch/arm/dts/rk3588s.dtsi              |  5 ++-
>  drivers/clk/clk-divider.c              |  2 +-
>  drivers/clk/rockchip/clk-pll.c         |  3 +-
>  drivers/firmware/arm_scmi/clock.c      |  2 +-
>  drivers/mci/rockchip-dwcmshc-sdhci.c   | 54 ++++++++++++++++++++------
>  drivers/pinctrl/pinctrl-rockchip.c     | 31 +++++++++++++--
>  9 files changed, 83 insertions(+), 22 deletions(-)
> 

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