[PATCH 03/10] clk: rockchip: add missing pll_rk3588_core handling

[Sascha Hauer <s.hauer@pengutronix.de>]

According to the reference manual the PLLs of type pll_rk3588_core also
need the CLK_MUX_HIWORD_MASK. Add it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/rockchip/clk-pll.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 68e680d6ea..736b87e32b 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1097,7 +1097,8 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 	    pll_type == pll_rk3066 ||
 	    pll_type == pll_rk3328 ||
 	    pll_type == pll_rk3399 ||
-	    pll_type == pll_rk3588)
+	    pll_type == pll_rk3588 ||
+	    pll_type == pll_rk3588_core)
 		pll_mux->flags |= CLK_MUX_HIWORD_MASK;
 
 	/* the actual muxing is xin24m, pll-output, xin32k */
-- 
2.39.2