From: Denis Orlov <denorl2009@gmail.com>
To: barebox@lists.infradead.org
Cc: Denis Orlov <denorl2009@gmail.com>
Subject: [PATCH 07/17] MIPS: use MIPS32/MIPS64 generic instruction macros
Date: Mon, 5 Jun 2023 23:10:38 +0300 [thread overview]
Message-ID: <20230605202634.42175-8-denorl2009@gmail.com> (raw)
In-Reply-To: <20230605202634.42175-1-denorl2009@gmail.com>
Use PTR_* for various arithmetic operations on pointers, and also use
PTR_LA instead of simple 'la' instruction, as it will correctly handle
loading 64-bit addresses from non-32-bit-compatible virtual memory
segments.
This fixes "la used to load 64-bit address; recommend using dla instead"
warnings when compiling assembly code with CONFIG_64BIT.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/boot/start.S | 2 +-
arch/mips/include/asm/asm.h | 10 +++++-----
arch/mips/include/asm/debug_ll_ns16550.h | 6 +++---
arch/mips/include/asm/pbl_macros.h | 22 +++++++++++-----------
arch/mips/lib/genex.S | 8 ++++----
5 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
index c1cd2d9dd5..5f134f9ae9 100644
--- a/arch/mips/boot/start.S
+++ b/arch/mips/boot/start.S
@@ -34,7 +34,7 @@ EXPORT(_start)
move a0, s0
move a1, s1
move a2, s2
- la v0, relocate_code
+ PTR_LA v0, relocate_code
jal v0
nop
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 69931662ff..c699542a55 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -94,10 +94,10 @@ EXPORT(symbol)
copy_to_link_location symbol; \
stack_setup; \
\
- la a0, __dtb_ ## dtb##_start; \
- la a1, __dtb_ ## dtb##_end; \
- li a2, ram_size; \
- la v0, pbl_main_entry; \
+ PTR_LA a0, __dtb_ ## dtb##_start; \
+ PTR_LA a1, __dtb_ ## dtb##_end; \
+ PTR_LI a2, ram_size; \
+ PTR_LA v0, pbl_main_entry; \
jal v0; \
nop; \
\
@@ -122,7 +122,7 @@ EXPORT(symbol)
/* Call some code from .text section. \
* It is needed to keep same linker script for \
* all images. */ \
- la v0, mips_dead_end; \
+ PTR_LA v0, mips_dead_end; \
jal v0; \
nop;
diff --git a/arch/mips/include/asm/debug_ll_ns16550.h b/arch/mips/include/asm/debug_ll_ns16550.h
index 703bfaee77..7cfd844cb6 100644
--- a/arch/mips/include/asm/debug_ll_ns16550.h
+++ b/arch/mips/include/asm/debug_ll_ns16550.h
@@ -60,7 +60,7 @@ static inline void PUTC_LL(char ch)
.macro debug_ll_ns16550_init divisor=DEBUG_LL_UART_DIVISOR
#ifdef CONFIG_DEBUG_LL
- la t0, DEBUG_LL_UART_ADDR
+ PTR_LA t0, DEBUG_LL_UART_ADDR
li t1, UART_LCR_DLAB /* DLAB on */
sb t1, UART_LCR(t0) /* Write it out */
@@ -83,7 +83,7 @@ static inline void PUTC_LL(char ch)
.set push
.set reorder
- la t0, DEBUG_LL_UART_ADDR
+ PTR_LA t0, DEBUG_LL_UART_ADDR
201: lbu t1, UART_LSR(t0) /* get line status */
andi t1, t1, UART_LSR_THRE /* check for transmitter empty */
@@ -126,7 +126,7 @@ static inline void PUTC_LL(char ch)
.set push
.set reorder
- la t0, DEBUG_LL_UART_ADDR
+ PTR_LA t0, DEBUG_LL_UART_ADDR
/* get line status and check for data present */
lbu t1, UART_LSR(t0)
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index e60af38442..1fba690c8c 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -73,7 +73,7 @@
.macro pbl_probe_mem ret1 ret2 addr
.set push
.set noreorder
- la \ret1, \addr
+ PTR_LA \ret1, \addr
sw zero, 0(\ret1)
li \ret2, 0x12345678
sw \ret2, 0(\ret1)
@@ -97,7 +97,7 @@
move \temp, ra # preserve ra beforehand
bal 255f
nop
-255: addiu \rd, ra, \label - 255b # label is assumed to be
+255: PTR_ADDIU \rd, ra, \label - 255b # label is assumed to be
move ra, \temp # within pc +/- 32KB
.set pop
.endm
@@ -110,15 +110,15 @@
ADR a0, \start_addr, t1 /* a0 <- pc-relative
position of start_addr */
- la a1, \start_addr /* a1 <- link (RAM) start_addr address */
+ PTR_LA a1, \start_addr /* a1 <- link (RAM) start_addr address */
beq a0, a1, copy_loop_exit
nop
- la t0, \start_addr
- la t1, __bss_start
- subu t2, t1, t0 /* t2 <- size of pbl */
- addu a2, a0, t2 /* a2 <- source end address */
+ PTR_LA t0, \start_addr
+ PTR_LA t1, __bss_start
+ PTR_SUBU t2, t1, t0 /* t2 <- size of pbl */
+ PTR_ADDU a2, a0, t2 /* a2 <- source end address */
#define WSIZE 4
copy_loop:
@@ -132,10 +132,10 @@
sw ta1, WSIZE * 1(a1)
sw ta2, WSIZE * 2(a1)
sw ta3, WSIZE * 3(a1)
- addi a0, WSIZE * 4
- subu t3, a0, a2
+ PTR_ADDI a0, WSIZE * 4
+ PTR_SUBU t3, a0, a2
blez t3, copy_loop
- addi a1, WSIZE * 4
+ PTR_ADDI a1, WSIZE * 4
copy_loop_exit:
@@ -196,7 +196,7 @@
.set noreorder
/* set stack pointer; reserve four 32-bit argument slots */
- la sp, (TEXT_BASE - MALLOC_SIZE - 16)
+ PTR_LA sp, (TEXT_BASE - MALLOC_SIZE - 16)
.set pop
.endm
diff --git a/arch/mips/lib/genex.S b/arch/mips/lib/genex.S
index d75a652e4d..b9d18fc394 100644
--- a/arch/mips/lib/genex.S
+++ b/arch/mips/lib/genex.S
@@ -14,7 +14,7 @@
/* Exception vector */
NESTED(handle_reserved, 0, sp)
SAVE_ALL
- la k0, barebox_exc_handler
+ PTR_LA k0, barebox_exc_handler
jal k0
move a0, sp
/* will never return here */
@@ -24,10 +24,10 @@ NESTED(handle_reserved, 0, sp)
NESTED(except_vec3_generic, 0, sp)
.set noat
mfc0 k1, CP0_CAUSE
- la k0, exception_handlers
+ PTR_LA k0, exception_handlers
andi k1, k1, 0x7c
- addu k0, k0, k1
- lw k0, (k0)
+ PTR_ADDU k0, k0, k1
+ PTR_L k0, (k0)
nop
jr k0
nop
--
2.41.0
next prev parent reply other threads:[~2023-06-05 20:28 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-05 20:10 [PATCH 00/17] MIPS: fix and improve 64BIT support Denis Orlov
2023-06-05 20:10 ` [PATCH 01/17] MIPS: malta: allow to choose MIPS64 target CPU in config Denis Orlov
2023-06-06 8:06 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 02/17] MIPS: malta: use CKSEG instead of KSEG macros Denis Orlov
2023-06-06 8:03 ` Ahmad Fatoum
2023-06-06 9:14 ` Denis Orlov
2023-06-05 20:10 ` [PATCH 03/17] MIPS: reloc: fix relocation with CONFIG_64BIT enabled Denis Orlov
2023-06-06 8:08 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 04/17] MIPS: o32: provide ta0..ta3 register definitions Denis Orlov
2023-06-06 8:13 ` Ahmad Fatoum
2023-06-06 9:38 ` Denis Orlov
2023-06-05 20:10 ` [PATCH 05/17] MIPS: pbl: use o32/n64 compatible " Denis Orlov
2023-06-06 8:20 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 06/17] MIPS: pbl: fix linking errors with CONFIG_64BIT Denis Orlov
2023-06-05 20:10 ` Denis Orlov [this message]
2023-06-06 8:23 ` [PATCH 07/17] MIPS: use MIPS32/MIPS64 generic instruction macros Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 08/17] MIPS: malta: fix GT64120 base virtual address on 64BIT Denis Orlov
2023-06-06 8:35 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 09/17] MIPS: fix addresses of exception vectors in 64-bit mode Denis Orlov
2023-06-06 8:36 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 10/17] MIPS: fix *ADDR macro usage warnings on CONFIG_64BIT Denis Orlov
2023-06-05 20:10 ` [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value " Denis Orlov
2023-06-06 9:04 ` Ahmad Fatoum
2023-06-06 9:23 ` Denis Orlov
2023-06-09 6:40 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 12/17] MIPS: enable 64-bit kernel segment addressing " Denis Orlov
2023-06-06 9:06 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 13/17] MIPS: traps: fix passing wrong sp when returning from exception Denis Orlov
2023-06-05 20:10 ` [PATCH 14/17] MIPS: pbl_macros: use generic load/store macros in copy_to_link_location Denis Orlov
2023-06-06 9:07 ` Ahmad Fatoum
2023-06-05 20:10 ` [PATCH 15/17] MIPS: add 64-bit support for optimized string functions Denis Orlov
2023-06-05 20:10 ` [PATCH 16/17] MIPS: make setjmp/longjmp/initjmp available in 64BIT builds Denis Orlov
2023-06-05 20:10 ` [PATCH 17/17] MIPS: main_entry-pbl: fix conversion warnings on CONFIG_64BIT Denis Orlov
2023-06-06 8:02 ` [PATCH 00/17] MIPS: fix and improve 64BIT support Ahmad Fatoum
2023-06-06 8:43 ` Denis Orlov
2023-06-09 6:43 ` Sascha Hauer
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