From: Denis Orlov <denorl2009@gmail.com>
To: barebox@lists.infradead.org
Cc: Denis Orlov <denorl2009@gmail.com>,
Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH 15/21] MIPS: main_entry: properly set XTLB handler for 64-bit mode
Date: Tue, 25 Jul 2023 08:05:16 +0300 [thread overview]
Message-ID: <20230725050618.3451-16-denorl2009@gmail.com> (raw)
In-Reply-To: <20230725050618.3451-1-denorl2009@gmail.com>
The offset of the TLB Load exception is different when 64-bit addressing
is enabled - 0x80 is used instead of 0x0. To simplify things, just copy
the handler code twice, for each of the cases.
While at it, also remove the incomprehensible cpu_has_4kex check. All of
the supported CPUs have MIPS R4K compatible exception handling scheme
(and we even hardcode that), so what are we trying to achieve there
anyway?
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
arch/mips/boot/main_entry.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
index 99cd2ec846..237288a337 100644
--- a/arch/mips/boot/main_entry.c
+++ b/arch/mips/boot/main_entry.c
@@ -50,11 +50,9 @@ static void trap_init(void)
set_except_vector(i, &handle_reserved);
}
- if (!cpu_has_4kex)
- memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
-
/* FIXME: handle tlb */
memcpy((void *)(ebase), &except_vec3_generic, 0x80);
+ memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
/* unset BOOT EXCEPTION VECTOR bit */
write_c0_status(read_c0_status() & ~ST0_BEV);
--
2.41.0
next prev parent reply other threads:[~2023-07-25 5:08 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-25 5:05 [PATCH 00/21] MIPS: semi-random code improvements Denis Orlov
2023-07-25 5:05 ` [PATCH 01/21] MIPS: addrspace: rectify ksseg segment naming Denis Orlov
2023-07-25 5:05 ` [PATCH 02/21] MIPS: addrspace: simplify the header Denis Orlov
2023-07-25 5:05 ` [PATCH 03/21] MIPS: main_entry-pbl: remove unused variable Denis Orlov
2023-07-25 5:05 ` [PATCH 04/21] MIPS: barebox.lds: remove extra whitespace Denis Orlov
2023-07-25 5:05 ` [PATCH 05/21] MIPS: reloc: mark relocate_code() as noreturn Denis Orlov
2023-07-25 5:05 ` [PATCH 06/21] MIPS: cpuinfo: use appropriate format specifiers in printf Denis Orlov
2023-07-25 5:05 ` [PATCH 07/21] MIPS: print BadVAddr CP0 register on exception Denis Orlov
2023-07-25 5:05 ` [PATCH 08/21] MIPS: malta: merge GT64120 headers Denis Orlov
2023-07-25 5:05 ` [PATCH 09/21] MIPS: pbl_macros: use .asciiz instead of .ascii + .byte 0 Denis Orlov
2023-07-25 5:05 ` [PATCH 10/21] MIPS: malta: remove duplicated barebox magic code Denis Orlov
2023-07-25 5:05 ` [PATCH 11/21] MIPS: pbl: put mips_barebox_10h into ENTRY_FUNCTION Denis Orlov
2023-07-25 5:05 ` [PATCH 12/21] MIPS: pbl: make sure to disable interrupts/watchpoints on entry Denis Orlov
2023-07-25 5:05 ` [PATCH 13/21] MIPS: pbl: do enable 64-bit addressing in PBL Denis Orlov
2023-07-25 5:05 ` [PATCH 14/21] MIPS: clean up barebox proper entry point Denis Orlov
2023-07-25 5:05 ` Denis Orlov [this message]
2023-07-25 5:05 ` [PATCH 16/21] MIPS: main_entry: remove exception vector array Denis Orlov
2023-07-25 5:05 ` [PATCH 17/21] MIPS: c-r4k: prettify code in __BUILD_BLAST_CACHE_RANGE Denis Orlov
2023-07-25 5:05 ` [PATCH 18/21] MIPS: c-r4k: generate blast_*cache functions via macros Denis Orlov
2023-07-25 5:05 ` [PATCH 19/21] MIPS: c-r4k: do flush secondary cache Denis Orlov
2023-07-25 5:05 ` [PATCH 20/21] MIPS: c-r4k: remove extra function declaration Denis Orlov
2023-07-25 5:05 ` [PATCH 21/21] MIPS: reloc: use IS_ALIGNED macro to check for an alignment Denis Orlov
2023-07-27 5:09 ` [PATCH 00/21] MIPS: semi-random code improvements Sascha Hauer
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