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Mon, 24 Jul 2023 22:06:46 -0700 (PDT) Received: from localhost.localdomain ([188.123.230.211]) by smtp.gmail.com with ESMTPSA id k17-20020a05640212d100b0052237dfa82fsm1730505edx.64.2023.07.24.22.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 22:06:46 -0700 (PDT) From: Denis Orlov To: barebox@lists.infradead.org Date: Tue, 25 Jul 2023 08:05:16 +0300 Message-ID: <20230725050618.3451-16-denorl2009@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230725050618.3451-1-denorl2009@gmail.com> References: <20230725050618.3451-1-denorl2009@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230724_220648_670413_79539019 X-CRM114-Status: GOOD ( 11.34 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Denis Orlov , Ahmad Fatoum Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.6 required=4.0 tests=AWL,BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 15/21] MIPS: main_entry: properly set XTLB handler for 64-bit mode X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) The offset of the TLB Load exception is different when 64-bit addressing is enabled - 0x80 is used instead of 0x0. To simplify things, just copy the handler code twice, for each of the cases. While at it, also remove the incomprehensible cpu_has_4kex check. All of the supported CPUs have MIPS R4K compatible exception handling scheme (and we even hardcode that), so what are we trying to achieve there anyway? Signed-off-by: Denis Orlov --- arch/mips/boot/main_entry.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c index 99cd2ec846..237288a337 100644 --- a/arch/mips/boot/main_entry.c +++ b/arch/mips/boot/main_entry.c @@ -50,11 +50,9 @@ static void trap_init(void) set_except_vector(i, &handle_reserved); } - if (!cpu_has_4kex) - memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); - /* FIXME: handle tlb */ memcpy((void *)(ebase), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); /* unset BOOT EXCEPTION VECTOR bit */ write_c0_status(read_c0_status() & ~ST0_BEV); -- 2.41.0