[PATCH 00/21] MIPS: semi-random code improvements

[PATCH 00/21] MIPS: semi-random code improvements

[Denis Orlov]

Denis Orlov (21):
  MIPS: addrspace: rectify ksseg segment naming
  MIPS: addrspace: simplify the header
  MIPS: main_entry-pbl: remove unused variable
  MIPS: barebox.lds: remove extra whitespace
  MIPS: reloc: mark relocate_code() as noreturn
  MIPS: cpuinfo: use appropriate format specifiers in printf
  MIPS: print BadVAddr CP0 register on exception
  MIPS: malta: merge GT64120 headers
  MIPS: pbl_macros: use .asciiz instead of .ascii + .byte 0
  MIPS: malta: remove duplicated barebox magic code
  MIPS: pbl: put mips_barebox_10h into ENTRY_FUNCTION
  MIPS: pbl: make sure to disable interrupts/watchpoints on entry
  MIPS: pbl: do enable 64-bit addressing in PBL
  MIPS: clean up barebox proper entry point
  MIPS: main_entry: properly set XTLB handler for 64-bit mode
  MIPS: main_entry: remove exception vector array
  MIPS: c-r4k: prettify code in __BUILD_BLAST_CACHE_RANGE
  MIPS: c-r4k: generate blast_*cache functions via macros
  MIPS: c-r4k: do flush secondary cache
  MIPS: c-r4k: remove extra function declaration
  MIPS: reloc: use IS_ALIGNED macro to check for an alignment

 arch/mips/boards/8devices-lima/lowlevel.S     |  2 +-
 arch/mips/boards/dlink-dir-320/lowlevel.S     |  4 +-
 arch/mips/boards/img-ci20/lowlevel.S          |  2 +-
 arch/mips/boards/loongson-ls1b/lowlevel.S     |  4 +-
 arch/mips/boards/netgear-wg102/lowlevel.S     |  4 +-
 arch/mips/boards/qemu-malta/lowlevel.S        | 17 +----
 arch/mips/boards/ritmix-rzx50/lowlevel.S      |  2 +-
 arch/mips/boards/tplink-wdr4300/lowlevel.S    |  2 +-
 arch/mips/boot/main_entry-pbl.c               |  4 --
 arch/mips/boot/main_entry.c                   | 41 +++--------
 arch/mips/boot/start.S                        | 46 -------------
 arch/mips/boot/start.c                        | 17 +++++
 arch/mips/include/asm/addrspace.h             | 47 ++++++-------
 arch/mips/include/asm/asm.h                   |  4 +-
 arch/mips/include/asm/cacheops.h              |  5 ++
 arch/mips/include/asm/pbl_macros.h            | 20 +++++-
 arch/mips/include/asm/stackframe.h            |  4 ++
 arch/mips/lib/barebox.lds.S                   |  2 -
 arch/mips/lib/c-r4k.c                         | 68 ++++++++++---------
 arch/mips/lib/cpuinfo.c                       |  6 +-
 arch/mips/lib/genex.S                         | 29 +++-----
 arch/mips/lib/reloc.c                         |  6 +-
 arch/mips/lib/traps.c                         |  3 +-
 .../mips/mach-ath79/include/mach/pbl_macros.h |  4 +-
 .../asm => mach-malta/include/mach}/gt64120.h | 13 ++--
 .../mach-malta/include/mach/mach-gt64120.h    | 17 -----
 arch/mips/mach-malta/pci.c                    |  4 +-
 27 files changed, 147 insertions(+), 230 deletions(-)
 delete mode 100644 arch/mips/boot/start.S
 create mode 100644 arch/mips/boot/start.c
 rename arch/mips/{include/asm => mach-malta/include/mach}/gt64120.h (92%)
 delete mode 100644 arch/mips/mach-malta/include/mach/mach-gt64120.h

-- 
2.41.0

[PATCH 01/21] MIPS: addrspace: rectify ksseg segment naming

[Denis Orlov]

There was a slight confusion in macro definitions for various memory
segments. In the 64-bit mode, there was CKSEG2ADDR defined without a
corresponding CKSEG2 definition, which led to errors when trying to
actually use it. Instead there was a CKSSEG definition that stands for
exactly the same memory segment.

Change the name of this memory segment macro into KSSEG/CKSSEG for the
32/64-bit mode respectively and also rename the corresponding *ADDR
macros as this is how this segment is actually named in the MIPS
architecture specification. This makes the naming more consistent.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/include/asm/addrspace.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 11f10e5011..7a2006a8d1 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -67,7 +67,7 @@
 
 #define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
 #define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
-#define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
+#define CKSSEGADDR(a)		(CPHYSADDR(a) | CKSSEG)
 #define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
 
 /*
@@ -94,7 +94,7 @@
 
 #define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
 #define CKSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
-#define CKSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
+#define CKSSEGADDR(a)		(CPHYSADDR(a) | KSSEG)
 #define CKSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
 
 /*
@@ -102,7 +102,7 @@
  */
 #define KSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
 #define KSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
-#define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
+#define KSSEGADDR(a)		(CPHYSADDR(a) | KSSEG)
 #define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
 
 /*
@@ -112,13 +112,13 @@
 #define KUSEG			0x00000000
 #define KSEG0			0x80000000
 #define KSEG1			0xa0000000
-#define KSEG2			0xc0000000
+#define KSSEG			0xc0000000
 #define KSEG3			0xe0000000
 
 #define CKUSEG			0x00000000
 #define CKSEG0			0x80000000
 #define CKSEG1			0xa0000000
-#define CKSEG2			0xc0000000
+#define CKSSEG			0xc0000000
 #define CKSEG3			0xe0000000
 
 #endif
-- 
2.41.0

[PATCH 02/21] MIPS: addrspace: simplify the header

[Denis Orlov]

Deduplicate some of the definitions for 32/64-bit targets and make KSEG*
32-bit defines available for 64-bit builds, as those might still be
useful in certain cases.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/include/asm/addrspace.h | 45 ++++++++++++++-----------------
 1 file changed, 20 insertions(+), 25 deletions(-)

diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 7a2006a8d1..dd3b5570dd 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -49,6 +49,16 @@
 #define XPHYSADDR(a)            ((_ACAST64_(a)) &			\
 				 _CONST64_(0x000000ffffffffff))
 
+/*
+ * Memory segments (32bit kernel mode addresses)
+ * These are the traditional names used in the 32-bit universe.
+ */
+#define KUSEG			0x00000000
+#define KSEG0			0x80000000
+#define KSEG1			0xa0000000
+#define KSSEG			0xc0000000
+#define KSEG3			0xe0000000
+
 #ifdef CONFIG_64BIT
 
 /*
@@ -65,11 +75,6 @@
 #define CKSSEG			_CONST64_(0xffffffffc0000000)
 #define CKSEG3			_CONST64_(0xffffffffe0000000)
 
-#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
-#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
-#define CKSSEGADDR(a)		(CPHYSADDR(a) | CKSSEG)
-#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
-
 /*
  * Cache modes for XKPHYS address conversion macros
  */
@@ -92,11 +97,6 @@
 
 #else
 
-#define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
-#define CKSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
-#define CKSSEGADDR(a)		(CPHYSADDR(a) | KSSEG)
-#define CKSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
-
 /*
  * Map an address to a certain kernel segment
  */
@@ -105,22 +105,17 @@
 #define KSSEGADDR(a)		(CPHYSADDR(a) | KSSEG)
 #define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
 
-/*
- * Memory segments (32bit kernel mode addresses)
- * These are the traditional names used in the 32-bit universe.
- */
-#define KUSEG			0x00000000
-#define KSEG0			0x80000000
-#define KSEG1			0xa0000000
-#define KSSEG			0xc0000000
-#define KSEG3			0xe0000000
-
-#define CKUSEG			0x00000000
-#define CKSEG0			0x80000000
-#define CKSEG1			0xa0000000
-#define CKSSEG			0xc0000000
-#define CKSEG3			0xe0000000
+#define CKUSEG			KUSEG
+#define CKSEG0			KSEG0
+#define CKSEG1			KSEG1
+#define CKSSEG			KSSEG
+#define CKSEG3			KSEG3
 
 #endif
 
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
+#define CKSSEGADDR(a)		(CPHYSADDR(a) | CKSSEG)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
+
 #endif /* _ASM_ADDRSPACE_H */
-- 
2.41.0

[PATCH 03/21] MIPS: main_entry-pbl: remove unused variable

[Denis Orlov]

For some reason we do set 'ttb' global variable, however we never end up
using it.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/boot/main_entry-pbl.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/mips/boot/main_entry-pbl.c b/arch/mips/boot/main_entry-pbl.c
index f75ec03851..78982fd995 100644
--- a/arch/mips/boot/main_entry-pbl.c
+++ b/arch/mips/boot/main_entry-pbl.c
@@ -20,16 +20,12 @@ unsigned long free_mem_end_ptr;
 
 void pbl_main_entry(void *fdt, void *fdt_end, u32 ram_size);
 
-static unsigned long *ttb;
-
 static void barebox_uncompress(void *compressed_start, unsigned int len)
 {
 	/* set 128 KiB at the end of the MALLOC_BASE for early malloc */
 	free_mem_ptr = TEXT_BASE - SZ_128K;
 	free_mem_end_ptr = free_mem_ptr + SZ_128K;
 
-	ttb = (void *)((free_mem_ptr - 0x4000) & ~0x3fff);
-
 	pbl_barebox_uncompress((void*)TEXT_BASE, compressed_start, len);
 }
 
-- 
2.41.0

[PATCH 04/21] MIPS: barebox.lds: remove extra whitespace

[Denis Orlov]

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/lib/barebox.lds.S | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/mips/lib/barebox.lds.S b/arch/mips/lib/barebox.lds.S
index 1259a4e94f..0720f9295d 100644
--- a/arch/mips/lib/barebox.lds.S
+++ b/arch/mips/lib/barebox.lds.S
@@ -3,7 +3,6 @@
  * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
  */
 
-
 #include <asm/barebox.lds.h>
 
 OUTPUT_ARCH(BAREBOX_OUTPUT_ARCH)
@@ -67,5 +66,4 @@ SECTIONS
 		. = ALIGN(4);
 		__bss_stop = .;
 	}
-
 }
-- 
2.41.0

[PATCH 05/21] MIPS: reloc: mark relocate_code() as noreturn

[Denis Orlov]

After relocating the code we jump straight to it, with the function
having an 'unreachable()' call at the end. So add an appropriate
attribute.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/lib/reloc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
index 3c845a9663..83b4040d95 100644
--- a/arch/mips/lib/reloc.c
+++ b/arch/mips/lib/reloc.c
@@ -41,7 +41,7 @@
 #include <asm-generic/memory_layout.h>
 
 void main_entry(void *fdt, u32 fdt_size);
-void relocate_code(void *fdt, u32 fdt_size, u32 relocaddr);
+void __noreturn relocate_code(void *fdt, u32 fdt_size, u32 relocaddr);
 
 /**
  * read_uint() - Read an unsigned integer from the buffer
@@ -106,7 +106,7 @@ static void apply_reloc(unsigned int type, void *addr, long off)
 	}
 }
 
-void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
+void __noreturn relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
 {
 	unsigned long addr, length, bss_len, relocaddr, new_stack;
 	uint8_t *buf;
-- 
2.41.0

[PATCH 06/21] MIPS: cpuinfo: use appropriate format specifiers in printf

[Denis Orlov]

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/lib/cpuinfo.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/lib/cpuinfo.c b/arch/mips/lib/cpuinfo.c
index fd27920f9b..41ec7b8d53 100644
--- a/arch/mips/lib/cpuinfo.c
+++ b/arch/mips/lib/cpuinfo.c
@@ -25,12 +25,12 @@ static int do_cpuinfo(int argc, char *argv[])
 	icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
 	dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
 
-	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
+	printk("Primary instruction cache %ukB, %s, %s, linesize %d bytes.\n",
 	       icache_size >> 10,
 	       c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
 	       way_string[c->icache.ways], c->icache.linesz);
 
-	printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+	printk("Primary data cache %ukB, %s, %s, %s, linesize %d bytes\n",
 	       dcache_size >> 10, way_string[c->dcache.ways],
 	       (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
 	       (c->dcache.flags & MIPS_CACHE_ALIASES) ?
@@ -39,7 +39,7 @@ static int do_cpuinfo(int argc, char *argv[])
 	if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
 		return 0;
 	scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
-	printk("Secondary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+	printk("Secondary data cache %ukB, %s, %s, %s, linesize %d bytes\n",
 	       scache_size >> 10, way_string[c->scache.ways],
 	       (c->scache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
 	       (c->scache.flags & MIPS_CACHE_ALIASES) ?
-- 
2.41.0

[PATCH 07/21] MIPS: print BadVAddr CP0 register on exception

[Denis Orlov]

This register contains the failing address on Address Error and some
TLB-related exceptions, and is useful for debugging purposes.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/include/asm/stackframe.h | 4 ++++
 arch/mips/lib/traps.c              | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 2295d7f02f..64ec37478a 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -89,8 +89,10 @@
 #endif
 		LONG_S	v1, PT_EPC(sp)
 		LONG_S	$25, PT_R25(sp)
+		MFC0	v1, CP0_BADVADDR
 		LONG_S	$28, PT_R28(sp)
 		LONG_S	$31, PT_R31(sp)
+		LONG_S	v1, PT_BVADDR(sp)
 		.set	pop
 		.endm
 
@@ -157,11 +159,13 @@
 		MTC0	v1, CP0_EPC
 		LONG_L	$31, PT_R31(sp)
 		LONG_L	$28, PT_R28(sp)
+		LONG_L	v1, PT_BVADDR(sp)
 		LONG_L	$25, PT_R25(sp)
 #ifdef CONFIG_64BIT
 		LONG_L	$8, PT_R8(sp)
 		LONG_L	$9, PT_R9(sp)
 #endif
+		MTC0	v0, CP0_BADVADDR
 		LONG_L	$7,  PT_R7(sp)
 		LONG_L	$6,  PT_R6(sp)
 		LONG_L	$5,  PT_R5(sp)
diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index 45694fe7ef..638a511fee 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -153,7 +153,8 @@ static void show_regs(const struct pt_regs *regs)
 
 	printf("Status: %08x\n", (uint32_t)regs->cp0_status);
 	printf("Cause : %08x\n", (uint32_t)regs->cp0_cause);
-	printf("Config: %08x\n\n", read_c0_config());
+	printf("Config: %08x\n", read_c0_config());
+	printf("BadVA : %0*lx\n\n", field, regs->cp0_badvaddr);
 }
 
 void barebox_exc_handler(struct pt_regs *regs)
-- 
2.41.0

[PATCH 08/21] MIPS: malta: merge GT64120 headers

[Denis Orlov]

The various definitions related to GT64120 system controller were split
between two headers: 'asm/gt64120.h' and 'mach/mach-gt64120.h'. It seems
that they were taken from Linux in this form. No reason to keep it like
that though, so unify them into 'mach/gt64120.h'.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/boards/qemu-malta/lowlevel.S          |  5 ++---
 .../asm => mach-malta/include/mach}/gt64120.h   | 13 ++++++++-----
 .../mips/mach-malta/include/mach/mach-gt64120.h | 17 -----------------
 arch/mips/mach-malta/pci.c                      |  4 +---
 4 files changed, 11 insertions(+), 28 deletions(-)
 rename arch/mips/{include/asm => mach-malta/include/mach}/gt64120.h (92%)
 delete mode 100644 arch/mips/mach-malta/include/mach/mach-gt64120.h

diff --git a/arch/mips/boards/qemu-malta/lowlevel.S b/arch/mips/boards/qemu-malta/lowlevel.S
index 541d62fc2a..09087ad916 100644
--- a/arch/mips/boards/qemu-malta/lowlevel.S
+++ b/arch/mips/boards/qemu-malta/lowlevel.S
@@ -11,10 +11,9 @@
 #include <asm/pbl_macros.h>
 #include <asm/pbl_nmon.h>
 #include <linux/sizes.h>
-
 #include <asm/addrspace.h>
-#include <asm/gt64120.h>
-#include <mach/mach-gt64120.h>
+
+#include <mach/gt64120.h>
 
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define GT_CPU_TO_LE32(x) (x)
diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/mach-malta/include/mach/gt64120.h
similarity index 92%
rename from arch/mips/include/asm/gt64120.h
rename to arch/mips/mach-malta/include/mach/gt64120.h
index 34d2382593..f8a257acb7 100644
--- a/arch/mips/include/asm/gt64120.h
+++ b/arch/mips/mach-malta/include/mach/gt64120.h
@@ -6,12 +6,15 @@
  *		 Maciej W. Rozycki <macro@mips.com>
  * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  */
-#ifndef _ASM_GT64120_H
-#define _ASM_GT64120_H
 
-#define MSK(n)			((1 << (n)) - 1)
+#ifndef _MALTA_GT64120_H
+#define _MALTA_GT64120_H
 
-#define GT_DEF_BASE		0x14000000
+#define GT_DEF_BASE	0x14000000
+#define MIPS_GT_BASE	0x1be00000
+#define GT64120_BASE	CKSEG1ADDR(MIPS_GT_BASE)
+
+#define MSK(n)		((1 << (n)) - 1)
 
 /*
  *  Register offset addresses
@@ -85,4 +88,4 @@
 #define GT_READ(ofs)		le32_to_cpu(__GT_READ(ofs))
 #define GT_WRITE(ofs, data)	__GT_WRITE(ofs, cpu_to_le32(data))
 
-#endif /* _ASM_GT64120_H */
+#endif /* _MALTA_GT64120_H */
diff --git a/arch/mips/mach-malta/include/mach/mach-gt64120.h b/arch/mips/mach-malta/include/mach/mach-gt64120.h
deleted file mode 100644
index 20ac4d94d6..0000000000
--- a/arch/mips/mach-malta/include/mach/mach-gt64120.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- *  This is a direct copy of the ev96100.h file, with a global
- * search and replace.	The numbers are the same.
- *
- *  The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H
-#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H
-
-#define MIPS_GT_BASE	0x1be00000
-
-#define GT64120_BASE    CKSEG1ADDR(MIPS_GT_BASE)
-
-#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
diff --git a/arch/mips/mach-malta/pci.c b/arch/mips/mach-malta/pci.c
index 0ab239f509..c9c1c7790b 100644
--- a/arch/mips/mach-malta/pci.c
+++ b/arch/mips/mach-malta/pci.c
@@ -7,11 +7,9 @@
 #include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/addrspace.h>
-
 #include <linux/pci.h>
-#include <asm/gt64120.h>
 
-#include <mach/mach-gt64120.h>
+#include <mach/gt64120.h>
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
-- 
2.41.0

[PATCH 09/21] MIPS: pbl_macros: use .asciiz instead of .ascii + .byte 0

[Denis Orlov]

GAS allows to use '.asciz'/'.asciiz' instead of manually writing
'.byte 0' to null-terminate the string specified in '.ascii' directive.
Do just that in 'mips_barebox_10h'. The malta-specific entry code
currently does the same.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/include/asm/pbl_macros.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index f8629d3f2c..6e177ff69a 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -170,8 +170,7 @@
 	 nop
 
 	.org	0x10
-	.ascii	"barebox"
-	.byte	0
+	.asciiz	"barebox"
 
 	.align	4
 1:
-- 
2.41.0

[PATCH 10/21] MIPS: malta: remove duplicated barebox magic code

[Denis Orlov]

Use 'mips_barebox_10h' macro instead. Remove the comment about the same
address being reserved for a Board ID as we don't really do anything
about it anyway.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/boards/qemu-malta/lowlevel.S | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/arch/mips/boards/qemu-malta/lowlevel.S b/arch/mips/boards/qemu-malta/lowlevel.S
index 09087ad916..d5d7480e21 100644
--- a/arch/mips/boards/qemu-malta/lowlevel.S
+++ b/arch/mips/boards/qemu-malta/lowlevel.S
@@ -31,17 +31,8 @@
 #define	GT_HD(x)	(GT_CPU_TO_LE32(((x) >> 21) & 0x7f))
 
 ENTRY_FUNCTION(BOARD_PBL_START)
-	b	__start
-	 nop
 
-	/*
-	   On MIPS Technologies boards
-	   0x1fc00010 address is reserved for BoardID
-	*/
-	.org	0x10
-	.asciiz	"barebox"
-
-__start:
+	mips_barebox_10h
 	mips_disable_interrupts
 
 	/* cpu specific setup ... */
-- 
2.41.0

[PATCH 11/21] MIPS: pbl: put mips_barebox_10h into ENTRY_FUNCTION

[Denis Orlov]

Remove duplicated macro calls by moving it into a common macro, as is
done in ARM code. Some boards were missing this one for no good reason,
it seems. Well, now they don't.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/boards/8devices-lima/lowlevel.S      | 2 --
 arch/mips/boards/dlink-dir-320/lowlevel.S      | 2 --
 arch/mips/boards/loongson-ls1b/lowlevel.S      | 2 --
 arch/mips/boards/netgear-wg102/lowlevel.S      | 2 --
 arch/mips/boards/qemu-malta/lowlevel.S         | 1 -
 arch/mips/boards/tplink-wdr4300/lowlevel.S     | 2 --
 arch/mips/include/asm/asm.h                    | 4 ++--
 arch/mips/mach-ath79/include/mach/pbl_macros.h | 4 ----
 8 files changed, 2 insertions(+), 17 deletions(-)

diff --git a/arch/mips/boards/8devices-lima/lowlevel.S b/arch/mips/boards/8devices-lima/lowlevel.S
index dd1ab6247d..8a4c77a44f 100644
--- a/arch/mips/boards/8devices-lima/lowlevel.S
+++ b/arch/mips/boards/8devices-lima/lowlevel.S
@@ -15,8 +15,6 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_barebox_10h
-
 	debug_ll_ath79_init
 
 	hornet_mips24k_cp0_setup
diff --git a/arch/mips/boards/dlink-dir-320/lowlevel.S b/arch/mips/boards/dlink-dir-320/lowlevel.S
index da969bc74e..7e496b50d1 100644
--- a/arch/mips/boards/dlink-dir-320/lowlevel.S
+++ b/arch/mips/boards/dlink-dir-320/lowlevel.S
@@ -13,8 +13,6 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_barebox_10h
-
 	mips_disable_interrupts
 
 	/* CPU/SoC specific setup ... */
diff --git a/arch/mips/boards/loongson-ls1b/lowlevel.S b/arch/mips/boards/loongson-ls1b/lowlevel.S
index 7240d351b4..c3d46c773b 100644
--- a/arch/mips/boards/loongson-ls1b/lowlevel.S
+++ b/arch/mips/boards/loongson-ls1b/lowlevel.S
@@ -17,8 +17,6 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_barebox_10h
-
 	mips_disable_interrupts
 
 	pbl_blt 0xbf000000 skip_pll_ram_config t0
diff --git a/arch/mips/boards/netgear-wg102/lowlevel.S b/arch/mips/boards/netgear-wg102/lowlevel.S
index e48dded269..d57b62583d 100644
--- a/arch/mips/boards/netgear-wg102/lowlevel.S
+++ b/arch/mips/boards/netgear-wg102/lowlevel.S
@@ -14,8 +14,6 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_barebox_10h
-
 	mips_disable_interrupts
 
 	pbl_ar2312_pll
diff --git a/arch/mips/boards/qemu-malta/lowlevel.S b/arch/mips/boards/qemu-malta/lowlevel.S
index d5d7480e21..8c2d82dab2 100644
--- a/arch/mips/boards/qemu-malta/lowlevel.S
+++ b/arch/mips/boards/qemu-malta/lowlevel.S
@@ -32,7 +32,6 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_barebox_10h
 	mips_disable_interrupts
 
 	/* cpu specific setup ... */
diff --git a/arch/mips/boards/tplink-wdr4300/lowlevel.S b/arch/mips/boards/tplink-wdr4300/lowlevel.S
index 8aed5ddcf1..01cc9fc212 100644
--- a/arch/mips/boards/tplink-wdr4300/lowlevel.S
+++ b/arch/mips/boards/tplink-wdr4300/lowlevel.S
@@ -15,8 +15,6 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_barebox_10h
-
 	debug_ll_ath79_init
 
 	hornet_mips24k_cp0_setup
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index c699542a55..f6daae6757 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -83,8 +83,8 @@ symbol:		.frame	sp, framesize, rpc
 	.set noreorder;					\
 	.section .text_head_entry.symbol;		\
 	.align 4;					\
-							\
-EXPORT(symbol)
+EXPORT(symbol)						\
+	mips_barebox_10h
 
 /*
  * ENTRY_FUNCTION_END - mark end of entry function
diff --git a/arch/mips/mach-ath79/include/mach/pbl_macros.h b/arch/mips/mach-ath79/include/mach/pbl_macros.h
index f101b41708..86d2cba392 100644
--- a/arch/mips/mach-ath79/include/mach/pbl_macros.h
+++ b/arch/mips/mach-ath79/include/mach/pbl_macros.h
@@ -374,8 +374,6 @@
 	.set	push
 	.set	noreorder
 
-	mips_barebox_10h
-
 	pbl_blt 0xbf000000 skip_pll_ram_config t8
 
 	hornet_mips24k_cp0_setup
@@ -406,8 +404,6 @@
 	.set	push
 	.set	noreorder
 
-	mips_barebox_10h
-
 	hornet_mips24k_cp0_setup
 
 	hornet_1_1_war
-- 
2.41.0

[PATCH 12/21] MIPS: pbl: make sure to disable interrupts/watchpoints on entry

[Denis Orlov]

The first thing that we should do on entry is to disable interrupts and
watchpoints, as who knows in what state we got there. The former was not
being done consistently on every board, while the latter was only being
done in the barebox proper for some reason. Add a macro that combines
both of those actions and ensure that it's used in every board's entry
code.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/boards/8devices-lima/lowlevel.S      |  2 ++
 arch/mips/boards/dlink-dir-320/lowlevel.S      |  2 +-
 arch/mips/boards/img-ci20/lowlevel.S           |  2 +-
 arch/mips/boards/loongson-ls1b/lowlevel.S      |  2 +-
 arch/mips/boards/netgear-wg102/lowlevel.S      |  2 +-
 arch/mips/boards/qemu-malta/lowlevel.S         |  2 +-
 arch/mips/boards/ritmix-rzx50/lowlevel.S       |  2 +-
 arch/mips/boards/tplink-wdr4300/lowlevel.S     |  2 ++
 arch/mips/include/asm/pbl_macros.h             | 16 ++++++++++++++++
 arch/mips/mach-ath79/include/mach/pbl_macros.h |  4 ++++
 10 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/arch/mips/boards/8devices-lima/lowlevel.S b/arch/mips/boards/8devices-lima/lowlevel.S
index 8a4c77a44f..fad4d8b4af 100644
--- a/arch/mips/boards/8devices-lima/lowlevel.S
+++ b/arch/mips/boards/8devices-lima/lowlevel.S
@@ -15,6 +15,8 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
+	mips_cpu_setup
+
 	debug_ll_ath79_init
 
 	hornet_mips24k_cp0_setup
diff --git a/arch/mips/boards/dlink-dir-320/lowlevel.S b/arch/mips/boards/dlink-dir-320/lowlevel.S
index 7e496b50d1..d0376c515c 100644
--- a/arch/mips/boards/dlink-dir-320/lowlevel.S
+++ b/arch/mips/boards/dlink-dir-320/lowlevel.S
@@ -13,7 +13,7 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_disable_interrupts
+	mips_cpu_setup
 
 	/* CPU/SoC specific setup ... */
 	/* ... absent */
diff --git a/arch/mips/boards/img-ci20/lowlevel.S b/arch/mips/boards/img-ci20/lowlevel.S
index 0295e44d1a..8ff9871c51 100644
--- a/arch/mips/boards/img-ci20/lowlevel.S
+++ b/arch/mips/boards/img-ci20/lowlevel.S
@@ -14,7 +14,7 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_disable_interrupts
+	mips_cpu_setup
 
 	/* CPU/SoC specific setup ... */
 	/* ... absent */
diff --git a/arch/mips/boards/loongson-ls1b/lowlevel.S b/arch/mips/boards/loongson-ls1b/lowlevel.S
index c3d46c773b..e823bb37dd 100644
--- a/arch/mips/boards/loongson-ls1b/lowlevel.S
+++ b/arch/mips/boards/loongson-ls1b/lowlevel.S
@@ -17,7 +17,7 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_disable_interrupts
+	mips_cpu_setup
 
 	pbl_blt 0xbf000000 skip_pll_ram_config t0
 
diff --git a/arch/mips/boards/netgear-wg102/lowlevel.S b/arch/mips/boards/netgear-wg102/lowlevel.S
index d57b62583d..6fdcfa3cca 100644
--- a/arch/mips/boards/netgear-wg102/lowlevel.S
+++ b/arch/mips/boards/netgear-wg102/lowlevel.S
@@ -14,7 +14,7 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_disable_interrupts
+	mips_cpu_setup
 
 	pbl_ar2312_pll
 
diff --git a/arch/mips/boards/qemu-malta/lowlevel.S b/arch/mips/boards/qemu-malta/lowlevel.S
index 8c2d82dab2..8ff7d93a74 100644
--- a/arch/mips/boards/qemu-malta/lowlevel.S
+++ b/arch/mips/boards/qemu-malta/lowlevel.S
@@ -32,7 +32,7 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_disable_interrupts
+	mips_cpu_setup
 
 	/* cpu specific setup ... */
 	/* ... absent */
diff --git a/arch/mips/boards/ritmix-rzx50/lowlevel.S b/arch/mips/boards/ritmix-rzx50/lowlevel.S
index 33810f67f5..4fccf0ddb9 100644
--- a/arch/mips/boards/ritmix-rzx50/lowlevel.S
+++ b/arch/mips/boards/ritmix-rzx50/lowlevel.S
@@ -14,7 +14,7 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
-	mips_disable_interrupts
+	mips_cpu_setup
 
 	/* CPU/SoC specific setup ... */
 	/* ... absent */
diff --git a/arch/mips/boards/tplink-wdr4300/lowlevel.S b/arch/mips/boards/tplink-wdr4300/lowlevel.S
index 01cc9fc212..94ae707b0b 100644
--- a/arch/mips/boards/tplink-wdr4300/lowlevel.S
+++ b/arch/mips/boards/tplink-wdr4300/lowlevel.S
@@ -15,6 +15,8 @@
 
 ENTRY_FUNCTION(BOARD_PBL_START)
 
+	mips_cpu_setup
+
 	debug_ll_ath79_init
 
 	hornet_mips24k_cp0_setup
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index 6e177ff69a..cc81e06a64 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -151,6 +151,14 @@
 	.set	pop
 	.endm
 
+	.macro	mips_disable_watchpoints
+	.set	push
+	.set	noreorder
+	mtc0	zero, CP0_WATCHLO
+	mtc0	zero, CP0_WATCHHI
+	.set	pop
+	.endm
+
 	.macro	mips64_enable_64bit_addressing
 #ifdef CONFIG_64BIT
 	.set	push
@@ -162,6 +170,14 @@
 #endif
 	.endm
 
+	.macro	mips_cpu_setup
+	.set	push
+	.set	noreorder
+	mips_disable_interrupts
+	mips_disable_watchpoints
+	.set	pop
+	.endm
+
 	.macro	mips_barebox_10h
 	.set	push
 	.set	noreorder
diff --git a/arch/mips/mach-ath79/include/mach/pbl_macros.h b/arch/mips/mach-ath79/include/mach/pbl_macros.h
index 86d2cba392..4b7b48618b 100644
--- a/arch/mips/mach-ath79/include/mach/pbl_macros.h
+++ b/arch/mips/mach-ath79/include/mach/pbl_macros.h
@@ -374,6 +374,8 @@
 	.set	push
 	.set	noreorder
 
+	mips_cpu_setup
+
 	pbl_blt 0xbf000000 skip_pll_ram_config t8
 
 	hornet_mips24k_cp0_setup
@@ -404,6 +406,8 @@
 	.set	push
 	.set	noreorder
 
+	mips_cpu_setup
+
 	hornet_mips24k_cp0_setup
 
 	hornet_1_1_war
-- 
2.41.0

[PATCH 13/21] MIPS: pbl: do enable 64-bit addressing in PBL

[Denis Orlov]

It seems more reasonable to do that in PBL code that initializes all the
other appropriate CP0 register bits. This also makes a corresponding
call in barebox proper entry code redundant, paving the way to its
removal.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/include/asm/pbl_macros.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index cc81e06a64..61e12cd004 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -175,6 +175,7 @@
 	.set	noreorder
 	mips_disable_interrupts
 	mips_disable_watchpoints
+	mips64_enable_64bit_addressing
 	.set	pop
 	.endm
 
-- 
2.41.0

[PATCH 14/21] MIPS: clean up barebox proper entry point

[Denis Orlov]

For MIPS, we don't actually have boards which lack PBL in the resulting
image. As such, the code in _start() is mostly redundant: the stack was
setup in ENTRY_FUNCTION_END, while copying the code to the link location
is not needed - it should already be executing at TEXT_BASE, where we
have decompressed it. Other than that, disabling interrupts with
watchpoints and enabling 64-bit addressing was already moved into PBL,
so we don't really need to repeat it there.

Replace the assembly implementation of _start() with the C one, as the
only thing it now does is jump straight into 'relocate_code()'.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/boot/start.S | 46 ------------------------------------------
 arch/mips/boot/start.c | 17 ++++++++++++++++
 2 files changed, 17 insertions(+), 46 deletions(-)
 delete mode 100644 arch/mips/boot/start.S
 create mode 100644 arch/mips/boot/start.c

diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
deleted file mode 100644
index 30828ad9ef..0000000000
--- a/arch/mips/boot/start.S
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Startup Code for MIPS CPU
- *
- * Copyright (C) 2011, 2015 Antony Pavlov <antonynpavlov@gmail.com>
- */
-
-#include <asm/pbl_macros.h>
-
-	.set noreorder
-	.section ".text_entry"
-	.align 4
-
-EXPORT(_start)
-
-	mips_barebox_10h
-
-	/* save dtb pointer */
-	move	s0, a0
-	move	s1, a1
-	move	s2, a2
-
-	/* disable watchpoints */
-	mtc0	zero, CP0_WATCHLO
-	mtc0	zero, CP0_WATCHHI
-
-	mips_disable_interrupts
-
-	mips64_enable_64bit_addressing
-
-	copy_to_link_location _start
-
-	stack_setup
-
-	/* restore dtb pointer */
-	move	a0, s0
-	move	a1, s1
-	move	a2, s2
-	PTR_LA	v0, relocate_code
-	jal	v0
-	 nop
-
-	/* No return */
-__error:
-	b __error
-	 nop
diff --git a/arch/mips/boot/start.c b/arch/mips/boot/start.c
new file mode 100644
index 0000000000..81603c8d7a
--- /dev/null
+++ b/arch/mips/boot/start.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Startup Code for MIPS CPU
+ *
+ * Copyright (C) 2011, 2015 Antony Pavlov <antonynpavlov@gmail.com>
+ */
+
+#include <linux/kernel.h>
+
+void __noreturn _start(void *fdt, u32 fdt_size, u32 relocaddr);
+void __noreturn relocate_code(void *fdt, u32 fdt_size, u32 relocaddr);
+
+void __noreturn __section(.text_entry) _start(void *fdt, u32 fdt_size,
+					      u32 relocaddr)
+{
+	relocate_code(fdt, fdt_size, relocaddr);
+}
-- 
2.41.0

[PATCH 15/21] MIPS: main_entry: properly set XTLB handler for 64-bit mode

[Denis Orlov]

The offset of the TLB Load exception is different when 64-bit addressing
is enabled - 0x80 is used instead of 0x0. To simplify things, just copy
the handler code twice, for each of the cases.

While at it, also remove the incomprehensible cpu_has_4kex check. All of
the supported CPUs have MIPS R4K compatible exception handling scheme
(and we even hardcode that), so what are we trying to achieve there
anyway?

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/boot/main_entry.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
index 99cd2ec846..237288a337 100644
--- a/arch/mips/boot/main_entry.c
+++ b/arch/mips/boot/main_entry.c
@@ -50,11 +50,9 @@ static void trap_init(void)
 		set_except_vector(i, &handle_reserved);
 	}
 
-	if (!cpu_has_4kex)
-		memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
-
 	/* FIXME: handle tlb */
 	memcpy((void *)(ebase), &except_vec3_generic, 0x80);
+	memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
 
 	/* unset BOOT EXCEPTION VECTOR bit */
 	write_c0_status(read_c0_status() & ~ST0_BEV);
-- 
2.41.0

[PATCH 16/21] MIPS: main_entry: remove exception vector array

[Denis Orlov]

This code must have been taken from Linux, where such a mechanism allows
for an efficient exception vector replacement for board-specific code.
We don't really need that. If some extensions for exception vector are
to be required, this may be done inside the generic handler code anyway.
As we are not using this code, it seems reasonable to just remove it.

Also properly calculate the size of the handler that we are copying into
the designated vectors. Originally, we just made a copy of a fixed size,
copying more than actually needed. We could have just hardcoded this
value there, as the code to copy now consists of just two instructions.
However it feels more safe to calculate that in code instead, so that we
don't have to update this value if some code is added there in the
future.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/boot/main_entry.c | 39 ++++++++-----------------------------
 arch/mips/lib/genex.S       | 29 ++++++++-------------------
 2 files changed, 16 insertions(+), 52 deletions(-)

diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
index 237288a337..d0c69f3c82 100644
--- a/arch/mips/boot/main_entry.c
+++ b/arch/mips/boot/main_entry.c
@@ -14,45 +14,22 @@
 #include <asm/addrspace.h>
 #include <linux/sizes.h>
 
-extern void handle_reserved(void);
+extern void exception_vec(void);
+extern void exception_vec_end(void);
 
 void main_entry(void *fdt, u32 fdt_size);
 
-unsigned long exception_handlers[32];
-
-static void set_except_vector(int n, void *addr)
-{
-	unsigned long handler = (unsigned long) addr;
-
-	exception_handlers[n] = handler;
-}
-
 static void trap_init(void)
 {
-	extern char except_vec3_generic;
-	int i;
-
-	unsigned long ebase;
-
-	ebase = CKSEG1;
-
-	/*
-	 * Copy the generic exception handlers to their final destination.
-	 * This will be overriden later as suitable for a particular
-	 * configuration.
-	 */
-	memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
+	const unsigned long vec_size = exception_vec_end - exception_vec;
+	const unsigned long ebase = CKSEG1;
 
-	/*
-	 * Setup default vectors
-	 */
-	for (i = 0; i <= 31; i++) {
-		set_except_vector(i, &handle_reserved);
-	}
+	 /* copy the generic exception handlers to their final destination */
+	memcpy((void *)(ebase + 0x180), &exception_vec, vec_size);
 
 	/* FIXME: handle tlb */
-	memcpy((void *)(ebase), &except_vec3_generic, 0x80);
-	memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
+	memcpy((void *)(ebase), &exception_vec, vec_size);
+	memcpy((void *)(ebase + 0x80), &exception_vec, vec_size);
 
 	/* unset BOOT EXCEPTION VECTOR bit */
 	write_c0_status(read_c0_status() & ~ST0_BEV);
diff --git a/arch/mips/lib/genex.S b/arch/mips/lib/genex.S
index b9d18fc394..27dd9de67a 100644
--- a/arch/mips/lib/genex.S
+++ b/arch/mips/lib/genex.S
@@ -2,7 +2,6 @@
 
 #include <asm/asm.h>
 #include <asm/regdef.h>
-#include <asm/mipsregs.h>
 #include <asm/stackframe.h>
 
 	.text
@@ -11,31 +10,19 @@
 	.set	noreorder
 	.align	5
 
-/* Exception vector */
-NESTED(handle_reserved, 0, sp)
+NESTED(exception_vec, 0, sp)
+	j	handle_reserved
+	 nop
+EXPORT(exception_vec_end)
+END(exception_vec)
+
+handle_reserved:
 	SAVE_ALL
 	PTR_LA	k0, barebox_exc_handler
-	jal	k0
+	j	k0
 	 move	a0, sp
-	/* will never return here */
-	END(handle_reserved)
-
-/* General exception vector */
-NESTED(except_vec3_generic, 0, sp)
-	.set	noat
-	mfc0	k1, CP0_CAUSE
-	PTR_LA	k0, exception_handlers
-	andi	k1, k1, 0x7c
-	PTR_ADDU	k0, k0, k1
-	PTR_L	k0, (k0)
-	nop
-	jr	k0
-	 nop
-	END(except_vec3_generic)
-	.set	at
 
 FEXPORT(ret_from_exception)
 	.set	noat
 	RESTORE_ALL_AND_RET
-	 nop
 	.set	at
-- 
2.41.0

[PATCH 17/21] MIPS: c-r4k: prettify code in __BUILD_BLAST_CACHE_RANGE

[Denis Orlov]

Even though the original code was taken from Linux, it is quite old and
crufty. Replace the 'while (1)' loop with the 'for' one, use const for
constant variables and use ALIGN_DOWN macro instead of repeating its
code.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/lib/c-r4k.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index 8bc0a7a411..6389ab9be2 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -27,19 +27,16 @@
 static inline void blast_##pfx##cache##_range(unsigned long start,	\
 					      unsigned long end)	\
 {									\
-	unsigned long lsize = current_cpu_data.desc.linesz;		\
-	unsigned long addr = start & ~(lsize - 1);			\
-	unsigned long aend = (end - 1) & ~(lsize - 1);			\
+	const unsigned long lsize = current_cpu_data.desc.linesz;	\
+	const unsigned long astart = ALIGN_DOWN(start, lsize);		\
+	const unsigned long aend = ALIGN_DOWN(end - 1, lsize);		\
+	unsigned long addr;						\
 									\
 	if (current_cpu_data.desc.flags & MIPS_CACHE_NOT_PRESENT)	\
 		return;							\
 									\
-	while (1) {							\
+	for (addr = astart; addr <= aend; addr += lsize)		\
 		cache_op(hitop, addr);					\
-		if (addr == aend)					\
-			break;						\
-		addr += lsize;						\
-	}								\
 }
 
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
-- 
2.41.0

[PATCH 18/21] MIPS: c-r4k: generate blast_*cache functions via macros

[Denis Orlov]

This gets us rid of this logic repeated in 'flush_cache_all()' for each
cache and allows to use blast_*cache funcs elsewhere if such a need
arises.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/lib/c-r4k.c | 41 ++++++++++++++++++++++++-----------------
 1 file changed, 24 insertions(+), 17 deletions(-)

diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index 6389ab9be2..d3855bd756 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -13,6 +13,8 @@
 #include <asm/cpu-info.h>
 #include <asm/bitops.h>
 
+#define INDEX_BASE	CKSEG0
+
 #define cache_op(op,addr)						\
 	__asm__ __volatile__(						\
 	"	.set	push					\n"	\
@@ -23,6 +25,23 @@
 	:								\
 	: "i" (op), "R" (*(unsigned char *)(addr)))
 
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop)				\
+static inline void blast_##pfx##cache(void)				\
+{									\
+	const unsigned long lsize = current_cpu_data.desc.linesz;	\
+	const unsigned long start = INDEX_BASE;				\
+	const unsigned long size = current_cpu_data.desc.waysize	\
+				   * current_cpu_data.desc.ways;	\
+	const unsigned long aend = start + size - 1;			\
+	unsigned long addr;						\
+									\
+	if (current_cpu_data.desc.flags & MIPS_CACHE_NOT_PRESENT)	\
+		return;							\
+									\
+	for (addr = start; addr <= aend; addr += lsize)			\
+		cache_op(indexop, addr);				\
+}
+
 #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop)			\
 static inline void blast_##pfx##cache##_range(unsigned long start,	\
 					      unsigned long end)	\
@@ -39,28 +58,16 @@ static inline void blast_##pfx##cache##_range(unsigned long start,	\
 		cache_op(hitop, addr);					\
 }
 
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D)
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I)
+
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
 __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D)
 
 void flush_cache_all(void)
 {
-	struct cpuinfo_mips *c = &current_cpu_data;
-	unsigned long lsize;
-	unsigned long addr;
-	unsigned long aend;
-	unsigned int icache_size, dcache_size;
-
-	dcache_size = c->dcache.waysize * c->dcache.ways;
-	lsize = c->dcache.linesz;
-	aend = (CKSEG0 + dcache_size - 1) & ~(lsize - 1);
-	for (addr = CKSEG0; addr <= aend; addr += lsize)
-		cache_op(Index_Writeback_Inv_D, addr);
-
-	icache_size = c->icache.waysize * c->icache.ways;
-	lsize = c->icache.linesz;
-	aend = (CKSEG0 + icache_size - 1) & ~(lsize - 1);
-	for (addr = CKSEG0; addr <= aend; addr += lsize)
-		cache_op(Index_Invalidate_I, addr);
+	blast_dcache();
+	blast_icache();
 
 	/* secondatory cache skipped */
 }
-- 
2.41.0

[PATCH 19/21] MIPS: c-r4k: do flush secondary cache

[Denis Orlov]

Even though we probe for the secondary cache, we don't actually utilize
it when flushing. It seems that the reason for this is that no MIPS
board currently supported in barebox actually has secondary caches and
thus requires the additional logic in handling them.

Add the required functions and calls to them. This will make it easier
to add support for boards that do happen to have secondary caches.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/include/asm/cacheops.h |  5 +++++
 arch/mips/lib/c-r4k.c            | 12 ++++++------
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 9f60e0287d..1e4e361e22 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -12,6 +12,7 @@
  */
 #define Cache_I				0x00
 #define Cache_D				0x01
+#define Cache_SD			0x03
 
 #define Index_Writeback_Inv		0x00
 #define Index_Store_Tag			0x08
@@ -23,9 +24,13 @@
  */
 #define Index_Invalidate_I		(Cache_I | Index_Writeback_Inv)
 #define Index_Writeback_Inv_D		(Cache_D | Index_Writeback_Inv)
+#define Index_Writeback_Inv_SD		(Cache_SD | Index_Writeback_Inv)
 #define Index_Store_Tag_I		(Cache_I | Index_Store_Tag)
 #define Index_Store_Tag_D		(Cache_D | Index_Store_Tag)
+#define Index_Store_Tag_SD		(Cache_SD | Index_Store_Tag)
 #define Hit_Invalidate_D		(Cache_D | Hit_Invalidate)
+#define Hit_Invalidate_SD		(Cache_SD | Hit_Invalidate)
 #define Hit_Writeback_Inv_D		(Cache_D | Hit_Writeback_Inv)
+#define Hit_Writeback_Inv_SD		(Cache_SD | Hit_Writeback_Inv)
 
 #endif	/* __ASM_CACHEOPS_H */
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index d3855bd756..2fb4e90138 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -60,30 +60,30 @@ static inline void blast_##pfx##cache##_range(unsigned long start,	\
 
 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D)
 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I)
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD)
 
 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD)
 __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D)
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD)
 
 void flush_cache_all(void)
 {
 	blast_dcache();
 	blast_icache();
-
-	/* secondatory cache skipped */
+	blast_scache();
 }
 
 void dma_flush_range(unsigned long start, unsigned long end)
 {
 	blast_dcache_range(start, end);
-
-	/* secondatory cache skipped */
+	blast_scache_range(start, end);
 }
 
 void dma_inv_range(unsigned long start, unsigned long end)
 {
 	blast_inv_dcache_range(start, end);
-
-	/* secondatory cache skipped */
+	blast_inv_scache_range(start, end);
 }
 
 void r4k_cache_init(void);
-- 
2.41.0

[PATCH 20/21] MIPS: c-r4k: remove extra function declaration

[Denis Orlov]

'r4k_cache_init()' is already declared in the appropriate 'asm/cache.h'
header.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/lib/c-r4k.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index 2fb4e90138..44cf57d99b 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -86,8 +86,6 @@ void dma_inv_range(unsigned long start, unsigned long end)
 	blast_inv_scache_range(start, end);
 }
 
-void r4k_cache_init(void);
-
 static void probe_pcache(void)
 {
 	struct cpuinfo_mips *c = &current_cpu_data;
-- 
2.41.0

[PATCH 21/21] MIPS: reloc: use IS_ALIGNED macro to check for an alignment

[Denis Orlov]

Improves the code readability a tiny little bit.

Signed-off-by: Denis Orlov <denorl2009@gmail.com>
---
 arch/mips/lib/reloc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
index 83b4040d95..a9078aa813 100644
--- a/arch/mips/lib/reloc.c
+++ b/arch/mips/lib/reloc.c
@@ -133,7 +133,7 @@ void __noreturn relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
 	 * space in the Barebox binary & complexity in handling them.
 	 */
 	off = relocaddr - (unsigned long)__image_start;
-	if (off & 0xffff)
+	if (!IS_ALIGNED(off, SZ_64K))
 		panic("Mis-aligned relocation\n");
 
 	/* Copy Barebox to RAM */
-- 
2.41.0

Re: [PATCH 00/21] MIPS: semi-random code improvements

[Sascha Hauer]

On Tue, Jul 25, 2023 at 08:05:01AM +0300, Denis Orlov wrote:
> Denis Orlov (21):
>   MIPS: addrspace: rectify ksseg segment naming
>   MIPS: addrspace: simplify the header
>   MIPS: main_entry-pbl: remove unused variable
>   MIPS: barebox.lds: remove extra whitespace
>   MIPS: reloc: mark relocate_code() as noreturn
>   MIPS: cpuinfo: use appropriate format specifiers in printf
>   MIPS: print BadVAddr CP0 register on exception
>   MIPS: malta: merge GT64120 headers
>   MIPS: pbl_macros: use .asciiz instead of .ascii + .byte 0
>   MIPS: malta: remove duplicated barebox magic code
>   MIPS: pbl: put mips_barebox_10h into ENTRY_FUNCTION
>   MIPS: pbl: make sure to disable interrupts/watchpoints on entry
>   MIPS: pbl: do enable 64-bit addressing in PBL
>   MIPS: clean up barebox proper entry point
>   MIPS: main_entry: properly set XTLB handler for 64-bit mode
>   MIPS: main_entry: remove exception vector array
>   MIPS: c-r4k: prettify code in __BUILD_BLAST_CACHE_RANGE
>   MIPS: c-r4k: generate blast_*cache functions via macros
>   MIPS: c-r4k: do flush secondary cache
>   MIPS: c-r4k: remove extra function declaration
>   MIPS: reloc: use IS_ALIGNED macro to check for an alignment

Applied, thanks

Sascha

> 
>  arch/mips/boards/8devices-lima/lowlevel.S     |  2 +-
>  arch/mips/boards/dlink-dir-320/lowlevel.S     |  4 +-
>  arch/mips/boards/img-ci20/lowlevel.S          |  2 +-
>  arch/mips/boards/loongson-ls1b/lowlevel.S     |  4 +-
>  arch/mips/boards/netgear-wg102/lowlevel.S     |  4 +-
>  arch/mips/boards/qemu-malta/lowlevel.S        | 17 +----
>  arch/mips/boards/ritmix-rzx50/lowlevel.S      |  2 +-
>  arch/mips/boards/tplink-wdr4300/lowlevel.S    |  2 +-
>  arch/mips/boot/main_entry-pbl.c               |  4 --
>  arch/mips/boot/main_entry.c                   | 41 +++--------
>  arch/mips/boot/start.S                        | 46 -------------
>  arch/mips/boot/start.c                        | 17 +++++
>  arch/mips/include/asm/addrspace.h             | 47 ++++++-------
>  arch/mips/include/asm/asm.h                   |  4 +-
>  arch/mips/include/asm/cacheops.h              |  5 ++
>  arch/mips/include/asm/pbl_macros.h            | 20 +++++-
>  arch/mips/include/asm/stackframe.h            |  4 ++
>  arch/mips/lib/barebox.lds.S                   |  2 -
>  arch/mips/lib/c-r4k.c                         | 68 ++++++++++---------
>  arch/mips/lib/cpuinfo.c                       |  6 +-
>  arch/mips/lib/genex.S                         | 29 +++-----
>  arch/mips/lib/reloc.c                         |  6 +-
>  arch/mips/lib/traps.c                         |  3 +-
>  .../mips/mach-ath79/include/mach/pbl_macros.h |  4 +-
>  .../asm => mach-malta/include/mach}/gt64120.h | 13 ++--
>  .../mach-malta/include/mach/mach-gt64120.h    | 17 -----
>  arch/mips/mach-malta/pci.c                    |  4 +-
>  27 files changed, 147 insertions(+), 230 deletions(-)
>  delete mode 100644 arch/mips/boot/start.S
>  create mode 100644 arch/mips/boot/start.c
>  rename arch/mips/{include/asm => mach-malta/include/mach}/gt64120.h (92%)
>  delete mode 100644 arch/mips/mach-malta/include/mach/mach-gt64120.h
> 
> -- 
> 2.41.0
> 
> 

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