Re: [PATCH v3] ARM: add Skov i.MX8MP based board support

[Sascha Hauer <sha@pengutronix.de>]

On Mon, Aug 14, 2023 at 02:12:34PM +0200, Oleksij Rempel wrote:
> Add basic support for the Skov i.MX8MP based system.
> This is initial support and will be extended later at least with board version
> detection.
> 
> The compatible used in the board file is for barebox specific generic
> devicetree which is expected to work with all Skov i.MX8MP based boards.
> 
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

Applied, thanks

Sascha

> ---
> changes v3:
> - use i.MX8MP instead of i.MX8M
> - add this board to *v8_defconfig files
> 
> changes v2:
> - remove board dependency on DSA and KSZ9477 drivers
> - add notice about generic board support
> 
>  arch/arm/boards/Makefile                      |    1 +
>  arch/arm/boards/skov-imx8mp/Makefile          |    4 +
>  arch/arm/boards/skov-imx8mp/board.c           |   43 +
>  .../flash-header-skov-imx8mp.imxcfg           |    7 +
>  arch/arm/boards/skov-imx8mp/lowlevel.c        |  142 ++
>  arch/arm/boards/skov-imx8mp/lpddr4-timing.c   | 1849 +++++++++++++++++
>  arch/arm/configs/imx_v8_defconfig             |    1 +
>  arch/arm/configs/multi_v8_defconfig           |    1 +
>  arch/arm/dts/Makefile                         |    1 +
>  arch/arm/dts/imx8mp-skov.dts                  |  518 +++++
>  arch/arm/mach-imx/Kconfig                     |   10 +
>  images/Makefile.imx                           |    5 +
>  12 files changed, 2582 insertions(+)
>  create mode 100644 arch/arm/boards/skov-imx8mp/Makefile
>  create mode 100644 arch/arm/boards/skov-imx8mp/board.c
>  create mode 100644 arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg
>  create mode 100644 arch/arm/boards/skov-imx8mp/lowlevel.c
>  create mode 100644 arch/arm/boards/skov-imx8mp/lpddr4-timing.c
>  create mode 100644 arch/arm/dts/imx8mp-skov.dts
> 
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index 382e649fce..83a3179185 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -115,6 +115,7 @@ obj-$(CONFIG_MACH_SABRELITE)			+= freescale-mx6-sabrelite/
>  obj-$(CONFIG_MACH_SABRESD)			+= freescale-mx6-sabresd/
>  obj-$(CONFIG_MACH_AC_SXB)			+= ac-sxb/
>  obj-$(CONFIG_MACH_SKOV_IMX6)			+= skov-imx6/
> +obj-$(CONFIG_MACH_SKOV_IMX8MP)			+= skov-imx8mp/
>  obj-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB)	+= freescale-mx6sx-sabresdb/
>  obj-$(CONFIG_MACH_SAMA5D27_GIANTBOARD)		+= sama5d27-giantboard/
>  obj-$(CONFIG_MACH_SAMA5D27_SOM1)		+= sama5d27-som1/
> diff --git a/arch/arm/boards/skov-imx8mp/Makefile b/arch/arm/boards/skov-imx8mp/Makefile
> new file mode 100644
> index 0000000000..35d8640087
> --- /dev/null
> +++ b/arch/arm/boards/skov-imx8mp/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +obj-y += board.o
> +lwl-y += lowlevel.o lpddr4-timing.o
> diff --git a/arch/arm/boards/skov-imx8mp/board.c b/arch/arm/boards/skov-imx8mp/board.c
> new file mode 100644
> index 0000000000..398c74677d
> --- /dev/null
> +++ b/arch/arm/boards/skov-imx8mp/board.c
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <bootsource.h>
> +#include <common.h>
> +#include <deep-probe.h>
> +#include <envfs.h>
> +#include <init.h>
> +#include <io.h>
> +#include <mach/imx/bbu.h>
> +#include <mach/imx/iomux-mx8mp.h>
> +
> +static int skov_imx8mp_probe(struct device *dev)
> +{
> +	int emmc_bbu_flag = 0;
> +	int sd_bbu_flag = 0;
> +
> +	if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() == 1) {
> +		of_device_enable_path("/chosen/environment-sd");
> +		sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
> +	} else {
> +		of_device_enable_path("/chosen/environment-emmc");
> +		emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
> +	}
> +
> +	imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", sd_bbu_flag);
> +	imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", emmc_bbu_flag);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id skov_imx8mp_of_match[] = {
> +	/* generic, barebox specific compatible for all board variants */
> +	{ .compatible = "skov,imx8mp" },
> +	{ /* Sentinel */ }
> +};
> +BAREBOX_DEEP_PROBE_ENABLE(skov_imx8mp_of_match);
> +
> +static struct driver skov_imx8mp_board_driver = {
> +	.name = "skov-imx8m",
> +	.probe = skov_imx8mp_probe,
> +	.of_compatible = skov_imx8mp_of_match,
> +};
> +coredevice_platform_driver(skov_imx8mp_board_driver);
> diff --git a/arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg b/arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg
> new file mode 100644
> index 0000000000..663bd102e9
> --- /dev/null
> +++ b/arch/arm/boards/skov-imx8mp/flash-header-skov-imx8mp.imxcfg
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +soc imx8mp
> +
> +loadaddr 0x920000
> +max_load_size 0x3f000
> +ivtofs 0x0
> diff --git a/arch/arm/boards/skov-imx8mp/lowlevel.c b/arch/arm/boards/skov-imx8mp/lowlevel.c
> new file mode 100644
> index 0000000000..c35ffe526d
> --- /dev/null
> +++ b/arch/arm/boards/skov-imx8mp/lowlevel.c
> @@ -0,0 +1,142 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <asm/barebox-arm.h>
> +#include <asm/barebox-arm-head.h>
> +#include <common.h>
> +#include <debug_ll.h>
> +#include <mach/imx/debug_ll.h>
> +#include <mach/imx/atf.h>
> +#include <mach/imx/esdctl.h>
> +#include <mach/imx/generic.h>
> +#include <mach/imx/imx8m-ccm-regs.h>
> +#include <mach/imx/imx8mp-regs.h>
> +#include <mach/imx/iomux-mx8mp.h>
> +#include <mach/imx/xload.h>
> +#include <mfd/pca9450.h>
> +#include <pbl/i2c.h>
> +#include <pbl/pmic.h>
> +#include <soc/imx8m/ddr.h>
> +
> +extern char __dtb_z_imx8mp_skov_start[];
> +
> +#define UART_PAD_CTRL   MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
> +				     MX8MP_PAD_CTL_FSEL | \
> +				     MX8MP_PAD_CTL_PUE | \
> +				     MX8MP_PAD_CTL_PE)
> +
> +#define I2C_PAD_CTRL	MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \
> +				     MX8MP_PAD_CTL_HYS | \
> +				     MX8MP_PAD_CTL_PUE | \
> +				     MX8MP_PAD_CTL_PE)
> +
> +static void setup_uart(void)
> +{
> +	void __iomem *uart = IOMEM(MX8M_UART2_BASE_ADDR);
> +
> +	imx8m_early_setup_uart_clock();
> +
> +	imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL);
> +	imx8mp_setup_pad(MX8MP_PAD_UART2_RXD__UART2_DCE_RX | UART_PAD_CTRL);
> +	imx8m_uart_setup(uart);
> +
> +	pbl_set_putc(imx_uart_putc, uart);
> +
> +	putc_ll('>');
> +}
> +
> +static struct pmic_config pca9450_cfg[] = {
> +	/* BUCKxOUT_DVS0/1 control BUCK123 output */
> +	{ PCA9450_BUCK123_DVS, 0x29 },
> +	/*
> +	 * increase VDD_SOC to typical value 0.95V before first
> +	 * DRAM access, set DVS1 to 0.85v for suspend.
> +	 * Enable DVS control through PMIC_STBY_REQ and
> +	 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
> +	 */
> +	{ PCA9450_BUCK1OUT_DVS0, 0x1C },
> +	{ PCA9450_BUCK1OUT_DVS1, 0x14 },
> +	{ PCA9450_BUCK1CTRL, 0x59 },
> +	/*
> +	 * Increase VDD_ARM to 0.95V to avoid issues in case software after
> +	 * Barebox switches to the OD ARM frequency without reprogramming the
> +	 * PMIC first.
> +	 */
> +	{ PCA9450_BUCK2OUT_DVS0, 0x1C },
> +	/* set WDOG_B_CFG to cold reset */
> +	{ PCA9450_RESET_CTRL, 0xA1 },
> +};
> +
> +static void power_init_board(void)
> +{
> +	struct pbl_i2c *i2c;
> +
> +	imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL);
> +	imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL);
> +
> +	imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1);
> +
> +	i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR));
> +
> +	pmic_configure(i2c, 0x25, pca9450_cfg, ARRAY_SIZE(pca9450_cfg));
> +}
> +
> +extern struct dram_timing_info imx8mp_skov_dram_timing;
> +
> +static void start_atf(struct dram_timing_info *dram_timing)
> +{
> +	/*
> +	 * If we are in EL3 we are running for the first time and need to
> +	 * initialize the DRAM and run TF-A (BL31). The TF-A will then jump
> +	 * to DRAM in EL2.
> +	 */
> +	if (current_el() != 3)
> +		return;
> +
> +	imx8mp_early_clock_init();
> +
> +	power_init_board();
> +
> +	imx8mp_ddr_init(dram_timing, DRAM_TYPE_LPDDR4);
> +
> +	imx8mp_load_and_start_image_via_tfa();
> +}
> +
> +/*
> + * Power-on execution flow of imx8mp_skov_start() might not be
> + * obvious for a very first read, so here's, hopefully helpful,
> + * summary:
> + *
> + * 1. MaskROM uploads PBL into OCRAM and that's where this function is
> + *    executed for the first time. At entry the exception level is EL3.
> + *
> + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL
> + *    part is copied from OCRAM to the TF-A return address in DRAM.
> + *
> + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us
> + *    from EL3 to EL2.
> + *
> + * 4. Standard barebox boot flow continues
> + */
> +static __noreturn noinline void
> +imx8mp_skov_start(struct dram_timing_info *dram_timing, void *dtb)
> +{
> +	setup_uart();
> +
> +	start_atf(dram_timing);
> +
> +	/*
> +	 * Standard entry we hit once we initialized both DDR and ATF
> +	 */
> +	imx8mp_barebox_entry(dtb);
> +}
> +
> +ENTRY_FUNCTION(start_skov_imx8mp, r0, r1, r2)
> +{
> +	imx8mp_cpu_lowlevel_init();
> +
> +	relocate_to_current_adr();
> +	setup_c();
> +
> +	imx8mp_skov_start(&imx8mp_skov_dram_timing,
> +			   __dtb_z_imx8mp_skov_start);
> +}
> diff --git a/arch/arm/boards/skov-imx8mp/lpddr4-timing.c b/arch/arm/boards/skov-imx8mp/lpddr4-timing.c
> new file mode 100644
> index 0000000000..6a896bc677
> --- /dev/null
> +++ b/arch/arm/boards/skov-imx8mp/lpddr4-timing.c
> @@ -0,0 +1,1849 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright 2019 NXP
> + *
> + * Generated code from MX8M_DDR_tool
> + */
> +
> +#include <common.h>
> +#include <soc/imx8m/ddr.h>
> +#include <soc/imx8m/lpddr4_define.h>
> +
> +static struct dram_cfg_param ddr_ddrc_cfg[] = {
> +	/** Initialize DDRC registers **/
> +	{ 0x3d400304, 0x1 },
> +	{ 0x3d400030, 0x1 },
> +	{ 0x3d400000, 0xa1080020 },
> +	{ 0x3d400020, 0x1223 },
> +	{ 0x3d400024, 0x16e3600 },
> +	{ 0x3d400064, 0x5b00d2 },
> +	{ 0x3d400070, 0x7027f90 },
> +	{ 0x3d400074, 0x790 },
> +	{ 0x3d4000d0, 0xc00305ba },
> +	{ 0x3d4000d4, 0x940000 },
> +	{ 0x3d4000dc, 0xd4002d },
> +	{ 0x3d4000e0, 0x310000 },
> +	{ 0x3d4000e8, 0x660048 },
> +	{ 0x3d4000ec, 0x160048 },
> +	{ 0x3d400100, 0x191e1920 },
> +	{ 0x3d400104, 0x60630 },
> +	{ 0x3d40010c, 0xb0b000 },
> +	{ 0x3d400110, 0xe04080e },
> +	{ 0x3d400114, 0x2040c0c },
> +	{ 0x3d400118, 0x1010007 },
> +	{ 0x3d40011c, 0x402 },
> +	{ 0x3d400130, 0x20600 },
> +	{ 0x3d400134, 0xc100002 },
> +	{ 0x3d400138, 0xd8 },
> +	{ 0x3d400144, 0x96004b },
> +	{ 0x3d400180, 0x2ee0017 },
> +	{ 0x3d400184, 0x2605b8e },
> +	{ 0x3d400188, 0x0 },
> +	{ 0x3d400190, 0x497820a },
> +	{ 0x3d400194, 0x80303 },
> +	{ 0x3d4001b4, 0x170a },
> +	{ 0x3d4001a0, 0xe0400018 },
> +	{ 0x3d4001a4, 0xdf00e4 },
> +	{ 0x3d4001a8, 0x80000000 },
> +	{ 0x3d4001b0, 0x11 },
> +	{ 0x3d4001c0, 0x1 },
> +	{ 0x3d4001c4, 0x1 },
> +	{ 0x3d4000f4, 0x699 },
> +	{ 0x3d400108, 0x70e1617 },
> +	{ 0x3d400200, 0x1f },
> +	{ 0x3d400208, 0x0 },
> +	{ 0x3d40020c, 0x0 },
> +	{ 0x3d400210, 0x1f1f },
> +	{ 0x3d400204, 0x80808 },
> +	{ 0x3d400214, 0x7070707 },
> +	{ 0x3d400218, 0x7070707 },
> +	{ 0x3d40021c, 0xf0f },
> +	{ 0x3d400250, 0x1705 },
> +	{ 0x3d400254, 0x2c },
> +	{ 0x3d40025c, 0x4000030 },
> +	{ 0x3d400264, 0x900093e7 },
> +	{ 0x3d40026c, 0x2005574 },
> +	{ 0x3d400400, 0x111 },
> +	{ 0x3d400404, 0x72ff },
> +	{ 0x3d400408, 0x72ff },
> +	{ 0x3d400494, 0x2100e07 },
> +	{ 0x3d400498, 0x620096 },
> +	{ 0x3d40049c, 0x1100e07 },
> +	{ 0x3d4004a0, 0xc8012c },
> +	{ 0x3d402020, 0x1021 },
> +	{ 0x3d402024, 0x30d400 },
> +	{ 0x3d402050, 0x20d000 },
> +	{ 0x3d402064, 0xc001c },
> +	{ 0x3d4020dc, 0x840000 },
> +	{ 0x3d4020e0, 0x330000 },
> +	{ 0x3d4020e8, 0x660048 },
> +	{ 0x3d4020ec, 0x160048 },
> +	{ 0x3d402100, 0xa040305 },
> +	{ 0x3d402104, 0x30407 },
> +	{ 0x3d402108, 0x203060b },
> +	{ 0x3d40210c, 0x505000 },
> +	{ 0x3d402110, 0x2040202 },
> +	{ 0x3d402114, 0x2030202 },
> +	{ 0x3d402118, 0x1010004 },
> +	{ 0x3d40211c, 0x302 },
> +	{ 0x3d402130, 0x20300 },
> +	{ 0x3d402134, 0xa100002 },
> +	{ 0x3d402138, 0x1d },
> +	{ 0x3d402144, 0x14000a },
> +	{ 0x3d402180, 0x640004 },
> +	{ 0x3d402190, 0x3818200 },
> +	{ 0x3d402194, 0x80303 },
> +	{ 0x3d4021b4, 0x100 },
> +	{ 0x3d4020f4, 0x599 },
> +	{ 0x3d403020, 0x1021 },
> +	{ 0x3d403024, 0xc3500 },
> +	{ 0x3d403050, 0x20d000 },
> +	{ 0x3d403064, 0x30007 },
> +	{ 0x3d4030dc, 0x840000 },
> +	{ 0x3d4030e0, 0x330000 },
> +	{ 0x3d4030e8, 0x660048 },
> +	{ 0x3d4030ec, 0x160048 },
> +	{ 0x3d403100, 0xa010102 },
> +	{ 0x3d403104, 0x30404 },
> +	{ 0x3d403108, 0x203060b },
> +	{ 0x3d40310c, 0x505000 },
> +	{ 0x3d403110, 0x2040202 },
> +	{ 0x3d403114, 0x2030202 },
> +	{ 0x3d403118, 0x1010004 },
> +	{ 0x3d40311c, 0x302 },
> +	{ 0x3d403130, 0x20300 },
> +	{ 0x3d403134, 0xa100002 },
> +	{ 0x3d403138, 0x8 },
> +	{ 0x3d403144, 0x50003 },
> +	{ 0x3d403180, 0x190004 },
> +	{ 0x3d403190, 0x3818200 },
> +	{ 0x3d403194, 0x80303 },
> +	{ 0x3d4031b4, 0x100 },
> +	{ 0x3d4030f4, 0x599 },
> +	{ 0x3d400028, 0x0 },
> +};
> +
> +/* PHY Initialize Configuration */
> +static struct dram_cfg_param ddr_ddrphy_cfg[] = {
> +	{ 0x100a0, 0x0 },
> +	{ 0x100a1, 0x1 },
> +	{ 0x100a2, 0x2 },
> +	{ 0x100a3, 0x3 },
> +	{ 0x100a4, 0x4 },
> +	{ 0x100a5, 0x5 },
> +	{ 0x100a6, 0x6 },
> +	{ 0x100a7, 0x7 },
> +	{ 0x110a0, 0x0 },
> +	{ 0x110a1, 0x1 },
> +	{ 0x110a2, 0x3 },
> +	{ 0x110a3, 0x4 },
> +	{ 0x110a4, 0x5 },
> +	{ 0x110a5, 0x2 },
> +	{ 0x110a6, 0x7 },
> +	{ 0x110a7, 0x6 },
> +	{ 0x120a0, 0x0 },
> +	{ 0x120a1, 0x1 },
> +	{ 0x120a2, 0x3 },
> +	{ 0x120a3, 0x2 },
> +	{ 0x120a4, 0x5 },
> +	{ 0x120a5, 0x4 },
> +	{ 0x120a6, 0x7 },
> +	{ 0x120a7, 0x6 },
> +	{ 0x130a0, 0x0 },
> +	{ 0x130a1, 0x1 },
> +	{ 0x130a2, 0x2 },
> +	{ 0x130a3, 0x3 },
> +	{ 0x130a4, 0x4 },
> +	{ 0x130a5, 0x5 },
> +	{ 0x130a6, 0x6 },
> +	{ 0x130a7, 0x7 },
> +	{ 0x1005f, 0x1ff },
> +	{ 0x1015f, 0x1ff },
> +	{ 0x1105f, 0x1ff },
> +	{ 0x1115f, 0x1ff },
> +	{ 0x1205f, 0x1ff },
> +	{ 0x1215f, 0x1ff },
> +	{ 0x1305f, 0x1ff },
> +	{ 0x1315f, 0x1ff },
> +	{ 0x11005f, 0x1ff },
> +	{ 0x11015f, 0x1ff },
> +	{ 0x11105f, 0x1ff },
> +	{ 0x11115f, 0x1ff },
> +	{ 0x11205f, 0x1ff },
> +	{ 0x11215f, 0x1ff },
> +	{ 0x11305f, 0x1ff },
> +	{ 0x11315f, 0x1ff },
> +	{ 0x21005f, 0x1ff },
> +	{ 0x21015f, 0x1ff },
> +	{ 0x21105f, 0x1ff },
> +	{ 0x21115f, 0x1ff },
> +	{ 0x21205f, 0x1ff },
> +	{ 0x21215f, 0x1ff },
> +	{ 0x21305f, 0x1ff },
> +	{ 0x21315f, 0x1ff },
> +	{ 0x55, 0x1ff },
> +	{ 0x1055, 0x1ff },
> +	{ 0x2055, 0x1ff },
> +	{ 0x3055, 0x1ff },
> +	{ 0x4055, 0x1ff },
> +	{ 0x5055, 0x1ff },
> +	{ 0x6055, 0x1ff },
> +	{ 0x7055, 0x1ff },
> +	{ 0x8055, 0x1ff },
> +	{ 0x9055, 0x1ff },
> +	{ 0x200c5, 0x19 },
> +	{ 0x1200c5, 0x7 },
> +	{ 0x2200c5, 0x7 },
> +	{ 0x2002e, 0x2 },
> +	{ 0x12002e, 0x2 },
> +	{ 0x22002e, 0x2 },
> +	{ 0x90204, 0x0 },
> +	{ 0x190204, 0x0 },
> +	{ 0x290204, 0x0 },
> +	{ 0x20024, 0x1a3 },
> +	{ 0x2003a, 0x2 },
> +	{ 0x120024, 0x1a3 },
> +	{ 0x2003a, 0x2 },
> +	{ 0x220024, 0x1a3 },
> +	{ 0x2003a, 0x2 },
> +	{ 0x20056, 0x3 },
> +	{ 0x120056, 0x3 },
> +	{ 0x220056, 0x3 },
> +	{ 0x1004d, 0xe00 },
> +	{ 0x1014d, 0xe00 },
> +	{ 0x1104d, 0xe00 },
> +	{ 0x1114d, 0xe00 },
> +	{ 0x1204d, 0xe00 },
> +	{ 0x1214d, 0xe00 },
> +	{ 0x1304d, 0xe00 },
> +	{ 0x1314d, 0xe00 },
> +	{ 0x11004d, 0xe00 },
> +	{ 0x11014d, 0xe00 },
> +	{ 0x11104d, 0xe00 },
> +	{ 0x11114d, 0xe00 },
> +	{ 0x11204d, 0xe00 },
> +	{ 0x11214d, 0xe00 },
> +	{ 0x11304d, 0xe00 },
> +	{ 0x11314d, 0xe00 },
> +	{ 0x21004d, 0xe00 },
> +	{ 0x21014d, 0xe00 },
> +	{ 0x21104d, 0xe00 },
> +	{ 0x21114d, 0xe00 },
> +	{ 0x21204d, 0xe00 },
> +	{ 0x21214d, 0xe00 },
> +	{ 0x21304d, 0xe00 },
> +	{ 0x21314d, 0xe00 },
> +	{ 0x10049, 0xeba },
> +	{ 0x10149, 0xeba },
> +	{ 0x11049, 0xeba },
> +	{ 0x11149, 0xeba },
> +	{ 0x12049, 0xeba },
> +	{ 0x12149, 0xeba },
> +	{ 0x13049, 0xeba },
> +	{ 0x13149, 0xeba },
> +	{ 0x110049, 0xeba },
> +	{ 0x110149, 0xeba },
> +	{ 0x111049, 0xeba },
> +	{ 0x111149, 0xeba },
> +	{ 0x112049, 0xeba },
> +	{ 0x112149, 0xeba },
> +	{ 0x113049, 0xeba },
> +	{ 0x113149, 0xeba },
> +	{ 0x210049, 0xeba },
> +	{ 0x210149, 0xeba },
> +	{ 0x211049, 0xeba },
> +	{ 0x211149, 0xeba },
> +	{ 0x212049, 0xeba },
> +	{ 0x212149, 0xeba },
> +	{ 0x213049, 0xeba },
> +	{ 0x213149, 0xeba },
> +	{ 0x43, 0x63 },
> +	{ 0x1043, 0x63 },
> +	{ 0x2043, 0x63 },
> +	{ 0x3043, 0x63 },
> +	{ 0x4043, 0x63 },
> +	{ 0x5043, 0x63 },
> +	{ 0x6043, 0x63 },
> +	{ 0x7043, 0x63 },
> +	{ 0x8043, 0x63 },
> +	{ 0x9043, 0x63 },
> +	{ 0x20018, 0x3 },
> +	{ 0x20075, 0x4 },
> +	{ 0x20050, 0x0 },
> +	{ 0x20008, 0x2ee },
> +	{ 0x120008, 0x64 },
> +	{ 0x220008, 0x19 },
> +	{ 0x20088, 0x9 },
> +	{ 0x200b2, 0x104 },
> +	{ 0x10043, 0x5a1 },
> +	{ 0x10143, 0x5a1 },
> +	{ 0x11043, 0x5a1 },
> +	{ 0x11143, 0x5a1 },
> +	{ 0x12043, 0x5a1 },
> +	{ 0x12143, 0x5a1 },
> +	{ 0x13043, 0x5a1 },
> +	{ 0x13143, 0x5a1 },
> +	{ 0x1200b2, 0x104 },
> +	{ 0x110043, 0x5a1 },
> +	{ 0x110143, 0x5a1 },
> +	{ 0x111043, 0x5a1 },
> +	{ 0x111143, 0x5a1 },
> +	{ 0x112043, 0x5a1 },
> +	{ 0x112143, 0x5a1 },
> +	{ 0x113043, 0x5a1 },
> +	{ 0x113143, 0x5a1 },
> +	{ 0x2200b2, 0x104 },
> +	{ 0x210043, 0x5a1 },
> +	{ 0x210143, 0x5a1 },
> +	{ 0x211043, 0x5a1 },
> +	{ 0x211143, 0x5a1 },
> +	{ 0x212043, 0x5a1 },
> +	{ 0x212143, 0x5a1 },
> +	{ 0x213043, 0x5a1 },
> +	{ 0x213143, 0x5a1 },
> +	{ 0x200fa, 0x1 },
> +	{ 0x1200fa, 0x1 },
> +	{ 0x2200fa, 0x1 },
> +	{ 0x20019, 0x1 },
> +	{ 0x120019, 0x1 },
> +	{ 0x220019, 0x1 },
> +	{ 0x200f0, 0x660 },
> +	{ 0x200f1, 0x0 },
> +	{ 0x200f2, 0x4444 },
> +	{ 0x200f3, 0x8888 },
> +	{ 0x200f4, 0x5665 },
> +	{ 0x200f5, 0x0 },
> +	{ 0x200f6, 0x0 },
> +	{ 0x200f7, 0xf000 },
> +	{ 0x20025, 0x0 },
> +	{ 0x2002d, 0x0 },
> +	{ 0x12002d, 0x0 },
> +	{ 0x22002d, 0x0 },
> +	{ 0x2007d, 0x212 },
> +	{ 0x12007d, 0x212 },
> +	{ 0x22007d, 0x212 },
> +	{ 0x2007c, 0x61 },
> +	{ 0x12007c, 0x61 },
> +	{ 0x22007c, 0x61 },
> +	{ 0x1004a, 0x500 },
> +	{ 0x1104a, 0x500 },
> +	{ 0x1204a, 0x500 },
> +	{ 0x1304a, 0x500 },
> +	{ 0x2002c, 0x0 },
> +};
> +
> +/* ddr phy trained csr */
> +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
> +	{ 0x200b2, 0x0 },
> +	{ 0x1200b2, 0x0 },
> +	{ 0x2200b2, 0x0 },
> +	{ 0x200cb, 0x0 },
> +	{ 0x10043, 0x0 },
> +	{ 0x110043, 0x0 },
> +	{ 0x210043, 0x0 },
> +	{ 0x10143, 0x0 },
> +	{ 0x110143, 0x0 },
> +	{ 0x210143, 0x0 },
> +	{ 0x11043, 0x0 },
> +	{ 0x111043, 0x0 },
> +	{ 0x211043, 0x0 },
> +	{ 0x11143, 0x0 },
> +	{ 0x111143, 0x0 },
> +	{ 0x211143, 0x0 },
> +	{ 0x12043, 0x0 },
> +	{ 0x112043, 0x0 },
> +	{ 0x212043, 0x0 },
> +	{ 0x12143, 0x0 },
> +	{ 0x112143, 0x0 },
> +	{ 0x212143, 0x0 },
> +	{ 0x13043, 0x0 },
> +	{ 0x113043, 0x0 },
> +	{ 0x213043, 0x0 },
> +	{ 0x13143, 0x0 },
> +	{ 0x113143, 0x0 },
> +	{ 0x213143, 0x0 },
> +	{ 0x80, 0x0 },
> +	{ 0x100080, 0x0 },
> +	{ 0x200080, 0x0 },
> +	{ 0x1080, 0x0 },
> +	{ 0x101080, 0x0 },
> +	{ 0x201080, 0x0 },
> +	{ 0x2080, 0x0 },
> +	{ 0x102080, 0x0 },
> +	{ 0x202080, 0x0 },
> +	{ 0x3080, 0x0 },
> +	{ 0x103080, 0x0 },
> +	{ 0x203080, 0x0 },
> +	{ 0x4080, 0x0 },
> +	{ 0x104080, 0x0 },
> +	{ 0x204080, 0x0 },
> +	{ 0x5080, 0x0 },
> +	{ 0x105080, 0x0 },
> +	{ 0x205080, 0x0 },
> +	{ 0x6080, 0x0 },
> +	{ 0x106080, 0x0 },
> +	{ 0x206080, 0x0 },
> +	{ 0x7080, 0x0 },
> +	{ 0x107080, 0x0 },
> +	{ 0x207080, 0x0 },
> +	{ 0x8080, 0x0 },
> +	{ 0x108080, 0x0 },
> +	{ 0x208080, 0x0 },
> +	{ 0x9080, 0x0 },
> +	{ 0x109080, 0x0 },
> +	{ 0x209080, 0x0 },
> +	{ 0x10080, 0x0 },
> +	{ 0x110080, 0x0 },
> +	{ 0x210080, 0x0 },
> +	{ 0x10180, 0x0 },
> +	{ 0x110180, 0x0 },
> +	{ 0x210180, 0x0 },
> +	{ 0x11080, 0x0 },
> +	{ 0x111080, 0x0 },
> +	{ 0x211080, 0x0 },
> +	{ 0x11180, 0x0 },
> +	{ 0x111180, 0x0 },
> +	{ 0x211180, 0x0 },
> +	{ 0x12080, 0x0 },
> +	{ 0x112080, 0x0 },
> +	{ 0x212080, 0x0 },
> +	{ 0x12180, 0x0 },
> +	{ 0x112180, 0x0 },
> +	{ 0x212180, 0x0 },
> +	{ 0x13080, 0x0 },
> +	{ 0x113080, 0x0 },
> +	{ 0x213080, 0x0 },
> +	{ 0x13180, 0x0 },
> +	{ 0x113180, 0x0 },
> +	{ 0x213180, 0x0 },
> +	{ 0x10081, 0x0 },
> +	{ 0x110081, 0x0 },
> +	{ 0x210081, 0x0 },
> +	{ 0x10181, 0x0 },
> +	{ 0x110181, 0x0 },
> +	{ 0x210181, 0x0 },
> +	{ 0x11081, 0x0 },
> +	{ 0x111081, 0x0 },
> +	{ 0x211081, 0x0 },
> +	{ 0x11181, 0x0 },
> +	{ 0x111181, 0x0 },
> +	{ 0x211181, 0x0 },
> +	{ 0x12081, 0x0 },
> +	{ 0x112081, 0x0 },
> +	{ 0x212081, 0x0 },
> +	{ 0x12181, 0x0 },
> +	{ 0x112181, 0x0 },
> +	{ 0x212181, 0x0 },
> +	{ 0x13081, 0x0 },
> +	{ 0x113081, 0x0 },
> +	{ 0x213081, 0x0 },
> +	{ 0x13181, 0x0 },
> +	{ 0x113181, 0x0 },
> +	{ 0x213181, 0x0 },
> +	{ 0x100d0, 0x0 },
> +	{ 0x1100d0, 0x0 },
> +	{ 0x2100d0, 0x0 },
> +	{ 0x101d0, 0x0 },
> +	{ 0x1101d0, 0x0 },
> +	{ 0x2101d0, 0x0 },
> +	{ 0x110d0, 0x0 },
> +	{ 0x1110d0, 0x0 },
> +	{ 0x2110d0, 0x0 },
> +	{ 0x111d0, 0x0 },
> +	{ 0x1111d0, 0x0 },
> +	{ 0x2111d0, 0x0 },
> +	{ 0x120d0, 0x0 },
> +	{ 0x1120d0, 0x0 },
> +	{ 0x2120d0, 0x0 },
> +	{ 0x121d0, 0x0 },
> +	{ 0x1121d0, 0x0 },
> +	{ 0x2121d0, 0x0 },
> +	{ 0x130d0, 0x0 },
> +	{ 0x1130d0, 0x0 },
> +	{ 0x2130d0, 0x0 },
> +	{ 0x131d0, 0x0 },
> +	{ 0x1131d0, 0x0 },
> +	{ 0x2131d0, 0x0 },
> +	{ 0x100d1, 0x0 },
> +	{ 0x1100d1, 0x0 },
> +	{ 0x2100d1, 0x0 },
> +	{ 0x101d1, 0x0 },
> +	{ 0x1101d1, 0x0 },
> +	{ 0x2101d1, 0x0 },
> +	{ 0x110d1, 0x0 },
> +	{ 0x1110d1, 0x0 },
> +	{ 0x2110d1, 0x0 },
> +	{ 0x111d1, 0x0 },
> +	{ 0x1111d1, 0x0 },
> +	{ 0x2111d1, 0x0 },
> +	{ 0x120d1, 0x0 },
> +	{ 0x1120d1, 0x0 },
> +	{ 0x2120d1, 0x0 },
> +	{ 0x121d1, 0x0 },
> +	{ 0x1121d1, 0x0 },
> +	{ 0x2121d1, 0x0 },
> +	{ 0x130d1, 0x0 },
> +	{ 0x1130d1, 0x0 },
> +	{ 0x2130d1, 0x0 },
> +	{ 0x131d1, 0x0 },
> +	{ 0x1131d1, 0x0 },
> +	{ 0x2131d1, 0x0 },
> +	{ 0x10068, 0x0 },
> +	{ 0x10168, 0x0 },
> +	{ 0x10268, 0x0 },
> +	{ 0x10368, 0x0 },
> +	{ 0x10468, 0x0 },
> +	{ 0x10568, 0x0 },
> +	{ 0x10668, 0x0 },
> +	{ 0x10768, 0x0 },
> +	{ 0x10868, 0x0 },
> +	{ 0x11068, 0x0 },
> +	{ 0x11168, 0x0 },
> +	{ 0x11268, 0x0 },
> +	{ 0x11368, 0x0 },
> +	{ 0x11468, 0x0 },
> +	{ 0x11568, 0x0 },
> +	{ 0x11668, 0x0 },
> +	{ 0x11768, 0x0 },
> +	{ 0x11868, 0x0 },
> +	{ 0x12068, 0x0 },
> +	{ 0x12168, 0x0 },
> +	{ 0x12268, 0x0 },
> +	{ 0x12368, 0x0 },
> +	{ 0x12468, 0x0 },
> +	{ 0x12568, 0x0 },
> +	{ 0x12668, 0x0 },
> +	{ 0x12768, 0x0 },
> +	{ 0x12868, 0x0 },
> +	{ 0x13068, 0x0 },
> +	{ 0x13168, 0x0 },
> +	{ 0x13268, 0x0 },
> +	{ 0x13368, 0x0 },
> +	{ 0x13468, 0x0 },
> +	{ 0x13568, 0x0 },
> +	{ 0x13668, 0x0 },
> +	{ 0x13768, 0x0 },
> +	{ 0x13868, 0x0 },
> +	{ 0x10069, 0x0 },
> +	{ 0x10169, 0x0 },
> +	{ 0x10269, 0x0 },
> +	{ 0x10369, 0x0 },
> +	{ 0x10469, 0x0 },
> +	{ 0x10569, 0x0 },
> +	{ 0x10669, 0x0 },
> +	{ 0x10769, 0x0 },
> +	{ 0x10869, 0x0 },
> +	{ 0x11069, 0x0 },
> +	{ 0x11169, 0x0 },
> +	{ 0x11269, 0x0 },
> +	{ 0x11369, 0x0 },
> +	{ 0x11469, 0x0 },
> +	{ 0x11569, 0x0 },
> +	{ 0x11669, 0x0 },
> +	{ 0x11769, 0x0 },
> +	{ 0x11869, 0x0 },
> +	{ 0x12069, 0x0 },
> +	{ 0x12169, 0x0 },
> +	{ 0x12269, 0x0 },
> +	{ 0x12369, 0x0 },
> +	{ 0x12469, 0x0 },
> +	{ 0x12569, 0x0 },
> +	{ 0x12669, 0x0 },
> +	{ 0x12769, 0x0 },
> +	{ 0x12869, 0x0 },
> +	{ 0x13069, 0x0 },
> +	{ 0x13169, 0x0 },
> +	{ 0x13269, 0x0 },
> +	{ 0x13369, 0x0 },
> +	{ 0x13469, 0x0 },
> +	{ 0x13569, 0x0 },
> +	{ 0x13669, 0x0 },
> +	{ 0x13769, 0x0 },
> +	{ 0x13869, 0x0 },
> +	{ 0x1008c, 0x0 },
> +	{ 0x11008c, 0x0 },
> +	{ 0x21008c, 0x0 },
> +	{ 0x1018c, 0x0 },
> +	{ 0x11018c, 0x0 },
> +	{ 0x21018c, 0x0 },
> +	{ 0x1108c, 0x0 },
> +	{ 0x11108c, 0x0 },
> +	{ 0x21108c, 0x0 },
> +	{ 0x1118c, 0x0 },
> +	{ 0x11118c, 0x0 },
> +	{ 0x21118c, 0x0 },
> +	{ 0x1208c, 0x0 },
> +	{ 0x11208c, 0x0 },
> +	{ 0x21208c, 0x0 },
> +	{ 0x1218c, 0x0 },
> +	{ 0x11218c, 0x0 },
> +	{ 0x21218c, 0x0 },
> +	{ 0x1308c, 0x0 },
> +	{ 0x11308c, 0x0 },
> +	{ 0x21308c, 0x0 },
> +	{ 0x1318c, 0x0 },
> +	{ 0x11318c, 0x0 },
> +	{ 0x21318c, 0x0 },
> +	{ 0x1008d, 0x0 },
> +	{ 0x11008d, 0x0 },
> +	{ 0x21008d, 0x0 },
> +	{ 0x1018d, 0x0 },
> +	{ 0x11018d, 0x0 },
> +	{ 0x21018d, 0x0 },
> +	{ 0x1108d, 0x0 },
> +	{ 0x11108d, 0x0 },
> +	{ 0x21108d, 0x0 },
> +	{ 0x1118d, 0x0 },
> +	{ 0x11118d, 0x0 },
> +	{ 0x21118d, 0x0 },
> +	{ 0x1208d, 0x0 },
> +	{ 0x11208d, 0x0 },
> +	{ 0x21208d, 0x0 },
> +	{ 0x1218d, 0x0 },
> +	{ 0x11218d, 0x0 },
> +	{ 0x21218d, 0x0 },
> +	{ 0x1308d, 0x0 },
> +	{ 0x11308d, 0x0 },
> +	{ 0x21308d, 0x0 },
> +	{ 0x1318d, 0x0 },
> +	{ 0x11318d, 0x0 },
> +	{ 0x21318d, 0x0 },
> +	{ 0x100c0, 0x0 },
> +	{ 0x1100c0, 0x0 },
> +	{ 0x2100c0, 0x0 },
> +	{ 0x101c0, 0x0 },
> +	{ 0x1101c0, 0x0 },
> +	{ 0x2101c0, 0x0 },
> +	{ 0x102c0, 0x0 },
> +	{ 0x1102c0, 0x0 },
> +	{ 0x2102c0, 0x0 },
> +	{ 0x103c0, 0x0 },
> +	{ 0x1103c0, 0x0 },
> +	{ 0x2103c0, 0x0 },
> +	{ 0x104c0, 0x0 },
> +	{ 0x1104c0, 0x0 },
> +	{ 0x2104c0, 0x0 },
> +	{ 0x105c0, 0x0 },
> +	{ 0x1105c0, 0x0 },
> +	{ 0x2105c0, 0x0 },
> +	{ 0x106c0, 0x0 },
> +	{ 0x1106c0, 0x0 },
> +	{ 0x2106c0, 0x0 },
> +	{ 0x107c0, 0x0 },
> +	{ 0x1107c0, 0x0 },
> +	{ 0x2107c0, 0x0 },
> +	{ 0x108c0, 0x0 },
> +	{ 0x1108c0, 0x0 },
> +	{ 0x2108c0, 0x0 },
> +	{ 0x110c0, 0x0 },
> +	{ 0x1110c0, 0x0 },
> +	{ 0x2110c0, 0x0 },
> +	{ 0x111c0, 0x0 },
> +	{ 0x1111c0, 0x0 },
> +	{ 0x2111c0, 0x0 },
> +	{ 0x112c0, 0x0 },
> +	{ 0x1112c0, 0x0 },
> +	{ 0x2112c0, 0x0 },
> +	{ 0x113c0, 0x0 },
> +	{ 0x1113c0, 0x0 },
> +	{ 0x2113c0, 0x0 },
> +	{ 0x114c0, 0x0 },
> +	{ 0x1114c0, 0x0 },
> +	{ 0x2114c0, 0x0 },
> +	{ 0x115c0, 0x0 },
> +	{ 0x1115c0, 0x0 },
> +	{ 0x2115c0, 0x0 },
> +	{ 0x116c0, 0x0 },
> +	{ 0x1116c0, 0x0 },
> +	{ 0x2116c0, 0x0 },
> +	{ 0x117c0, 0x0 },
> +	{ 0x1117c0, 0x0 },
> +	{ 0x2117c0, 0x0 },
> +	{ 0x118c0, 0x0 },
> +	{ 0x1118c0, 0x0 },
> +	{ 0x2118c0, 0x0 },
> +	{ 0x120c0, 0x0 },
> +	{ 0x1120c0, 0x0 },
> +	{ 0x2120c0, 0x0 },
> +	{ 0x121c0, 0x0 },
> +	{ 0x1121c0, 0x0 },
> +	{ 0x2121c0, 0x0 },
> +	{ 0x122c0, 0x0 },
> +	{ 0x1122c0, 0x0 },
> +	{ 0x2122c0, 0x0 },
> +	{ 0x123c0, 0x0 },
> +	{ 0x1123c0, 0x0 },
> +	{ 0x2123c0, 0x0 },
> +	{ 0x124c0, 0x0 },
> +	{ 0x1124c0, 0x0 },
> +	{ 0x2124c0, 0x0 },
> +	{ 0x125c0, 0x0 },
> +	{ 0x1125c0, 0x0 },
> +	{ 0x2125c0, 0x0 },
> +	{ 0x126c0, 0x0 },
> +	{ 0x1126c0, 0x0 },
> +	{ 0x2126c0, 0x0 },
> +	{ 0x127c0, 0x0 },
> +	{ 0x1127c0, 0x0 },
> +	{ 0x2127c0, 0x0 },
> +	{ 0x128c0, 0x0 },
> +	{ 0x1128c0, 0x0 },
> +	{ 0x2128c0, 0x0 },
> +	{ 0x130c0, 0x0 },
> +	{ 0x1130c0, 0x0 },
> +	{ 0x2130c0, 0x0 },
> +	{ 0x131c0, 0x0 },
> +	{ 0x1131c0, 0x0 },
> +	{ 0x2131c0, 0x0 },
> +	{ 0x132c0, 0x0 },
> +	{ 0x1132c0, 0x0 },
> +	{ 0x2132c0, 0x0 },
> +	{ 0x133c0, 0x0 },
> +	{ 0x1133c0, 0x0 },
> +	{ 0x2133c0, 0x0 },
> +	{ 0x134c0, 0x0 },
> +	{ 0x1134c0, 0x0 },
> +	{ 0x2134c0, 0x0 },
> +	{ 0x135c0, 0x0 },
> +	{ 0x1135c0, 0x0 },
> +	{ 0x2135c0, 0x0 },
> +	{ 0x136c0, 0x0 },
> +	{ 0x1136c0, 0x0 },
> +	{ 0x2136c0, 0x0 },
> +	{ 0x137c0, 0x0 },
> +	{ 0x1137c0, 0x0 },
> +	{ 0x2137c0, 0x0 },
> +	{ 0x138c0, 0x0 },
> +	{ 0x1138c0, 0x0 },
> +	{ 0x2138c0, 0x0 },
> +	{ 0x100c1, 0x0 },
> +	{ 0x1100c1, 0x0 },
> +	{ 0x2100c1, 0x0 },
> +	{ 0x101c1, 0x0 },
> +	{ 0x1101c1, 0x0 },
> +	{ 0x2101c1, 0x0 },
> +	{ 0x102c1, 0x0 },
> +	{ 0x1102c1, 0x0 },
> +	{ 0x2102c1, 0x0 },
> +	{ 0x103c1, 0x0 },
> +	{ 0x1103c1, 0x0 },
> +	{ 0x2103c1, 0x0 },
> +	{ 0x104c1, 0x0 },
> +	{ 0x1104c1, 0x0 },
> +	{ 0x2104c1, 0x0 },
> +	{ 0x105c1, 0x0 },
> +	{ 0x1105c1, 0x0 },
> +	{ 0x2105c1, 0x0 },
> +	{ 0x106c1, 0x0 },
> +	{ 0x1106c1, 0x0 },
> +	{ 0x2106c1, 0x0 },
> +	{ 0x107c1, 0x0 },
> +	{ 0x1107c1, 0x0 },
> +	{ 0x2107c1, 0x0 },
> +	{ 0x108c1, 0x0 },
> +	{ 0x1108c1, 0x0 },
> +	{ 0x2108c1, 0x0 },
> +	{ 0x110c1, 0x0 },
> +	{ 0x1110c1, 0x0 },
> +	{ 0x2110c1, 0x0 },
> +	{ 0x111c1, 0x0 },
> +	{ 0x1111c1, 0x0 },
> +	{ 0x2111c1, 0x0 },
> +	{ 0x112c1, 0x0 },
> +	{ 0x1112c1, 0x0 },
> +	{ 0x2112c1, 0x0 },
> +	{ 0x113c1, 0x0 },
> +	{ 0x1113c1, 0x0 },
> +	{ 0x2113c1, 0x0 },
> +	{ 0x114c1, 0x0 },
> +	{ 0x1114c1, 0x0 },
> +	{ 0x2114c1, 0x0 },
> +	{ 0x115c1, 0x0 },
> +	{ 0x1115c1, 0x0 },
> +	{ 0x2115c1, 0x0 },
> +	{ 0x116c1, 0x0 },
> +	{ 0x1116c1, 0x0 },
> +	{ 0x2116c1, 0x0 },
> +	{ 0x117c1, 0x0 },
> +	{ 0x1117c1, 0x0 },
> +	{ 0x2117c1, 0x0 },
> +	{ 0x118c1, 0x0 },
> +	{ 0x1118c1, 0x0 },
> +	{ 0x2118c1, 0x0 },
> +	{ 0x120c1, 0x0 },
> +	{ 0x1120c1, 0x0 },
> +	{ 0x2120c1, 0x0 },
> +	{ 0x121c1, 0x0 },
> +	{ 0x1121c1, 0x0 },
> +	{ 0x2121c1, 0x0 },
> +	{ 0x122c1, 0x0 },
> +	{ 0x1122c1, 0x0 },
> +	{ 0x2122c1, 0x0 },
> +	{ 0x123c1, 0x0 },
> +	{ 0x1123c1, 0x0 },
> +	{ 0x2123c1, 0x0 },
> +	{ 0x124c1, 0x0 },
> +	{ 0x1124c1, 0x0 },
> +	{ 0x2124c1, 0x0 },
> +	{ 0x125c1, 0x0 },
> +	{ 0x1125c1, 0x0 },
> +	{ 0x2125c1, 0x0 },
> +	{ 0x126c1, 0x0 },
> +	{ 0x1126c1, 0x0 },
> +	{ 0x2126c1, 0x0 },
> +	{ 0x127c1, 0x0 },
> +	{ 0x1127c1, 0x0 },
> +	{ 0x2127c1, 0x0 },
> +	{ 0x128c1, 0x0 },
> +	{ 0x1128c1, 0x0 },
> +	{ 0x2128c1, 0x0 },
> +	{ 0x130c1, 0x0 },
> +	{ 0x1130c1, 0x0 },
> +	{ 0x2130c1, 0x0 },
> +	{ 0x131c1, 0x0 },
> +	{ 0x1131c1, 0x0 },
> +	{ 0x2131c1, 0x0 },
> +	{ 0x132c1, 0x0 },
> +	{ 0x1132c1, 0x0 },
> +	{ 0x2132c1, 0x0 },
> +	{ 0x133c1, 0x0 },
> +	{ 0x1133c1, 0x0 },
> +	{ 0x2133c1, 0x0 },
> +	{ 0x134c1, 0x0 },
> +	{ 0x1134c1, 0x0 },
> +	{ 0x2134c1, 0x0 },
> +	{ 0x135c1, 0x0 },
> +	{ 0x1135c1, 0x0 },
> +	{ 0x2135c1, 0x0 },
> +	{ 0x136c1, 0x0 },
> +	{ 0x1136c1, 0x0 },
> +	{ 0x2136c1, 0x0 },
> +	{ 0x137c1, 0x0 },
> +	{ 0x1137c1, 0x0 },
> +	{ 0x2137c1, 0x0 },
> +	{ 0x138c1, 0x0 },
> +	{ 0x1138c1, 0x0 },
> +	{ 0x2138c1, 0x0 },
> +	{ 0x10020, 0x0 },
> +	{ 0x110020, 0x0 },
> +	{ 0x210020, 0x0 },
> +	{ 0x11020, 0x0 },
> +	{ 0x111020, 0x0 },
> +	{ 0x211020, 0x0 },
> +	{ 0x12020, 0x0 },
> +	{ 0x112020, 0x0 },
> +	{ 0x212020, 0x0 },
> +	{ 0x13020, 0x0 },
> +	{ 0x113020, 0x0 },
> +	{ 0x213020, 0x0 },
> +	{ 0x20072, 0x0 },
> +	{ 0x20073, 0x0 },
> +	{ 0x20074, 0x0 },
> +	{ 0x100aa, 0x0 },
> +	{ 0x110aa, 0x0 },
> +	{ 0x120aa, 0x0 },
> +	{ 0x130aa, 0x0 },
> +	{ 0x20010, 0x0 },
> +	{ 0x120010, 0x0 },
> +	{ 0x220010, 0x0 },
> +	{ 0x20011, 0x0 },
> +	{ 0x120011, 0x0 },
> +	{ 0x220011, 0x0 },
> +	{ 0x100ae, 0x0 },
> +	{ 0x1100ae, 0x0 },
> +	{ 0x2100ae, 0x0 },
> +	{ 0x100af, 0x0 },
> +	{ 0x1100af, 0x0 },
> +	{ 0x2100af, 0x0 },
> +	{ 0x110ae, 0x0 },
> +	{ 0x1110ae, 0x0 },
> +	{ 0x2110ae, 0x0 },
> +	{ 0x110af, 0x0 },
> +	{ 0x1110af, 0x0 },
> +	{ 0x2110af, 0x0 },
> +	{ 0x120ae, 0x0 },
> +	{ 0x1120ae, 0x0 },
> +	{ 0x2120ae, 0x0 },
> +	{ 0x120af, 0x0 },
> +	{ 0x1120af, 0x0 },
> +	{ 0x2120af, 0x0 },
> +	{ 0x130ae, 0x0 },
> +	{ 0x1130ae, 0x0 },
> +	{ 0x2130ae, 0x0 },
> +	{ 0x130af, 0x0 },
> +	{ 0x1130af, 0x0 },
> +	{ 0x2130af, 0x0 },
> +	{ 0x20020, 0x0 },
> +	{ 0x120020, 0x0 },
> +	{ 0x220020, 0x0 },
> +	{ 0x100a0, 0x0 },
> +	{ 0x100a1, 0x0 },
> +	{ 0x100a2, 0x0 },
> +	{ 0x100a3, 0x0 },
> +	{ 0x100a4, 0x0 },
> +	{ 0x100a5, 0x0 },
> +	{ 0x100a6, 0x0 },
> +	{ 0x100a7, 0x0 },
> +	{ 0x110a0, 0x0 },
> +	{ 0x110a1, 0x0 },
> +	{ 0x110a2, 0x0 },
> +	{ 0x110a3, 0x0 },
> +	{ 0x110a4, 0x0 },
> +	{ 0x110a5, 0x0 },
> +	{ 0x110a6, 0x0 },
> +	{ 0x110a7, 0x0 },
> +	{ 0x120a0, 0x0 },
> +	{ 0x120a1, 0x0 },
> +	{ 0x120a2, 0x0 },
> +	{ 0x120a3, 0x0 },
> +	{ 0x120a4, 0x0 },
> +	{ 0x120a5, 0x0 },
> +	{ 0x120a6, 0x0 },
> +	{ 0x120a7, 0x0 },
> +	{ 0x130a0, 0x0 },
> +	{ 0x130a1, 0x0 },
> +	{ 0x130a2, 0x0 },
> +	{ 0x130a3, 0x0 },
> +	{ 0x130a4, 0x0 },
> +	{ 0x130a5, 0x0 },
> +	{ 0x130a6, 0x0 },
> +	{ 0x130a7, 0x0 },
> +	{ 0x2007c, 0x0 },
> +	{ 0x12007c, 0x0 },
> +	{ 0x22007c, 0x0 },
> +	{ 0x2007d, 0x0 },
> +	{ 0x12007d, 0x0 },
> +	{ 0x22007d, 0x0 },
> +	{ 0x400fd, 0x0 },
> +	{ 0x400c0, 0x0 },
> +	{ 0x90201, 0x0 },
> +	{ 0x190201, 0x0 },
> +	{ 0x290201, 0x0 },
> +	{ 0x90202, 0x0 },
> +	{ 0x190202, 0x0 },
> +	{ 0x290202, 0x0 },
> +	{ 0x90203, 0x0 },
> +	{ 0x190203, 0x0 },
> +	{ 0x290203, 0x0 },
> +	{ 0x90204, 0x0 },
> +	{ 0x190204, 0x0 },
> +	{ 0x290204, 0x0 },
> +	{ 0x90205, 0x0 },
> +	{ 0x190205, 0x0 },
> +	{ 0x290205, 0x0 },
> +	{ 0x90206, 0x0 },
> +	{ 0x190206, 0x0 },
> +	{ 0x290206, 0x0 },
> +	{ 0x90207, 0x0 },
> +	{ 0x190207, 0x0 },
> +	{ 0x290207, 0x0 },
> +	{ 0x90208, 0x0 },
> +	{ 0x190208, 0x0 },
> +	{ 0x290208, 0x0 },
> +	{ 0x10062, 0x0 },
> +	{ 0x10162, 0x0 },
> +	{ 0x10262, 0x0 },
> +	{ 0x10362, 0x0 },
> +	{ 0x10462, 0x0 },
> +	{ 0x10562, 0x0 },
> +	{ 0x10662, 0x0 },
> +	{ 0x10762, 0x0 },
> +	{ 0x10862, 0x0 },
> +	{ 0x11062, 0x0 },
> +	{ 0x11162, 0x0 },
> +	{ 0x11262, 0x0 },
> +	{ 0x11362, 0x0 },
> +	{ 0x11462, 0x0 },
> +	{ 0x11562, 0x0 },
> +	{ 0x11662, 0x0 },
> +	{ 0x11762, 0x0 },
> +	{ 0x11862, 0x0 },
> +	{ 0x12062, 0x0 },
> +	{ 0x12162, 0x0 },
> +	{ 0x12262, 0x0 },
> +	{ 0x12362, 0x0 },
> +	{ 0x12462, 0x0 },
> +	{ 0x12562, 0x0 },
> +	{ 0x12662, 0x0 },
> +	{ 0x12762, 0x0 },
> +	{ 0x12862, 0x0 },
> +	{ 0x13062, 0x0 },
> +	{ 0x13162, 0x0 },
> +	{ 0x13262, 0x0 },
> +	{ 0x13362, 0x0 },
> +	{ 0x13462, 0x0 },
> +	{ 0x13562, 0x0 },
> +	{ 0x13662, 0x0 },
> +	{ 0x13762, 0x0 },
> +	{ 0x13862, 0x0 },
> +	{ 0x20077, 0x0 },
> +	{ 0x10001, 0x0 },
> +	{ 0x11001, 0x0 },
> +	{ 0x12001, 0x0 },
> +	{ 0x13001, 0x0 },
> +	{ 0x10040, 0x0 },
> +	{ 0x10140, 0x0 },
> +	{ 0x10240, 0x0 },
> +	{ 0x10340, 0x0 },
> +	{ 0x10440, 0x0 },
> +	{ 0x10540, 0x0 },
> +	{ 0x10640, 0x0 },
> +	{ 0x10740, 0x0 },
> +	{ 0x10840, 0x0 },
> +	{ 0x10030, 0x0 },
> +	{ 0x10130, 0x0 },
> +	{ 0x10230, 0x0 },
> +	{ 0x10330, 0x0 },
> +	{ 0x10430, 0x0 },
> +	{ 0x10530, 0x0 },
> +	{ 0x10630, 0x0 },
> +	{ 0x10730, 0x0 },
> +	{ 0x10830, 0x0 },
> +	{ 0x11040, 0x0 },
> +	{ 0x11140, 0x0 },
> +	{ 0x11240, 0x0 },
> +	{ 0x11340, 0x0 },
> +	{ 0x11440, 0x0 },
> +	{ 0x11540, 0x0 },
> +	{ 0x11640, 0x0 },
> +	{ 0x11740, 0x0 },
> +	{ 0x11840, 0x0 },
> +	{ 0x11030, 0x0 },
> +	{ 0x11130, 0x0 },
> +	{ 0x11230, 0x0 },
> +	{ 0x11330, 0x0 },
> +	{ 0x11430, 0x0 },
> +	{ 0x11530, 0x0 },
> +	{ 0x11630, 0x0 },
> +	{ 0x11730, 0x0 },
> +	{ 0x11830, 0x0 },
> +	{ 0x12040, 0x0 },
> +	{ 0x12140, 0x0 },
> +	{ 0x12240, 0x0 },
> +	{ 0x12340, 0x0 },
> +	{ 0x12440, 0x0 },
> +	{ 0x12540, 0x0 },
> +	{ 0x12640, 0x0 },
> +	{ 0x12740, 0x0 },
> +	{ 0x12840, 0x0 },
> +	{ 0x12030, 0x0 },
> +	{ 0x12130, 0x0 },
> +	{ 0x12230, 0x0 },
> +	{ 0x12330, 0x0 },
> +	{ 0x12430, 0x0 },
> +	{ 0x12530, 0x0 },
> +	{ 0x12630, 0x0 },
> +	{ 0x12730, 0x0 },
> +	{ 0x12830, 0x0 },
> +	{ 0x13040, 0x0 },
> +	{ 0x13140, 0x0 },
> +	{ 0x13240, 0x0 },
> +	{ 0x13340, 0x0 },
> +	{ 0x13440, 0x0 },
> +	{ 0x13540, 0x0 },
> +	{ 0x13640, 0x0 },
> +	{ 0x13740, 0x0 },
> +	{ 0x13840, 0x0 },
> +	{ 0x13030, 0x0 },
> +	{ 0x13130, 0x0 },
> +	{ 0x13230, 0x0 },
> +	{ 0x13330, 0x0 },
> +	{ 0x13430, 0x0 },
> +	{ 0x13530, 0x0 },
> +	{ 0x13630, 0x0 },
> +	{ 0x13730, 0x0 },
> +	{ 0x13830, 0x0 },
> +};
> +/* P0 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54003, 0xbb8 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x131f },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54012, 0x110 },
> +	{ 0x54019, 0x2dd4 },
> +	{ 0x5401a, 0x31 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x2dd4 },
> +	{ 0x54020, 0x31 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x1 },
> +	{ 0x54032, 0xd400 },
> +	{ 0x54033, 0x312d },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0xd400 },
> +	{ 0x54039, 0x312d },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +
> +/* P1 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp1_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54002, 0x101 },
> +	{ 0x54003, 0x190 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x121f },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54012, 0x110 },
> +	{ 0x54019, 0x84 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x84 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x1 },
> +	{ 0x54032, 0x8400 },
> +	{ 0x54033, 0x3300 },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0x8400 },
> +	{ 0x54039, 0x3300 },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +
> +/* P2 message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp2_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54002, 0x102 },
> +	{ 0x54003, 0x64 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x121f },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54012, 0x110 },
> +	{ 0x54019, 0x84 },
> +	{ 0x5401a, 0x33 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x84 },
> +	{ 0x54020, 0x33 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x1 },
> +	{ 0x54032, 0x8400 },
> +	{ 0x54033, 0x3300 },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0x8400 },
> +	{ 0x54039, 0x3300 },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +
> +/* P0 2D message block paremeter for training firmware */
> +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x54003, 0xbb8 },
> +	{ 0x54004, 0x2 },
> +	{ 0x54005, 0x2228 },
> +	{ 0x54006, 0x14 },
> +	{ 0x54008, 0x61 },
> +	{ 0x54009, 0xc8 },
> +	{ 0x5400b, 0x2 },
> +	{ 0x5400f, 0x100 },
> +	{ 0x54010, 0x1f7f },
> +	{ 0x54012, 0x110 },
> +	{ 0x54019, 0x2dd4 },
> +	{ 0x5401a, 0x31 },
> +	{ 0x5401b, 0x4866 },
> +	{ 0x5401c, 0x4800 },
> +	{ 0x5401e, 0x16 },
> +	{ 0x5401f, 0x2dd4 },
> +	{ 0x54020, 0x31 },
> +	{ 0x54021, 0x4866 },
> +	{ 0x54022, 0x4800 },
> +	{ 0x54024, 0x16 },
> +	{ 0x5402b, 0x1000 },
> +	{ 0x5402c, 0x1 },
> +	{ 0x54032, 0xd400 },
> +	{ 0x54033, 0x312d },
> +	{ 0x54034, 0x6600 },
> +	{ 0x54035, 0x48 },
> +	{ 0x54036, 0x48 },
> +	{ 0x54037, 0x1600 },
> +	{ 0x54038, 0xd400 },
> +	{ 0x54039, 0x312d },
> +	{ 0x5403a, 0x6600 },
> +	{ 0x5403b, 0x48 },
> +	{ 0x5403c, 0x48 },
> +	{ 0x5403d, 0x1600 },
> +	{ 0xd0000, 0x1 },
> +};
> +
> +/* DRAM PHY init engine image */
> +static struct dram_cfg_param ddr_phy_pie[] = {
> +	{ 0xd0000, 0x0 },
> +	{ 0x90000, 0x10 },
> +	{ 0x90001, 0x400 },
> +	{ 0x90002, 0x10e },
> +	{ 0x90003, 0x0 },
> +	{ 0x90004, 0x0 },
> +	{ 0x90005, 0x8 },
> +	{ 0x90029, 0xb },
> +	{ 0x9002a, 0x480 },
> +	{ 0x9002b, 0x109 },
> +	{ 0x9002c, 0x8 },
> +	{ 0x9002d, 0x448 },
> +	{ 0x9002e, 0x139 },
> +	{ 0x9002f, 0x8 },
> +	{ 0x90030, 0x478 },
> +	{ 0x90031, 0x109 },
> +	{ 0x90032, 0x0 },
> +	{ 0x90033, 0xe8 },
> +	{ 0x90034, 0x109 },
> +	{ 0x90035, 0x2 },
> +	{ 0x90036, 0x10 },
> +	{ 0x90037, 0x139 },
> +	{ 0x90038, 0xb },
> +	{ 0x90039, 0x7c0 },
> +	{ 0x9003a, 0x139 },
> +	{ 0x9003b, 0x44 },
> +	{ 0x9003c, 0x633 },
> +	{ 0x9003d, 0x159 },
> +	{ 0x9003e, 0x14f },
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> +	{ 0x116b4, 0x1 },
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> +	{ 0x118b4, 0x1 },
> +	{ 0x12011, 0x1 },
> +	{ 0x12012, 0x1 },
> +	{ 0x12013, 0x180 },
> +	{ 0x12018, 0x1 },
> +	{ 0x12002, 0x6209 },
> +	{ 0x120b2, 0x1 },
> +	{ 0x121b4, 0x1 },
> +	{ 0x122b4, 0x1 },
> +	{ 0x123b4, 0x1 },
> +	{ 0x124b4, 0x1 },
> +	{ 0x125b4, 0x1 },
> +	{ 0x126b4, 0x1 },
> +	{ 0x127b4, 0x1 },
> +	{ 0x128b4, 0x1 },
> +	{ 0x13011, 0x1 },
> +	{ 0x13012, 0x1 },
> +	{ 0x13013, 0x180 },
> +	{ 0x13018, 0x1 },
> +	{ 0x13002, 0x6209 },
> +	{ 0x130b2, 0x1 },
> +	{ 0x131b4, 0x1 },
> +	{ 0x132b4, 0x1 },
> +	{ 0x133b4, 0x1 },
> +	{ 0x134b4, 0x1 },
> +	{ 0x135b4, 0x1 },
> +	{ 0x136b4, 0x1 },
> +	{ 0x137b4, 0x1 },
> +	{ 0x138b4, 0x1 },
> +	{ 0x20089, 0x1 },
> +	{ 0x20088, 0x19 },
> +	{ 0xc0080, 0x2 },
> +	{ 0xd0000, 0x1 }
> +};
> +
> +static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
> +	{
> +		/* P0 3000mts 1D */
> +		.drate = 3000,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
> +	},
> +	{
> +		/* P1 400mts 1D */
> +		.drate = 400,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp1_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
> +	},
> +	{
> +		/* P2 100mts 1D */
> +		.drate = 100,
> +		.fw_type = FW_1D_IMAGE,
> +		.fsp_cfg = ddr_fsp2_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
> +	},
> +	{
> +		/* P0 3000mts 2D */
> +		.drate = 3000,
> +		.fw_type = FW_2D_IMAGE,
> +		.fsp_cfg = ddr_fsp0_2d_cfg,
> +		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
> +	},
> +};
> +
> +/* Samsung K4F6E3S4HB-MGCL ddr timing config params */
> +struct dram_timing_info imx8mp_skov_dram_timing = {
> +	.ddrc_cfg = ddr_ddrc_cfg,
> +	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
> +	.ddrphy_cfg = ddr_ddrphy_cfg,
> +	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
> +	.fsp_msg = ddr_dram_fsp_msg,
> +	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
> +	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
> +	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
> +	.ddrphy_pie = ddr_phy_pie,
> +	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
> +	.fsp_table = { 3000, 400, 100, },
> +};
> +
> diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig
> index 99d871bfb9..8084e72ea0 100644
> --- a/arch/arm/configs/imx_v8_defconfig
> +++ b/arch/arm/configs/imx_v8_defconfig
> @@ -7,6 +7,7 @@ CONFIG_MACH_NXP_IMX8MQ_EVK=y
>  CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y
>  CONFIG_MACH_POLYHEX_DEBIX=y
>  CONFIG_MACH_PROTONIC_IMX8M=y
> +CONFIG_MACH_SKOV_IMX8MP=y
>  CONFIG_MACH_TQ_MBA8MPXL=y
>  CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP=y
>  CONFIG_MACH_ZII_IMX8MQ_DEV=y
> diff --git a/arch/arm/configs/multi_v8_defconfig b/arch/arm/configs/multi_v8_defconfig
> index 77ad8a2688..20f630281d 100644
> --- a/arch/arm/configs/multi_v8_defconfig
> +++ b/arch/arm/configs/multi_v8_defconfig
> @@ -11,6 +11,7 @@ CONFIG_MACH_NXP_IMX8MQ_EVK=y
>  CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y
>  CONFIG_MACH_POLYHEX_DEBIX=y
>  CONFIG_MACH_PROTONIC_IMX8M=y
> +CONFIG_MACH_SKOV_IMX8MP=y
>  CONFIG_MACH_TQ_MBA8MPXL=y
>  CONFIG_MACH_VARISCITE_DT8MCUSTOMBOARD_IMX8MP=y
>  CONFIG_MACH_ZII_IMX8MQ_DEV=y
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 5cbb133b1a..81e11bb6a3 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -137,6 +137,7 @@ lwl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingb
>  				imx6dl-hummingboard2.dtb.o imx6q-hummingboard2.dtb.o \
>  				imx6q-h100.dtb.o
>  lwl-$(CONFIG_MACH_SKOV_IMX6) += imx6s-skov-imx6.dtb.o imx6dl-skov-imx6.dtb.o imx6q-skov-imx6.dtb.o
> +lwl-$(CONFIG_MACH_SKOV_IMX8MP) += imx8mp-skov.dtb.o
>  lwl-$(CONFIG_MACH_SKOV_ARM9CPU) += at91-skov-arm9cpu.dtb.o
>  lwl-$(CONFIG_MACH_SEEED_ODYSSEY) += stm32mp157c-odyssey.dtb.o
>  lwl-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp157c-dk2.dtb.o stm32mp157a-dk1.dtb.o
> diff --git a/arch/arm/dts/imx8mp-skov.dts b/arch/arm/dts/imx8mp-skov.dts
> new file mode 100644
> index 0000000000..b7f6fed4b7
> --- /dev/null
> +++ b/arch/arm/dts/imx8mp-skov.dts
> @@ -0,0 +1,518 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +/dts-v1/;
> +
> +#include <arm64/freescale/imx8mp.dtsi>
> +#include "imx8mp.dtsi"
> +
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> +	model = "Skov i.MX8MP";
> +	compatible = "skov,imx8mp", "fsl,imx8mp";
> +
> +	chosen {
> +		stdout-path = &uart2;
> +
> +		environment-sd {
> +			compatible = "barebox,environment";
> +			device-path = &env_sd;
> +			status = "disabled";
> +		};
> +
> +		environment-emmc {
> +			compatible = "barebox,environment";
> +			device-path = &env_emmc;
> +			status = "disabled";
> +		};
> +	};
> +
> +	aliases {
> +		ethernet0 = &eqos;
> +		ethernet1 = &lan1;
> +		ethernet2 = &lan2;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_gpio_led>;
> +
> +		led-0 {
> +			label = "D1";
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
> +			function = LED_FUNCTION_STATUS;
> +			default-state = "on";
> +			linux,default-trigger = "heartbeat";
> +		};
> +
> +		led-1 {
> +			label = "D2";
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
> +			default-state = "off";
> +		};
> +
> +		led-2 {
> +			label = "D3";
> +			color = <LED_COLOR_ID_GREEN>;
> +			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
> +			default-state = "on";
> +		};
> +	};
> +
> +	reg_usdhc2_vmmc: regulator-usdhc2 {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> +		regulator-name = "VSD_3V3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +};
> +
> +&usdhc2 {
> +	partitions {
> +		compatible = "fixed-partitions";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		partition@0 {
> +			label = "barebox";
> +			reg = <0x0 0x0 0x0 0x100000>;
> +		};
> +
> +		env_sd: partition@e0000 {
> +			label = "barebox-environment";
> +			reg = <0x0 0x100000 0x0 0x100000>;
> +		};
> +	};
> +};
> +
> +&usdhc3 {
> +	partitions {
> +		compatible = "fixed-partitions";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		partition@0 {
> +			label = "barebox";
> +			reg = <0x0 0x0 0x0 0x100000>;
> +		};
> +
> +		env_emmc: partition@e0000 {
> +			label = "barebox-environment";
> +			reg = <0x0 0x100000 0x0 0x100000>;
> +		};
> +	};
> +};
> +
> +&A53_0 {
> +	cpu-supply = <&buck2>;
> +};
> +
> +&A53_1 {
> +	cpu-supply = <&buck2>;
> +};
> +
> +&A53_2 {
> +	cpu-supply = <&buck2>;
> +};
> +
> +&A53_3 {
> +	cpu-supply = <&buck2>;
> +};
> +
> +&eqos {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_eqos>;
> +	phy-connection-type = "rgmii";
> +	status = "okay";
> +
> +	fixed-link {
> +		speed = <1000>;
> +		full-duplex;
> +	};
> +};
> +
> +&i2c1 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c1>;
> +	status = "okay";
> +
> +	pmic@25 {
> +		compatible = "nxp,pca9450c";
> +		reg = <0x25>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_pmic>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <3 IRQ_TYPE_EDGE_RISING>;
> +
> +		regulators {
> +			buck1: BUCK1 {
> +				regulator-name = "BUCK1";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <2187500>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +			};
> +
> +			buck2: BUCK2 {
> +				regulator-name = "BUCK2";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <2187500>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +				nxp,dvs-run-voltage = <950000>;
> +				nxp,dvs-standby-voltage = <850000>;
> +			};
> +
> +			buck4: BUCK4 {
> +				regulator-name = "BUCK4";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck5: BUCK5 {
> +				regulator-name = "BUCK5";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck6: BUCK6 {
> +				regulator-name = "BUCK6";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo1: LDO1 {
> +				regulator-name = "LDO1";
> +				regulator-min-microvolt = <1600000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo2: LDO2 {
> +				regulator-name = "LDO2";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <1150000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo3: LDO3 {
> +				regulator-name = "LDO3";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo4: LDO4 {
> +				regulator-name = "LDO4";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo5: LDO5 {
> +				regulator-name = "LDO5";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +};
> +
> +&i2c4 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c4>;
> +	status = "okay";
> +
> +	switch@5f {
> +		compatible = "microchip,ksz9893";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_switch>;
> +		reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
> +		reg = <0x5f>;
> +
> +		ethernet-ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			lan1: port@0 {
> +				reg = <0>;
> +				phy-mode = "internal";
> +				label = "lan1";
> +			};
> +
> +			lan2: port@1 {
> +				reg = <1>;
> +				phy-mode = "internal";
> +				label = "lan2";
> +			};
> +
> +			port@2 {
> +				reg = <2>;
> +				label = "cpu";
> +				ethernet = <&eqos>;
> +				/* 2ns rgmii-rxid is implemented on PCB.
> +				 * Switch should add only rgmii-txid.
> +				 */
> +				phy-mode = "rgmii-txid";
> +
> +				fixed-link {
> +					speed = <1000>;
> +					full-duplex;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&snvs_pwrkey {
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	/* console */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart2>;
> +	status = "okay";
> +};
> +
> +/* SD Card */
> +&usdhc2 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> +	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> +	wp-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
> +	vmmc-supply = <&reg_usdhc2_vmmc>;
> +	bus-width = <4>;
> +	status = "okay";
> +};
> +
> +/* eMMC */
> +&usdhc3 {
> +	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
> +	assigned-clock-rates = <400000000>;
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc3>;
> +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +&usb3_phy0 {
> +	status = "okay";
> +};
> +
> +&usb3_0 {
> +	status = "okay";
> +};
> +
> +&usb_dwc3_0 {
> +	dr_mode = "host";
> +	status = "okay";
> +};
> +
> +&usb3_phy1 {
> +	status = "okay";
> +};
> +
> +&usb3_1 {
> +	status = "okay";
> +};
> +
> +&usb_dwc3_1 {
> +	dr_mode = "host";
> +	status = "okay";
> +};
> +
> +&wdog1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_wdog>;
> +	fsl,ext-reset-output;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl_eqos: eqosgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
> +			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
> +			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
> +			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
> +			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
> +			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
> +			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
> +			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
> +			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
> +			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
> +			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
> +			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
> +		>;
> +	};
> +
> +	pinctrl_gpio_led: gpioledgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x19
> +			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06				0x19
> +			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07				0x19
> +		>;
> +	};
> +
> +	pinctrl_i2c1: i2c1grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL					0x400001c2
> +			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA					0x400001c2
> +		>;
> +	};
> +
> +	pinctrl_i2c4: i2c4grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c3
> +			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c3
> +		>;
> +	};
> +
> +	pinctrl_switch: switchgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01				0x41
> +		>;
> +	};
> +
> +	pinctrl_pmic: pmicirqgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03				0x41
> +		>;
> +	};
> +
> +	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19				0x41
> +		>;
> +	};
> +
> +	pinctrl_uart2: uart2grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX				0x14f
> +			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX				0x14f
> +		>;
> +	};
> +
> +	pinctrl_usdhc2: usdhc2grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x190
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d0
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d0
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d0
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d0
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d0
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x194
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d4
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d4
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d4
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d4
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d4
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK				0x196
> +			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD				0x1d6
> +			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0				0x1d6
> +			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1				0x1d6
> +			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2				0x1d6
> +			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3				0x1d6
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12				0x1c4
> +			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20					0x1c4
> +		>;
> +	};
> +
> +	pinctrl_usdhc3: usdhc3grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x190
> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d0
> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d0
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d0
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d0
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d0
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d0
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d0
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d0
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d0
> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x190
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x194
> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d4
> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d4
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d4
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d4
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d4
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d4
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d4
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d4
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d4
> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x194
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK				0x196
> +			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD				0x1d6
> +			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0				0x1d6
> +			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1				0x1d6
> +			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2				0x1d6
> +			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3				0x1d6
> +			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4				0x1d6
> +			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5				0x1d6
> +			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6				0x1d6
> +			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7				0x1d6
> +			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE				0x196
> +		>;
> +	};
> +
> +	pinctrl_wdog: wdoggrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B				0xc6
> +		>;
> +	};
> +};
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 8cab6de776..ebc486a669 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -646,6 +646,16 @@ config MACH_PROTONIC_IMX8M
>  	select IMX8M_DRAM
>  	select USB_GADGET_DRIVER_ARC_PBL
>  
> +config MACH_SKOV_IMX8MP
> +	bool "Skov i.MX8MP based boards"
> +	select ARCH_IMX8MP
> +	select FIRMWARE_IMX_LPDDR4_PMU_TRAIN
> +	select FIRMWARE_IMX8MP_ATF
> +	select ARM_SMCCC
> +	select MCI_IMX_ESDHC_PBL
> +	select IMX8M_DRAM
> +	select I2C_IMX_EARLY
> +
>  config MACH_TQ_MBA8MPXL
>  	bool "TQ i.MX8MP Dual/Quad on MBa8MPxL Board"
>  	select ARCH_IMX8MP
> diff --git a/images/Makefile.imx b/images/Makefile.imx
> index 65512e0e07..02355d3395 100644
> --- a/images/Makefile.imx
> +++ b/images/Makefile.imx
> @@ -458,6 +458,11 @@ CFG_start_nxp_imx8mp_evk.pblb.imximg = $(board)/nxp-imx8mp-evk/flash-header-imx8
>  FILE_barebox-nxp-imx8mp-evk.img = start_nxp_imx8mp_evk.pblb.pimximg
>  image-$(CONFIG_MACH_NXP_IMX8MP_EVK) += barebox-nxp-imx8mp-evk.img
>  
> +pblb-$(CONFIG_MACH_SKOV_IMX8MP) += start_skov_imx8mp
> +CFG_start_skov_imx8mp.pblb.imximg = $(board)/skov-imx8mp/flash-header-skov-imx8mp.imxcfg
> +FILE_barebox-skov-imx8mp.img = start_skov_imx8mp.pblb.pimximg
> +image-$(CONFIG_MACH_SKOV_IMX8MP) += barebox-skov-imx8mp.img
> +
>  pblb-$(CONFIG_MACH_TQ_MBA8MPXL) += start_tqma8mpxl
>  CFG_start_tqma8mpxl.pblb.imximg = $(board)/tqma8mpxl/flash-header-tqma8mpxl.imxcfg
>  FILE_barebox-tqma8mpxl.img = start_tqma8mpxl.pblb.pimximg
> -- 
> 2.39.2
> 
> 
> 

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