From mboxrd@z Thu Jan 1 00:00:00 1970 Delivery-date: Wed, 16 Aug 2023 07:57:24 +0200 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by lore.white.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1qW9X3-005uIE-7p for lore@lore.pengutronix.de; Wed, 16 Aug 2023 07:57:24 +0200 Received: from bombadil.infradead.org ([2607:7c80:54:3::133]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qW9X0-0005vB-QR for lore@pengutronix.de; Wed, 16 Aug 2023 07:57:24 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=+qS8pADweMJXhZizw+LX+xv4Jb2yLO8R1jtOXvPuFnU=; b=dwzVC3W1haPCwe imi6AuXqxHWfUUaSFjC3dqY/+KVrYfAADjdzWgpsOYgMVxq9DtIzQkBN1BlVITeLA7+CNy6Hvpqa7 7adR1ODAx/UkjHqFKOI4BA/ut3av/hLUjCkYFHrAA07OQGzDZBE3cqmdf6bvdQL2HNw3kAid6np4J Bvx7Wq/Y8NxfPe7f0gX/ah/gYfHF9KZZjpMDmHoSci3R+N8mFvEzMMdE+QokRTYXOgsNI+4bg3mLH lRO5jLMsMBTtQvU4MnflE59g4Ex06DbG8g7n/B4aHSqonpyZUTSsQRN5hcOzVisPHDPCwA/h2gi2D CmIEJH8gNDBOezEPggcg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qW9Va-003GEs-32; Wed, 16 Aug 2023 05:55:54 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qW9VW-003GE9-3A for barebox@lists.infradead.org; Wed, 16 Aug 2023 05:55:53 +0000 Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qW9VN-0005iW-ND; Wed, 16 Aug 2023 07:55:41 +0200 Received: from [2a0a:edc0:0:1101:1d::39] (helo=dude03.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1qW9VM-000yDJ-V9; Wed, 16 Aug 2023 07:55:40 +0200 Received: from uol by dude03.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1qW9VL-009gBC-TK; Wed, 16 Aug 2023 07:55:40 +0200 From: =?UTF-8?q?Ulrich=20=C3=96lmann?= To: Barebox List Date: Wed, 16 Aug 2023 07:55:35 +0200 Message-Id: <20230816055536.2307080-1-u.oelmann@pengutronix.de> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230815_225551_330953_1E56F931 X-CRM114-Status: GOOD ( 11.86 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?S=C3=B8ren=20Andersen?= Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.ext.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.9 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 1/2] ARM: skov-imx6: Add new calibration values for i.MX6Q X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.ext.pengutronix.de) From: Sascha Hauer Update to new DDR3 calibration values. The values are taken from the NXP DDR Stress Test (3.0.0) on a board variant 24 (ptx internal inventory skov-K-00-04624). The DRAM controller settings and IOMUX settings have been taken from the MX6DQ_DDR3_register_programming_aid_v2.4.xlxs file. DDR setup debug output: ----------------------- density:8 Gb (2 Gb per chip) clock: 528MHz (1893 ps) memspd:1066 tcke=2 tcksrx=6 tcksre=6 taofpd=1 taonpd=1 todtlon=4 tanpd=4 taxpd=4 trfc=84 txs=89 txp=3 txpdll=12 tfaw=26 tcl=5 trcd=7 trp=7 trc=25 tras=18 twr=7 tmrd=11 tcwl=4 tdllk=511 trtp=3 twtr=3 trrd=5 txpr=89 cs0_end=39 ncs=1 Rtt_wr=0 Rtt_nom=2 SRT=0 tcl=5 twr=7 MR2 CS0: 0x00088032 MR3 CS0: 0x00008033 MR1 CS0: 0x00408031 MR0 CS0: 0x19408030 ============================================ DDR Stress Test (3.0.0) Build: Dec 14 2018, 14:20:05 NXP Semiconductors. ============================================ ============================================ Chip ID CHIP ID = i.MX6 Dual/Quad (0x63) Internal Revision = TO1.6 ============================================ ============================================ Boot Configuration SRC_SBMR1(0x020d8004) = 0x28003032 SRC_SBMR2(0x020d801c) = 0x02000001 ============================================ What ARM core speed would you like to run? Type 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz ARM Clock set to 800MHz ============================================ DDR configuration BOOT_CFG3[5-4]: 0x00, Single DDR channel. DDR type is DDR3 Data width: 64, bank num: 8 Row size: 14, col size: 10 Chip select CSD0 is used Density per chip select: 1024MB ============================================ Current Temperature: 37 ============================================ Please select the DDR density per chip select (in bytes) on the board Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6 for 32MB For maximum supported density (4GB), we can only access up to 3.75GB. Type 7 to select this DDR density selected (MB): 128 Would do you want to change VDD_SOC_CAP/VDD_ARM_CAP voltage? Type 'y' to run and 'n' to skip Would do you want run DDR Calibration? Type 'y' to run and 'n' to skip Calibration will run at DDR frequency 528MHz. Type 'y' to continue. If you want to run at other DDR frequency. Type 'n' Please enter the MR1 value on the initilization script This will be re-programmed into MR1 after write leveling calibration Enter as a 4-digit HEX value, example 0004, then hit enter 0040DDR Freq: 528 MHz ddr_mr1=0x00000040 Start write leveling calibration... running Write level HW calibration MPWLHWERR register read out for factory diagnostics: MPWLHWERR PHY0 = 0x3c3e3c3c MPWLHWERR PHY1 = 0x3e3c3e3c Write leveling calibration completed, update the following registers in your initialization script MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00230023 MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0029001E MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F002A MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001A0028 Write DQS delay result: Write DQS0 delay: 35/256 CK Write DQS1 delay: 35/256 CK Write DQS2 delay: 30/256 CK Write DQS3 delay: 41/256 CK Write DQS4 delay: 42/256 CK Write DQS5 delay: 31/256 CK Write DQS6 delay: 40/256 CK Write DQS7 delay: 26/256 CK WARNING: write-leveling calibration value is greater than 1/8 CK. Per the reference manual, WALAT must be set to 1 in the register MDMISC(0x021B0018). This has been performed automatically. However, in addition to updating the calibration values in your DDR initialization, it is also REQUIRED change the value of MDMISC in their DDR initialization as follows: MMDC_MDMISC (0x021b0018) = 0x00091740 Starting DQS gating calibration . HC_DEL=0x00000000 result[00]=0x11101101 . HC_DEL=0x00000001 result[01]=0x11101101 . HC_DEL=0x00000002 result[02]=0x00100001 . HC_DEL=0x00000003 result[03]=0x00000000 . HC_DEL=0x00000004 result[04]=0x00000000 . HC_DEL=0x00000005 result[05]=0x11111111 . HC_DEL=0x00000006 result[06]=0x11111111 . HC_DEL=0x00000007 result[07]=0x11111111 . HC_DEL=0x00000008 result[08]=0x11111111 . HC_DEL=0x00000009 result[09]=0x11111111 . HC_DEL=0x0000000A result[0A]=0x11111111 . HC_DEL=0x0000000B result[0B]=0x11111111 . HC_DEL=0x0000000C result[0C]=0x11111111 . HC_DEL=0x0000000D result[0D]=0x11111111 DQS HC delay value low1 = 0x02020003, high1=0x04040404 DQS HC delay value low2 = 0x02020300, high2=0x04040404 loop ABS offset to get HW_DG_LOW . ABS_OFFSET=0x00000000 result[00]=0x11101101 . ABS_OFFSET=0x00000004 result[01]=0x11101101 . ABS_OFFSET=0x00000008 result[02]=0x11001101 . ABS_OFFSET=0x0000000C result[03]=0x11011111 . ABS_OFFSET=0x00000010 result[04]=0x11001100 . ABS_OFFSET=0x00000014 result[05]=0x11001100 . ABS_OFFSET=0x00000018 result[06]=0x11001100 . ABS_OFFSET=0x0000001C result[07]=0x11001100 . ABS_OFFSET=0x00000020 result[08]=0x11001100 . ABS_OFFSET=0x00000024 result[09]=0x11001100 . ABS_OFFSET=0x00000028 result[0A]=0x11001100 . ABS_OFFSET=0x0000002C result[0B]=0x11001100 . ABS_OFFSET=0x00000030 result[0C]=0x11001100 . ABS_OFFSET=0x00000034 result[0D]=0x11001100 . ABS_OFFSET=0x00000038 result[0E]=0x11011110 . ABS_OFFSET=0x0000003C result[0F]=0x11001100 . ABS_OFFSET=0x00000040 result[10]=0x11001100 . ABS_OFFSET=0x00000044 result[11]=0x11011110 . ABS_OFFSET=0x00000048 result[12]=0x11001100 . ABS_OFFSET=0x0000004C result[13]=0x11001100 . ABS_OFFSET=0x00000050 result[14]=0x10001100 . ABS_OFFSET=0x00000054 result[15]=0x10001100 . ABS_OFFSET=0x00000058 result[16]=0x10001100 . ABS_OFFSET=0x0000005C result[17]=0x10001100 . ABS_OFFSET=0x00000060 result[18]=0x10001100 . ABS_OFFSET=0x00000064 result[19]=0x10010110 . ABS_OFFSET=0x00000068 result[1A]=0x00000100 . ABS_OFFSET=0x0000006C result[1B]=0x00000000 . ABS_OFFSET=0x00000070 result[1C]=0x00000000 . ABS_OFFSET=0x00000074 result[1D]=0x00000000 . ABS_OFFSET=0x00000078 result[1E]=0x00000000 . ABS_OFFSET=0x0000007C result[1F]=0x00000000 loop ABS offset to get HW_DG_HIGH . ABS_OFFSET=0x00000000 result[00]=0x00000000 . ABS_OFFSET=0x00000004 result[01]=0x01000000 . ABS_OFFSET=0x00000008 result[02]=0x01000000 . ABS_OFFSET=0x0000000C result[03]=0x01000000 . ABS_OFFSET=0x00000010 result[04]=0x01000000 . ABS_OFFSET=0x00000014 result[05]=0x01000000 . ABS_OFFSET=0x00000018 result[06]=0x01000000 . ABS_OFFSET=0x0000001C result[07]=0x01000000 . ABS_OFFSET=0x00000020 result[08]=0x01000000 . ABS_OFFSET=0x00000024 result[09]=0x01000000 . ABS_OFFSET=0x00000028 result[0A]=0x01000000 . ABS_OFFSET=0x0000002C result[0B]=0x01000000 . ABS_OFFSET=0x00000030 result[0C]=0x01000000 . ABS_OFFSET=0x00000034 result[0D]=0x01100100 . ABS_OFFSET=0x00000038 result[0E]=0x11100100 . ABS_OFFSET=0x0000003C result[0F]=0x11101100 . ABS_OFFSET=0x00000040 result[10]=0x11101100 . ABS_OFFSET=0x00000044 result[11]=0x11111110 . ABS_OFFSET=0x00000048 result[12]=0x11111110 . ABS_OFFSET=0x0000004C result[13]=0x11111110 . ABS_OFFSET=0x00000050 result[14]=0x11111110 . ABS_OFFSET=0x00000054 result[15]=0x11111111 . ABS_OFFSET=0x00000058 result[16]=0x11111111 . ABS_OFFSET=0x0000005C result[17]=0x11111111 . ABS_OFFSET=0x00000060 result[18]=0x11111111 . ABS_OFFSET=0x00000064 result[19]=0x11111111 . ABS_OFFSET=0x00000068 result[1A]=0x11111111 . ABS_OFFSET=0x0000006C result[1B]=0x11111111 . ABS_OFFSET=0x00000070 result[1C]=0x11111111 . ABS_OFFSET=0x00000074 result[1D]=0x11111111 . ABS_OFFSET=0x00000078 result[1E]=0x11111111 . ABS_OFFSET=0x0000007C result[1F]=0x11111111 BYTE 0: Start: HC=0x02 ABS=0x10 End: HC=0x04 ABS=0x50 Mean: HC=0x03 ABS=0x30 End-0.5*tCK: HC=0x03 ABS=0x50 Final: HC=0x03 ABS=0x50 BYTE 1: Start: HC=0x00 ABS=0x00 End: HC=0x04 ABS=0x40 Mean: HC=0x02 ABS=0x20 End-0.5*tCK: HC=0x03 ABS=0x40 Final: HC=0x03 ABS=0x40 BYTE 2: Start: HC=0x01 ABS=0x6C End: HC=0x04 ABS=0x30 Mean: HC=0x03 ABS=0x0E End-0.5*tCK: HC=0x03 ABS=0x30 Final: HC=0x03 ABS=0x30 BYTE 3: Start: HC=0x01 ABS=0x64 End: HC=0x04 ABS=0x38 Mean: HC=0x03 ABS=0x0E End-0.5*tCK: HC=0x03 ABS=0x38 Final: HC=0x03 ABS=0x38 BYTE 4: Start: HC=0x00 ABS=0x00 End: HC=0x04 ABS=0x40 Mean: HC=0x02 ABS=0x20 End-0.5*tCK: HC=0x03 ABS=0x40 Final: HC=0x03 ABS=0x40 BYTE 5: Start: HC=0x02 ABS=0x08 End: HC=0x04 ABS=0x30 Mean: HC=0x03 ABS=0x1C End-0.5*tCK: HC=0x03 ABS=0x30 Final: HC=0x03 ABS=0x30 BYTE 6: Start: HC=0x01 ABS=0x50 End: HC=0x04 ABS=0x00 Mean: HC=0x02 ABS=0x67 End-0.5*tCK: HC=0x03 ABS=0x00 Final: HC=0x03 ABS=0x00 BYTE 7: Start: HC=0x01 ABS=0x68 End: HC=0x04 ABS=0x34 Mean: HC=0x03 ABS=0x0E End-0.5*tCK: HC=0x03 ABS=0x34 Final: HC=0x03 ABS=0x34 DQS calibration MMDC0 MPDGCTRL0 = 0x43400350, MPDGCTRL1 = 0x03380330 DQS calibration MMDC1 MPDGCTRL0 = 0x43300340, MPDGCTRL1 = 0x03340300 Note: Array result[] holds the DRAM test result of each byte. 0: test pass. 1: test fail 4 bits respresent the result of 1 byte. result 00000001:byte 0 fail. result 00000011:byte 0, 1 fail. Starting Read calibration... ABS_OFFSET=0x00000000 result[00]=0x11111111 ABS_OFFSET=0x04040404 result[01]=0x11111111 ABS_OFFSET=0x08080808 result[02]=0x11111111 ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111 ABS_OFFSET=0x10101010 result[04]=0x11011111 ABS_OFFSET=0x14141414 result[05]=0x01011001 ABS_OFFSET=0x18181818 result[06]=0x00011000 ABS_OFFSET=0x1C1C1C1C result[07]=0x00010000 ABS_OFFSET=0x20202020 result[08]=0x00000000 ABS_OFFSET=0x24242424 result[09]=0x00000000 ABS_OFFSET=0x28282828 result[0A]=0x00000000 ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000 ABS_OFFSET=0x30303030 result[0C]=0x00000000 ABS_OFFSET=0x34343434 result[0D]=0x00000000 ABS_OFFSET=0x38383838 result[0E]=0x00000000 ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000 ABS_OFFSET=0x40404040 result[10]=0x00000000 ABS_OFFSET=0x44444444 result[11]=0x00000000 ABS_OFFSET=0x48484848 result[12]=0x00000000 ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000 ABS_OFFSET=0x50505050 result[14]=0x00000000 ABS_OFFSET=0x54545454 result[15]=0x00000100 ABS_OFFSET=0x58585858 result[16]=0x00100100 ABS_OFFSET=0x5C5C5C5C result[17]=0x00100111 ABS_OFFSET=0x60606060 result[18]=0x11100111 ABS_OFFSET=0x64646464 result[19]=0x11101111 ABS_OFFSET=0x68686868 result[1A]=0x11110111 ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111 ABS_OFFSET=0x70707070 result[1C]=0x11111111 ABS_OFFSET=0x74747474 result[1D]=0x11111111 ABS_OFFSET=0x78787878 result[1E]=0x11111111 ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111 Byte 0: (0x18 - 0x58), middle value:0x38 Byte 1: (0x14 - 0x58), middle value:0x36 Byte 2: (0x14 - 0x50), middle value:0x32 Byte 3: (0x1c - 0x60), middle value:0x3e Byte 4: (0x20 - 0x64), middle value:0x42 Byte 5: (0x10 - 0x54), middle value:0x32 Byte 6: (0x18 - 0x5c), middle value:0x3a Byte 7: (0x14 - 0x5c), middle value:0x38 MMDC0 MPRDDLCTL = 0x3E323638, MMDC1 MPRDDLCTL = 0x383A3242 Starting Write calibration... ABS_OFFSET=0x00000000 result[00]=0x11111111 ABS_OFFSET=0x04040404 result[01]=0x10111111 ABS_OFFSET=0x08080808 result[02]=0x10110111 ABS_OFFSET=0x0C0C0C0C result[03]=0x10100010 ABS_OFFSET=0x10101010 result[04]=0x10100000 ABS_OFFSET=0x14141414 result[05]=0x00100000 ABS_OFFSET=0x18181818 result[06]=0x00000000 ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000 ABS_OFFSET=0x20202020 result[08]=0x00000000 ABS_OFFSET=0x24242424 result[09]=0x00000000 ABS_OFFSET=0x28282828 result[0A]=0x00000000 ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000 ABS_OFFSET=0x30303030 result[0C]=0x00000000 ABS_OFFSET=0x34343434 result[0D]=0x00000000 ABS_OFFSET=0x38383838 result[0E]=0x00000000 ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000 ABS_OFFSET=0x40404040 result[10]=0x00000000 ABS_OFFSET=0x44444444 result[11]=0x00000000 ABS_OFFSET=0x48484848 result[12]=0x00000000 ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000 ABS_OFFSET=0x50505050 result[14]=0x00000000 ABS_OFFSET=0x54545454 result[15]=0x00000000 ABS_OFFSET=0x58585858 result[16]=0x00000000 ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000 ABS_OFFSET=0x60606060 result[18]=0x00000000 ABS_OFFSET=0x64646464 result[19]=0x01000000 ABS_OFFSET=0x68686868 result[1A]=0x01000000 ABS_OFFSET=0x6C6C6C6C result[1B]=0x01011101 ABS_OFFSET=0x70707070 result[1C]=0x01011111 ABS_OFFSET=0x74747474 result[1D]=0x11011111 ABS_OFFSET=0x78787878 result[1E]=0x11111111 ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111 Byte 0: (0x0c - 0x68), middle value:0x3a Byte 1: (0x10 - 0x6c), middle value:0x3e Byte 2: (0x0c - 0x68), middle value:0x3a Byte 3: (0x08 - 0x68), middle value:0x38 Byte 4: (0x0c - 0x68), middle value:0x3a Byte 5: (0x18 - 0x74), middle value:0x46 Byte 6: (0x04 - 0x60), middle value:0x32 Byte 7: (0x14 - 0x70), middle value:0x42 MMDC0 MPWRDLCTL = 0x383A3E3A,MMDC1 MPWRDLCTL = 0x4232463A MMDC registers updated from calibration Write leveling calibration MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00230023 MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0029001E MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001F002A MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x001A0028 Read DQS Gating calibration MPDGCTRL0 PHY0 (0x021b083c) = 0x43400350 MPDGCTRL1 PHY0 (0x021b0840) = 0x03380330 MPDGCTRL0 PHY1 (0x021b483c) = 0x43300340 MPDGCTRL1 PHY1 (0x021b4840) = 0x03340300 Read calibration MPRDDLCTL PHY0 (0x021b0848) = 0x3E323638 MPRDDLCTL PHY1 (0x021b4848) = 0x383A3242 Write calibration MPWRDLCTL PHY0 (0x021b0850) = 0x383A3E3A MPWRDLCTL PHY1 (0x021b4850) = 0x4232463A Success: DDR calibration completed!!! Signed-off-by: Sascha Hauer --- arch/arm/boards/skov-imx6/lowlevel.c | 68 ++++++++++++++-------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/boards/skov-imx6/lowlevel.c b/arch/arm/boards/skov-imx6/lowlevel.c index a7f5dce890ff..842e3af6db77 100644 --- a/arch/arm/boards/skov-imx6/lowlevel.c +++ b/arch/arm/boards/skov-imx6/lowlevel.c @@ -175,33 +175,33 @@ static const struct mx6_ddr_sysinfo skov_imx6_sysinfo_4x128Mb_1066MHz = { .dsize = 2, /* 64 bit wide = 4 devices, 16 bit each */ .cs_density = 8, /* four 2 GBit devices connected */ .ncs = 1, /* one CS line for all devices */ - .cs1_mirror = 1, /* TODO */ - .bi_on = 1, /* TODO */ + .cs1_mirror = 1, + .bi_on = 1, .rtt_nom = 1, /* MX6_MMDC_P0_MPODTCTRL -> 0x00022227 */ .rtt_wr = 0, /* is LW_EN is 0 in their code */ - .ralat = 5, /* TODO */ - .walat = 1, /* TODO */ - .mif3_mode = 3, /* TODO */ - .rst_to_cke = 0x23, /* used in their code as well */ - .sde_to_rst = 0x10, /* used in their code as well */ - .pd_fast_exit = 0, /* TODO */ + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, + .pd_fast_exit = 1, }; /* calibration info for the "max performance" and "high performance" */ static const struct mx6_mmdc_calibration skov_imx6_calib_4x128Mb_1066MHz = { - .p0_mpwldectrl0 = 0x0011000E, - .p0_mpwldectrl1 = 0x000E001B, - .p0_mpdgctrl0 = 0x42720306, - .p0_mpdgctrl1 = 0x026F0266, - .p0_mprddlctl = 0x45393B3E, - .p0_mpwrdlctl = 0x40434541, - - .p1_mpwldectrl0 = 0x00190015, - .p1_mpwldectrl1 = 0x00070018, - .p1_mpdgctrl0 = 0x4273030A, - .p1_mpdgctrl1 = 0x02740240, - .p1_mprddlctl = 0x403A3747, - .p1_mpwrdlctl = 0x473E4A3B, + .p0_mpwldectrl0 = 0x00230023, + .p0_mpwldectrl1 = 0x0029001E, + .p0_mpdgctrl0 = 0x43400350, + .p0_mpdgctrl1 = 0x03380330, + .p0_mprddlctl = 0x3E323638, + .p0_mpwrdlctl = 0x383A3E3A, + + .p1_mpwldectrl0 = 0x001F002A, + .p1_mpwldectrl1 = 0x001A0028, + .p1_mpdgctrl0 = 0x43300340, + .p1_mpdgctrl1 = 0x03340300, + .p1_mprddlctl = 0x383A3242, + .p1_mpwrdlctl = 0x4232463A, }; /* ------------------------------------------------------------------------ */ @@ -215,21 +215,21 @@ static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { .dram_sdqs5 = 0x00000030, .dram_sdqs6 = 0x00000030, .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_dqm4 = 0x00000030, + .dram_dqm5 = 0x00000030, + .dram_dqm6 = 0x00000030, + .dram_dqm7 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, .dram_sdcke0 = 0x00003000, .dram_sdcke1 = 0x00003000, - .dram_reset = 0x00020030, + .dram_reset = 0x00000030, .dram_sdba2 = 0x00000000, .dram_sdodt0 = 0x00003030, .dram_sdodt1 = 0x00003030, -- 2.39.2