From: Sascha Hauer <s.hauer@pengutronix.de>
To: Lior Weintraub <liorw@pliops.com>
Cc: "barebox@lists.infradead.org" <barebox@lists.infradead.org>
Subject: Re: ARM: mmu_early_enable
Date: Thu, 17 Aug 2023 09:17:36 +0200 [thread overview]
Message-ID: <20230817071736.GJ5650@pengutronix.de> (raw)
In-Reply-To: <PR3P195MB0555EE60DE17128F9831C028C31AA@PR3P195MB0555.EURP195.PROD.OUTLOOK.COM>
On Thu, Aug 17, 2023 at 06:22:50AM +0000, Lior Weintraub wrote:
> Hi Sascha,
>
> I think I found an issue with the CONFIG_MMU feature.
> When the code under barebox_pbl_start calls mmu_early_enable, the MMU
> is set such that only the given SRAM is defined (membase, memsize).
> But then, if DEBUG_LL is in use and the function pr_debug is called we
> get an exception because the UART address is not included in the MMU.
That shouldn't happen. See the code in mmu_early_enable():
early_remap_range(0, 1UL << (BITS_PER_VA - 1), MAP_UNCACHED);
early_remap_range(membase, memsize - OPTEE_SIZE, MAP_CACHED);
early_remap_range(membase + memsize - OPTEE_SIZE, OPTEE_SIZE, MAP_FAULT);
The first line maps the whole address space uncached in a flat 1:1
mapping. The second and third lines map the SDRAM (SRAM in your case)
cached.
Your availabe memory is quite small (3MiB) and by skipping the
relocation your SRAM layout is not standard. Could it be that something
overwrites your page tables?
Sascha
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next prev parent reply other threads:[~2023-08-17 7:19 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-17 6:22 Lior Weintraub
2023-08-17 7:17 ` Sascha Hauer [this message]
2023-08-17 7:32 ` Lior Weintraub
2023-08-17 13:49 ` Lior Weintraub
2023-08-21 14:29 ` Lior Weintraub
2023-09-07 8:31 ` Ahmad Fatoum
2023-09-07 10:08 ` Lior Weintraub
2023-12-14 16:04 ` [PATCH] [ARM64][MMU] Fix mmu_early_enable VA->PA mapping Lior Weintraub
2023-12-18 6:52 ` Sascha Hauer
2023-12-18 11:06 ` Sascha Hauer
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