* [PATCH 1/3] memory: Add driver for FMC2 External Bus Interface on STM32MP SoCs
@ 2023-08-30 10:47 Alexander Shiyan
2023-08-30 10:47 ` [PATCH 2/3] mtd: nand: Add driver for NAND controller " Alexander Shiyan
2023-08-30 10:47 ` [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support Alexander Shiyan
0 siblings, 2 replies; 10+ messages in thread
From: Alexander Shiyan @ 2023-08-30 10:47 UTC (permalink / raw)
To: barebox; +Cc: Alexander Shiyan
This adds support for FMC2 External Bus Interface on STM32MP SoCs.
The original source is taken from linux-6.4.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
drivers/memory/Kconfig | 11 +
drivers/memory/Makefile | 1 +
drivers/memory/stm32-fmc2-ebi.c | 1136 +++++++++++++++++++++++++++++++
3 files changed, 1148 insertions(+)
create mode 100644 drivers/memory/stm32-fmc2-ebi.c
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index e18b452009..70c5846e69 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -23,4 +23,15 @@ config MC_TEGRA124
the Tegra124 SoC. This driver performs the necessary initialization
to provide a function GPU when the OS is running.
+config STM32_FMC2_EBI
+ bool "Support for FMC2 External Bus Interface on STM32MP SoCs"
+ depends on ARCH_STM32MP || COMPILE_TEST
+ select RESET_CONTROLLER if ARCH_STM32MP
+ select RESET_SIMPLE if ARCH_STM32MP
+ help
+ Select this option to enable the STM32 FMC2 External Bus Interface
+ controller. This driver configures the transactions with external
+ devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
+ SOCs containing the FMC2 External Bus Interface.
+
endmenu
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index bdf8db66e8..67d3c47621 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o
obj-$(CONFIG_MC_TEGRA124) += mc-tegra124.o
+obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c
new file mode 100644
index 0000000000..5fee805261
--- /dev/null
+++ b/drivers/memory/stm32-fmc2-ebi.c
@@ -0,0 +1,1136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2020
+ */
+
+#include <common.h>
+#include <init.h>
+#include <regmap.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <mfd/syscon.h>
+
+/* FMC2 Controller Registers */
+#define FMC2_BCR1 0x0
+#define FMC2_BTR1 0x4
+#define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
+#define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
+#define FMC2_PCSCNTR 0x20
+#define FMC2_BWTR1 0x104
+#define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
+
+/* Register: FMC2_BCR1 */
+#define FMC2_BCR1_CCLKEN BIT(20)
+#define FMC2_BCR1_FMC2EN BIT(31)
+
+/* Register: FMC2_BCRx */
+#define FMC2_BCR_MBKEN BIT(0)
+#define FMC2_BCR_MUXEN BIT(1)
+#define FMC2_BCR_MTYP GENMASK(3, 2)
+#define FMC2_BCR_MWID GENMASK(5, 4)
+#define FMC2_BCR_FACCEN BIT(6)
+#define FMC2_BCR_BURSTEN BIT(8)
+#define FMC2_BCR_WAITPOL BIT(9)
+#define FMC2_BCR_WAITCFG BIT(11)
+#define FMC2_BCR_WREN BIT(12)
+#define FMC2_BCR_WAITEN BIT(13)
+#define FMC2_BCR_EXTMOD BIT(14)
+#define FMC2_BCR_ASYNCWAIT BIT(15)
+#define FMC2_BCR_CPSIZE GENMASK(18, 16)
+#define FMC2_BCR_CBURSTRW BIT(19)
+#define FMC2_BCR_NBLSET GENMASK(23, 22)
+
+/* Register: FMC2_BTRx/FMC2_BWTRx */
+#define FMC2_BXTR_ADDSET GENMASK(3, 0)
+#define FMC2_BXTR_ADDHLD GENMASK(7, 4)
+#define FMC2_BXTR_DATAST GENMASK(15, 8)
+#define FMC2_BXTR_BUSTURN GENMASK(19, 16)
+#define FMC2_BTR_CLKDIV GENMASK(23, 20)
+#define FMC2_BTR_DATLAT GENMASK(27, 24)
+#define FMC2_BXTR_ACCMOD GENMASK(29, 28)
+#define FMC2_BXTR_DATAHLD GENMASK(31, 30)
+
+/* Register: FMC2_PCSCNTR */
+#define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0)
+#define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16)
+
+#define FMC2_MAX_EBI_CE 4
+#define FMC2_MAX_BANKS 5
+
+#define FMC2_BCR_CPSIZE_0 0x0
+#define FMC2_BCR_CPSIZE_128 0x1
+#define FMC2_BCR_CPSIZE_256 0x2
+#define FMC2_BCR_CPSIZE_512 0x3
+#define FMC2_BCR_CPSIZE_1024 0x4
+
+#define FMC2_BCR_MWID_8 0x0
+#define FMC2_BCR_MWID_16 0x1
+
+#define FMC2_BCR_MTYP_SRAM 0x0
+#define FMC2_BCR_MTYP_PSRAM 0x1
+#define FMC2_BCR_MTYP_NOR 0x2
+
+#define FMC2_BXTR_EXTMOD_A 0x0
+#define FMC2_BXTR_EXTMOD_B 0x1
+#define FMC2_BXTR_EXTMOD_C 0x2
+#define FMC2_BXTR_EXTMOD_D 0x3
+
+#define FMC2_BCR_NBLSET_MAX 0x3
+#define FMC2_BXTR_ADDSET_MAX 0xf
+#define FMC2_BXTR_ADDHLD_MAX 0xf
+#define FMC2_BXTR_DATAST_MAX 0xff
+#define FMC2_BXTR_BUSTURN_MAX 0xf
+#define FMC2_BXTR_DATAHLD_MAX 0x3
+#define FMC2_BTR_CLKDIV_MAX 0xf
+#define FMC2_BTR_DATLAT_MAX 0xf
+#define FMC2_PCSCNTR_CSCOUNT_MAX 0xff
+
+enum stm32_fmc2_ebi_bank {
+ FMC2_EBI1 = 0,
+ FMC2_EBI2,
+ FMC2_EBI3,
+ FMC2_EBI4,
+ FMC2_NAND
+};
+
+enum stm32_fmc2_ebi_register_type {
+ FMC2_REG_BCR = 1,
+ FMC2_REG_BTR,
+ FMC2_REG_BWTR,
+ FMC2_REG_PCSCNTR
+};
+
+enum stm32_fmc2_ebi_transaction_type {
+ FMC2_ASYNC_MODE_1_SRAM = 0,
+ FMC2_ASYNC_MODE_1_PSRAM,
+ FMC2_ASYNC_MODE_A_SRAM,
+ FMC2_ASYNC_MODE_A_PSRAM,
+ FMC2_ASYNC_MODE_2_NOR,
+ FMC2_ASYNC_MODE_B_NOR,
+ FMC2_ASYNC_MODE_C_NOR,
+ FMC2_ASYNC_MODE_D_NOR,
+ FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
+ FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
+ FMC2_SYNC_READ_SYNC_WRITE_NOR,
+ FMC2_SYNC_READ_ASYNC_WRITE_NOR
+};
+
+enum stm32_fmc2_ebi_buswidth {
+ FMC2_BUSWIDTH_8 = 8,
+ FMC2_BUSWIDTH_16 = 16
+};
+
+enum stm32_fmc2_ebi_cpsize {
+ FMC2_CPSIZE_0 = 0,
+ FMC2_CPSIZE_128 = 128,
+ FMC2_CPSIZE_256 = 256,
+ FMC2_CPSIZE_512 = 512,
+ FMC2_CPSIZE_1024 = 1024
+};
+
+struct stm32_fmc2_ebi {
+ struct device *dev;
+ struct clk *clk;
+ struct regmap *regmap;
+ u8 bank_assigned;
+
+ u32 bcr[FMC2_MAX_EBI_CE];
+ u32 btr[FMC2_MAX_EBI_CE];
+ u32 bwtr[FMC2_MAX_EBI_CE];
+ u32 pcscntr;
+};
+
+/*
+ * struct stm32_fmc2_prop - STM32 FMC2 EBI property
+ * @name: the device tree binding name of the property
+ * @bprop: indicate that it is a boolean property
+ * @mprop: indicate that it is a mandatory property
+ * @reg_type: the register that have to be modified
+ * @reg_mask: the bit that have to be modified in the selected register
+ * in case of it is a boolean property
+ * @reset_val: the default value that have to be set in case the property
+ * has not been defined in the device tree
+ * @check: this callback ckecks that the property is compliant with the
+ * transaction type selected
+ * @calculate: this callback is called to calculate for exemple a timing
+ * set in nanoseconds in the device tree in clock cycles or in
+ * clock period
+ * @set: this callback applies the values in the registers
+ */
+struct stm32_fmc2_prop {
+ const char *name;
+ bool bprop;
+ bool mprop;
+ int reg_type;
+ u32 reg_mask;
+ u32 reset_val;
+ int (*check)(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop, int cs);
+ u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
+ int (*set)(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup);
+};
+
+static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs)
+{
+ u32 bcr;
+
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
+
+ if (bcr & FMC2_BCR_MTYP)
+ return 0;
+
+ return -EINVAL;
+}
+
+static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs)
+{
+ u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
+
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
+
+ if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
+ return 0;
+
+ return -EINVAL;
+}
+
+static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs)
+{
+ u32 bcr;
+
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
+
+ if (bcr & FMC2_BCR_BURSTEN)
+ return 0;
+
+ return -EINVAL;
+}
+
+static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs)
+{
+ u32 bcr;
+
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
+
+ if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
+ return 0;
+
+ return -EINVAL;
+}
+
+static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs)
+{
+ u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
+
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
+
+ if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
+ return 0;
+
+ return -EINVAL;
+}
+
+static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs)
+{
+ u32 bcr, bxtr, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
+
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
+ if (prop->reg_type == FMC2_REG_BWTR)
+ regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
+ else
+ regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
+
+ if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
+ ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
+ return 0;
+
+ return -EINVAL;
+}
+
+static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs)
+{
+ u32 bcr, bcr1;
+
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
+ if (cs)
+ regmap_read(ebi->regmap, FMC2_BCR1, &bcr1);
+ else
+ bcr1 = bcr;
+
+ if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
+ return 0;
+
+ return -EINVAL;
+}
+
+static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs)
+{
+ if (cs)
+ return -EINVAL;
+
+ return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
+}
+
+static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
+ int cs, u32 setup)
+{
+ unsigned long hclk = clk_get_rate(ebi->clk);
+ unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
+
+ return DIV_ROUND_UP(setup * 1000, hclkp);
+}
+
+static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
+ int cs, u32 setup)
+{
+ u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
+ u32 bcr, btr, clk_period;
+
+ regmap_read(ebi->regmap, FMC2_BCR1, &bcr);
+ if (bcr & FMC2_BCR1_CCLKEN || !cs)
+ regmap_read(ebi->regmap, FMC2_BTR1, &btr);
+ else
+ regmap_read(ebi->regmap, FMC2_BTR(cs), &btr);
+
+ clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
+
+ return DIV_ROUND_UP(nb_clk_cycles, clk_period);
+}
+
+static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
+{
+ switch (reg_type) {
+ case FMC2_REG_BCR:
+ *reg = FMC2_BCR(cs);
+ break;
+ case FMC2_REG_BTR:
+ *reg = FMC2_BTR(cs);
+ break;
+ case FMC2_REG_BWTR:
+ *reg = FMC2_BWTR(cs);
+ break;
+ case FMC2_REG_PCSCNTR:
+ *reg = FMC2_PCSCNTR;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 reg;
+ int ret;
+
+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
+ if (ret)
+ return ret;
+
+ regmap_update_bits(ebi->regmap, reg, prop->reg_mask,
+ setup ? prop->reg_mask : 0);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 bcr_mask, bcr = FMC2_BCR_WREN;
+ u32 btr_mask, btr = 0;
+ u32 bwtr_mask, bwtr = 0;
+
+ bwtr_mask = FMC2_BXTR_ACCMOD;
+ btr_mask = FMC2_BXTR_ACCMOD;
+ bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
+ FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
+ FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
+
+ switch (setup) {
+ case FMC2_ASYNC_MODE_1_SRAM:
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
+ /*
+ * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
+ */
+ break;
+ case FMC2_ASYNC_MODE_1_PSRAM:
+ /*
+ * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
+ break;
+ case FMC2_ASYNC_MODE_A_SRAM:
+ /*
+ * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
+ bcr |= FMC2_BCR_EXTMOD;
+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
+ break;
+ case FMC2_ASYNC_MODE_A_PSRAM:
+ /*
+ * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
+ bcr |= FMC2_BCR_EXTMOD;
+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
+ break;
+ case FMC2_ASYNC_MODE_2_NOR:
+ /*
+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
+ bcr |= FMC2_BCR_FACCEN;
+ break;
+ case FMC2_ASYNC_MODE_B_NOR:
+ /*
+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
+ break;
+ case FMC2_ASYNC_MODE_C_NOR:
+ /*
+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
+ break;
+ case FMC2_ASYNC_MODE_D_NOR:
+ /*
+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
+ * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
+ btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
+ bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
+ break;
+ case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
+ /*
+ * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
+ * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
+ bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
+ break;
+ case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
+ /*
+ * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
+ bcr |= FMC2_BCR_BURSTEN;
+ break;
+ case FMC2_SYNC_READ_SYNC_WRITE_NOR:
+ /*
+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
+ * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
+ break;
+ case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
+ /*
+ * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
+ * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
+ */
+ bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
+ bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
+ break;
+ default:
+ /* Type of transaction not supported */
+ return -EINVAL;
+ }
+
+ if (bcr & FMC2_BCR_EXTMOD)
+ regmap_update_bits(ebi->regmap, FMC2_BWTR(cs),
+ bwtr_mask, bwtr);
+ regmap_update_bits(ebi->regmap, FMC2_BTR(cs), btr_mask, btr);
+ regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 val;
+
+ switch (setup) {
+ case FMC2_BUSWIDTH_8:
+ val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
+ break;
+ case FMC2_BUSWIDTH_16:
+ val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
+ break;
+ default:
+ /* Buswidth not supported */
+ return -EINVAL;
+ }
+
+ regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 val;
+
+ switch (setup) {
+ case FMC2_CPSIZE_0:
+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
+ break;
+ case FMC2_CPSIZE_128:
+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
+ break;
+ case FMC2_CPSIZE_256:
+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
+ break;
+ case FMC2_CPSIZE_512:
+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
+ break;
+ case FMC2_CPSIZE_1024:
+ val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
+ break;
+ default:
+ /* Cpsize not supported */
+ return -EINVAL;
+ }
+
+ regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 val;
+
+ val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
+ val = FIELD_PREP(FMC2_BCR_NBLSET, val);
+ regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 bcr, bxtr, reg;
+ u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
+ int ret;
+
+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
+ if (ret)
+ return ret;
+
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
+ if (prop->reg_type == FMC2_REG_BWTR)
+ regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
+ else
+ regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
+
+ if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
+ val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
+ else
+ val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
+ val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
+ regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDSET, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 val, reg;
+ int ret;
+
+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
+ if (ret)
+ return ret;
+
+ val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
+ val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
+ regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDHLD, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 val, reg;
+ int ret;
+
+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
+ if (ret)
+ return ret;
+
+ val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
+ val = FIELD_PREP(FMC2_BXTR_DATAST, val);
+ regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAST, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 val, reg;
+ int ret;
+
+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
+ if (ret)
+ return ret;
+
+ val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
+ val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
+ regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_BUSTURN, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 val, reg;
+ int ret;
+
+ ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®);
+ if (ret)
+ return ret;
+
+ if (prop->reg_type == FMC2_REG_BWTR)
+ val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
+ else
+ val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
+ val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
+ regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAHLD, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 val;
+
+ val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
+ val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
+ regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 val;
+
+ val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
+ val = FIELD_PREP(FMC2_BTR_DATLAT, val);
+ regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
+ const struct stm32_fmc2_prop *prop,
+ int cs, u32 setup)
+{
+ u32 old_val, new_val, pcscntr;
+
+ if (setup < 1)
+ return 0;
+
+ regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr);
+
+ /* Enable counter for the bank */
+ regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
+ FMC2_PCSCNTR_CNTBEN(cs),
+ FMC2_PCSCNTR_CNTBEN(cs));
+
+ new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
+ old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
+ if (old_val && new_val > old_val)
+ /* Keep current counter value */
+ return 0;
+
+ new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
+ regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
+ FMC2_PCSCNTR_CSCOUNT, new_val);
+
+ return 0;
+}
+
+static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
+ /* st,fmc2-ebi-cs-trans-type must be the first property */
+ {
+ .name = "st,fmc2-ebi-cs-transaction-type",
+ .mprop = true,
+ .set = stm32_fmc2_ebi_set_trans_type,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-cclk-enable",
+ .bprop = true,
+ .reg_type = FMC2_REG_BCR,
+ .reg_mask = FMC2_BCR1_CCLKEN,
+ .check = stm32_fmc2_ebi_check_cclk,
+ .set = stm32_fmc2_ebi_set_bit_field,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-mux-enable",
+ .bprop = true,
+ .reg_type = FMC2_REG_BCR,
+ .reg_mask = FMC2_BCR_MUXEN,
+ .check = stm32_fmc2_ebi_check_mux,
+ .set = stm32_fmc2_ebi_set_bit_field,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-buswidth",
+ .reset_val = FMC2_BUSWIDTH_16,
+ .set = stm32_fmc2_ebi_set_buswidth,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-waitpol-high",
+ .bprop = true,
+ .reg_type = FMC2_REG_BCR,
+ .reg_mask = FMC2_BCR_WAITPOL,
+ .set = stm32_fmc2_ebi_set_bit_field,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-waitcfg-enable",
+ .bprop = true,
+ .reg_type = FMC2_REG_BCR,
+ .reg_mask = FMC2_BCR_WAITCFG,
+ .check = stm32_fmc2_ebi_check_waitcfg,
+ .set = stm32_fmc2_ebi_set_bit_field,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-wait-enable",
+ .bprop = true,
+ .reg_type = FMC2_REG_BCR,
+ .reg_mask = FMC2_BCR_WAITEN,
+ .check = stm32_fmc2_ebi_check_sync_trans,
+ .set = stm32_fmc2_ebi_set_bit_field,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-asyncwait-enable",
+ .bprop = true,
+ .reg_type = FMC2_REG_BCR,
+ .reg_mask = FMC2_BCR_ASYNCWAIT,
+ .check = stm32_fmc2_ebi_check_async_trans,
+ .set = stm32_fmc2_ebi_set_bit_field,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-cpsize",
+ .check = stm32_fmc2_ebi_check_cpsize,
+ .set = stm32_fmc2_ebi_set_cpsize,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_bl_setup,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-address-setup-ns",
+ .reg_type = FMC2_REG_BTR,
+ .reset_val = FMC2_BXTR_ADDSET_MAX,
+ .check = stm32_fmc2_ebi_check_async_trans,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_address_setup,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-address-hold-ns",
+ .reg_type = FMC2_REG_BTR,
+ .reset_val = FMC2_BXTR_ADDHLD_MAX,
+ .check = stm32_fmc2_ebi_check_address_hold,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_address_hold,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-data-setup-ns",
+ .reg_type = FMC2_REG_BTR,
+ .reset_val = FMC2_BXTR_DATAST_MAX,
+ .check = stm32_fmc2_ebi_check_async_trans,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_data_setup,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
+ .reg_type = FMC2_REG_BTR,
+ .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_bus_turnaround,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-data-hold-ns",
+ .reg_type = FMC2_REG_BTR,
+ .check = stm32_fmc2_ebi_check_async_trans,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_data_hold,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-clk-period-ns",
+ .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
+ .check = stm32_fmc2_ebi_check_clk_period,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_clk_period,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-data-latency-ns",
+ .check = stm32_fmc2_ebi_check_sync_trans,
+ .calculate = stm32_fmc2_ebi_ns_to_clk_period,
+ .set = stm32_fmc2_ebi_set_data_latency,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-write-address-setup-ns",
+ .reg_type = FMC2_REG_BWTR,
+ .reset_val = FMC2_BXTR_ADDSET_MAX,
+ .check = stm32_fmc2_ebi_check_async_trans,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_address_setup,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-write-address-hold-ns",
+ .reg_type = FMC2_REG_BWTR,
+ .reset_val = FMC2_BXTR_ADDHLD_MAX,
+ .check = stm32_fmc2_ebi_check_address_hold,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_address_hold,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-write-data-setup-ns",
+ .reg_type = FMC2_REG_BWTR,
+ .reset_val = FMC2_BXTR_DATAST_MAX,
+ .check = stm32_fmc2_ebi_check_async_trans,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_data_setup,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
+ .reg_type = FMC2_REG_BWTR,
+ .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_bus_turnaround,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-write-data-hold-ns",
+ .reg_type = FMC2_REG_BWTR,
+ .check = stm32_fmc2_ebi_check_async_trans,
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_data_hold,
+ },
+ {
+ .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
+ .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
+ .set = stm32_fmc2_ebi_set_max_low_pulse,
+ },
+};
+
+static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
+ struct device_node *dev_node,
+ const struct stm32_fmc2_prop *prop,
+ int cs)
+{
+ struct device *dev = ebi->dev;
+ u32 setup = 0;
+
+ if (!prop->set) {
+ dev_err(dev, "property %s is not well defined\n", prop->name);
+ return -EINVAL;
+ }
+
+ if (prop->check && prop->check(ebi, prop, cs))
+ /* Skeep this property */
+ return 0;
+
+ if (prop->bprop) {
+ bool bprop;
+
+ bprop = of_property_read_bool(dev_node, prop->name);
+ if (prop->mprop && !bprop) {
+ dev_err(dev, "mandatory property %s not defined in the device tree\n",
+ prop->name);
+ return -EINVAL;
+ }
+
+ if (bprop)
+ setup = 1;
+ } else {
+ u32 val;
+ int ret;
+
+ ret = of_property_read_u32(dev_node, prop->name, &val);
+ if (prop->mprop && ret) {
+ dev_err(dev, "mandatory property %s not defined in the device tree\n",
+ prop->name);
+ return ret;
+ }
+
+ if (ret)
+ setup = prop->reset_val;
+ else if (prop->calculate)
+ setup = prop->calculate(ebi, cs, val);
+ else
+ setup = val;
+ }
+
+ return prop->set(ebi, prop, cs, setup);
+}
+
+static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
+{
+ regmap_update_bits(ebi->regmap, FMC2_BCR(cs),
+ FMC2_BCR_MBKEN, FMC2_BCR_MBKEN);
+}
+
+static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
+{
+ regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0);
+}
+
+static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi)
+{
+ unsigned int cs;
+
+ for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]);
+ regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]);
+ regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]);
+ }
+
+ regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr);
+}
+
+static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi)
+{
+ unsigned int cs;
+
+ for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
+ if (!(ebi->bank_assigned & BIT(cs)))
+ continue;
+
+ stm32_fmc2_ebi_disable_bank(ebi, cs);
+ }
+}
+
+/* NWAIT signal can not be connected to EBI controller and NAND controller */
+static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
+{
+ unsigned int cs;
+ u32 bcr;
+
+ for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
+ if (!(ebi->bank_assigned & BIT(cs)))
+ continue;
+
+ regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
+ if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
+ ebi->bank_assigned & BIT(FMC2_NAND))
+ return true;
+ }
+
+ return false;
+}
+
+static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
+{
+ regmap_update_bits(ebi->regmap, FMC2_BCR1,
+ FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
+}
+
+static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi)
+{
+ regmap_update_bits(ebi->regmap, FMC2_BCR1, FMC2_BCR1_FMC2EN, 0);
+}
+
+static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
+ struct device_node *dev_node,
+ u32 cs)
+{
+ unsigned int i;
+ int ret;
+
+ stm32_fmc2_ebi_disable_bank(ebi, cs);
+
+ for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
+ const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
+
+ ret = stm32_fmc2_ebi_parse_prop(ebi, dev_node, p, cs);
+ if (ret) {
+ dev_err(ebi->dev, "property %s could not be set: %d\n",
+ p->name, ret);
+ return ret;
+ }
+ }
+
+ stm32_fmc2_ebi_enable_bank(ebi, cs);
+
+ return 0;
+}
+
+static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi)
+{
+ struct device *dev = ebi->dev;
+ struct device_node *child;
+ bool child_found = false;
+ u32 bank;
+ int ret;
+
+ for_each_available_child_of_node(dev->of_node, child) {
+ ret = of_property_read_u32(child, "reg", &bank);
+ if (ret) {
+ dev_err(dev, "could not retrieve reg property: %d\n",
+ ret);
+ of_node_put(child);
+ return ret;
+ }
+
+ if (bank >= FMC2_MAX_BANKS) {
+ dev_err(dev, "invalid reg value: %d\n", bank);
+ of_node_put(child);
+ return -EINVAL;
+ }
+
+ if (ebi->bank_assigned & BIT(bank)) {
+ dev_err(dev, "bank already assigned: %d\n", bank);
+ of_node_put(child);
+ return -EINVAL;
+ }
+
+ if (bank < FMC2_MAX_EBI_CE) {
+ ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
+ if (ret) {
+ dev_err(dev, "setup chip select %d failed: %d\n",
+ bank, ret);
+ of_node_put(child);
+ return ret;
+ }
+ }
+
+ ebi->bank_assigned |= BIT(bank);
+ child_found = true;
+ }
+
+ if (!child_found) {
+ dev_warn(dev, "no subnodes found, disable the driver.\n");
+ return -ENODEV;
+ }
+
+ if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
+ dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
+ return -EINVAL;
+ }
+
+ stm32_fmc2_ebi_enable(ebi);
+
+ return of_platform_populate(dev->of_node, NULL, dev);
+}
+
+static int stm32_fmc2_ebi_probe(struct device *dev)
+{
+ struct stm32_fmc2_ebi *ebi;
+ int ret;
+
+ ebi = kzalloc(sizeof(*ebi), GFP_KERNEL);
+ if (!ebi)
+ return -ENOMEM;
+
+ ebi->dev = dev;
+
+ ebi->regmap = device_node_to_regmap(dev->of_node);
+ if (IS_ERR(ebi->regmap))
+ return PTR_ERR(ebi->regmap);
+
+ ebi->clk = clk_get(dev, NULL);
+ if (IS_ERR(ebi->clk))
+ return PTR_ERR(ebi->clk);
+
+ ret = device_reset_us(dev, 2);
+ if (ret)
+ return -EINVAL;
+
+ ret = clk_prepare_enable(ebi->clk);
+ if (ret)
+ return ret;
+
+ ret = stm32_fmc2_ebi_parse_dt(ebi);
+ if (ret)
+ goto err_release;
+
+ stm32_fmc2_ebi_save_setup(ebi);
+
+ return 0;
+
+err_release:
+ stm32_fmc2_ebi_disable_banks(ebi);
+ stm32_fmc2_ebi_disable(ebi);
+ clk_disable_unprepare(ebi->clk);
+
+ return ret;
+}
+
+static __maybe_unused struct of_device_id stm32_fmc2_ebi_match[] = {
+ { .compatible = "st,stm32mp1-fmc2-ebi", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match);
+
+static struct driver stm32_fmc2_ebi_driver = {
+ .name = "stm32_fmc2_ebi",
+ .probe = stm32_fmc2_ebi_probe,
+ .of_compatible = DRV_OF_COMPAT(stm32_fmc2_ebi_match),
+};
+coredevice_platform_driver(stm32_fmc2_ebi_driver);
--
2.39.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] mtd: nand: Add driver for NAND controller on STM32MP SoCs
2023-08-30 10:47 [PATCH 1/3] memory: Add driver for FMC2 External Bus Interface on STM32MP SoCs Alexander Shiyan
@ 2023-08-30 10:47 ` Alexander Shiyan
2023-08-30 10:47 ` [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support Alexander Shiyan
1 sibling, 0 replies; 10+ messages in thread
From: Alexander Shiyan @ 2023-08-30 10:47 UTC (permalink / raw)
To: barebox; +Cc: Alexander Shiyan
This adds support for NAND controller on STM32MP SoCs.
The original source is taken from linux-6.4.
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
drivers/mtd/nand/Kconfig | 12 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/stm32_fmc2_nand.c | 1354 ++++++++++++++++++++++++++++
3 files changed, 1367 insertions(+)
create mode 100644 drivers/mtd/nand/stm32_fmc2_nand.c
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index d4b941d20c..87926d88d2 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -95,6 +95,18 @@ config NAND_MRVL_NFC
Support for the PXA3xx NAND controller, present in Armada 370/XP and
PXA3xx SoCs.
+config NAND_STM32
+ bool "Support for NAND controller on STM32MP SoCs"
+ depends on ARCH_STM32MP || COMPILE_TEST
+ select STM32_FMC2_EBI if ARCH_STM32MP
+ select RESET_CONTROLLER if ARCH_STM32MP
+ select RESET_SIMPLE if ARCH_STM32MP
+ help
+ Enables support for NAND Flash chips on SoCs containing the FMC2
+ NAND controller. This controller is found on STM32MP SoCs.
+ The controller supports a maximum 8k page size and supports
+ a maximum 8-bit correction error per sector of 512 bytes.
+
config NAND_ATMEL
bool
prompt "Atmel (AT91SAM9xxx) NAND driver"
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 6258eb2177..a0207d328b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_NAND_IMX) += nand_imx.o
obj-$(CONFIG_NAND_OMAP_GPMC) += nand_omap_gpmc.o nand_omap_bch_decoder.o
obj-$(CONFIG_MTD_NAND_OMAP_ELM) += omap_elm.o
obj-$(CONFIG_NAND_ORION) += nand_orion.o
+obj-$(CONFIG_NAND_STM32) += stm32_fmc2_nand.o
obj-$(CONFIG_NAND_MRVL_NFC) += nand_mrvl_nfc.o
obj-$(CONFIG_NAND_ATMEL) += atmel/
obj-$(CONFIG_NAND_MXS) += nand_mxs.o
diff --git a/drivers/mtd/nand/stm32_fmc2_nand.c b/drivers/mtd/nand/stm32_fmc2_nand.c
new file mode 100644
index 0000000000..958a619be5
--- /dev/null
+++ b/drivers/mtd/nand/stm32_fmc2_nand.c
@@ -0,0 +1,1354 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2018
+ * Author: Christophe Kerello <christophe.kerello@st.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <of_address.h>
+#include <regmap.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/gpio/consumer.h>
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+#include <mfd/syscon.h>
+
+#include "internals.h"
+
+/* Bad block marker length */
+#define FMC2_BBM_LEN 2
+
+/* ECC step size */
+#define FMC2_ECC_STEP_SIZE 512
+
+/* Max requests done for a 8k nand page size */
+#define FMC2_MAX_SG 16
+
+/* Max chip enable */
+#define FMC2_MAX_CE 2
+
+#define FMC2_TIMEOUT_MS 5000
+
+/* Timings */
+#define FMC2_THIZ 1
+#define FMC2_TIO 8000
+#define FMC2_TSYNC 3000
+#define FMC2_PCR_TIMING_MASK 0xf
+#define FMC2_PMEM_PATT_TIMING_MASK 0xff
+
+/* FMC2 Controller Registers */
+#define FMC2_BCR1 0x0
+#define FMC2_PCR 0x80
+#define FMC2_SR 0x84
+#define FMC2_PMEM 0x88
+#define FMC2_PATT 0x8c
+#define FMC2_HECCR 0x94
+#define FMC2_ISR 0x184
+#define FMC2_ICR 0x188
+#define FMC2_CSQCR 0x200
+#define FMC2_CSQCFGR1 0x204
+#define FMC2_CSQCFGR2 0x208
+#define FMC2_CSQCFGR3 0x20c
+#define FMC2_CSQAR1 0x210
+#define FMC2_CSQAR2 0x214
+#define FMC2_CSQIER 0x220
+#define FMC2_CSQISR 0x224
+#define FMC2_CSQICR 0x228
+#define FMC2_CSQEMSR 0x230
+#define FMC2_BCHIER 0x250
+#define FMC2_BCHISR 0x254
+#define FMC2_BCHICR 0x258
+#define FMC2_BCHPBR1 0x260
+#define FMC2_BCHPBR2 0x264
+#define FMC2_BCHPBR3 0x268
+#define FMC2_BCHPBR4 0x26c
+#define FMC2_BCHDSR0 0x27c
+#define FMC2_BCHDSR1 0x280
+#define FMC2_BCHDSR2 0x284
+#define FMC2_BCHDSR3 0x288
+#define FMC2_BCHDSR4 0x28c
+
+/* Register: FMC2_BCR1 */
+#define FMC2_BCR1_FMC2EN BIT(31)
+
+/* Register: FMC2_PCR */
+#define FMC2_PCR_PWAITEN BIT(1)
+#define FMC2_PCR_PBKEN BIT(2)
+#define FMC2_PCR_PWID GENMASK(5, 4)
+#define FMC2_PCR_PWID_BUSWIDTH_8 0
+#define FMC2_PCR_PWID_BUSWIDTH_16 1
+#define FMC2_PCR_ECCEN BIT(6)
+#define FMC2_PCR_ECCALG BIT(8)
+#define FMC2_PCR_TCLR GENMASK(12, 9)
+#define FMC2_PCR_TCLR_DEFAULT 0xf
+#define FMC2_PCR_TAR GENMASK(16, 13)
+#define FMC2_PCR_TAR_DEFAULT 0xf
+#define FMC2_PCR_ECCSS GENMASK(19, 17)
+#define FMC2_PCR_ECCSS_512 1
+#define FMC2_PCR_ECCSS_2048 3
+#define FMC2_PCR_BCHECC BIT(24)
+#define FMC2_PCR_WEN BIT(25)
+
+/* Register: FMC2_SR */
+#define FMC2_SR_NWRF BIT(6)
+
+/* Register: FMC2_PMEM */
+#define FMC2_PMEM_MEMSET GENMASK(7, 0)
+#define FMC2_PMEM_MEMWAIT GENMASK(15, 8)
+#define FMC2_PMEM_MEMHOLD GENMASK(23, 16)
+#define FMC2_PMEM_MEMHIZ GENMASK(31, 24)
+#define FMC2_PMEM_DEFAULT 0x0a0a0a0a
+
+/* Register: FMC2_PATT */
+#define FMC2_PATT_ATTSET GENMASK(7, 0)
+#define FMC2_PATT_ATTWAIT GENMASK(15, 8)
+#define FMC2_PATT_ATTHOLD GENMASK(23, 16)
+#define FMC2_PATT_ATTHIZ GENMASK(31, 24)
+#define FMC2_PATT_DEFAULT 0x0a0a0a0a
+
+/* Register: FMC2_ISR */
+#define FMC2_ISR_IHLF BIT(1)
+
+/* Register: FMC2_BCHISR */
+#define FMC2_BCHISR_DERF BIT(1)
+#define FMC2_BCHISR_EPBRF BIT(4)
+
+/* Register: FMC2_ICR */
+#define FMC2_ICR_CIHLF BIT(1)
+
+/* Register: FMC2_CSQCR */
+#define FMC2_CSQCR_CSQSTART BIT(0)
+
+/* Register: FMC2_CSQCFGR1 */
+#define FMC2_CSQCFGR1_CMD2EN BIT(1)
+#define FMC2_CSQCFGR1_DMADEN BIT(2)
+#define FMC2_CSQCFGR1_ACYNBR GENMASK(6, 4)
+#define FMC2_CSQCFGR1_CMD1 GENMASK(15, 8)
+#define FMC2_CSQCFGR1_CMD2 GENMASK(23, 16)
+#define FMC2_CSQCFGR1_CMD1T BIT(24)
+#define FMC2_CSQCFGR1_CMD2T BIT(25)
+
+/* Register: FMC2_CSQCFGR2 */
+#define FMC2_CSQCFGR2_SQSDTEN BIT(0)
+#define FMC2_CSQCFGR2_RCMD2EN BIT(1)
+#define FMC2_CSQCFGR2_DMASEN BIT(2)
+#define FMC2_CSQCFGR2_RCMD1 GENMASK(15, 8)
+#define FMC2_CSQCFGR2_RCMD2 GENMASK(23, 16)
+#define FMC2_CSQCFGR2_RCMD1T BIT(24)
+#define FMC2_CSQCFGR2_RCMD2T BIT(25)
+
+/* Register: FMC2_CSQCFGR3 */
+#define FMC2_CSQCFGR3_SNBR GENMASK(13, 8)
+#define FMC2_CSQCFGR3_AC1T BIT(16)
+#define FMC2_CSQCFGR3_AC2T BIT(17)
+#define FMC2_CSQCFGR3_AC3T BIT(18)
+#define FMC2_CSQCFGR3_AC4T BIT(19)
+#define FMC2_CSQCFGR3_AC5T BIT(20)
+#define FMC2_CSQCFGR3_SDT BIT(21)
+#define FMC2_CSQCFGR3_RAC1T BIT(22)
+#define FMC2_CSQCFGR3_RAC2T BIT(23)
+
+/* Register: FMC2_CSQCAR1 */
+#define FMC2_CSQCAR1_ADDC1 GENMASK(7, 0)
+#define FMC2_CSQCAR1_ADDC2 GENMASK(15, 8)
+#define FMC2_CSQCAR1_ADDC3 GENMASK(23, 16)
+#define FMC2_CSQCAR1_ADDC4 GENMASK(31, 24)
+
+/* Register: FMC2_CSQCAR2 */
+#define FMC2_CSQCAR2_ADDC5 GENMASK(7, 0)
+#define FMC2_CSQCAR2_NANDCEN GENMASK(11, 10)
+#define FMC2_CSQCAR2_SAO GENMASK(31, 16)
+
+/* Register: FMC2_CSQIER */
+#define FMC2_CSQIER_TCIE BIT(0)
+
+/* Register: FMC2_CSQICR */
+#define FMC2_CSQICR_CLEAR_IRQ GENMASK(4, 0)
+
+/* Register: FMC2_CSQEMSR */
+#define FMC2_CSQEMSR_SEM GENMASK(15, 0)
+
+/* Register: FMC2_BCHIER */
+#define FMC2_BCHIER_DERIE BIT(1)
+#define FMC2_BCHIER_EPBRIE BIT(4)
+
+/* Register: FMC2_BCHICR */
+#define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0)
+
+/* Register: FMC2_BCHDSR0 */
+#define FMC2_BCHDSR0_DUE BIT(0)
+#define FMC2_BCHDSR0_DEF BIT(1)
+#define FMC2_BCHDSR0_DEN GENMASK(7, 4)
+
+/* Register: FMC2_BCHDSR1 */
+#define FMC2_BCHDSR1_EBP1 GENMASK(12, 0)
+#define FMC2_BCHDSR1_EBP2 GENMASK(28, 16)
+
+/* Register: FMC2_BCHDSR2 */
+#define FMC2_BCHDSR2_EBP3 GENMASK(12, 0)
+#define FMC2_BCHDSR2_EBP4 GENMASK(28, 16)
+
+/* Register: FMC2_BCHDSR3 */
+#define FMC2_BCHDSR3_EBP5 GENMASK(12, 0)
+#define FMC2_BCHDSR3_EBP6 GENMASK(28, 16)
+
+/* Register: FMC2_BCHDSR4 */
+#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)
+#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)
+
+enum stm32_fmc2_ecc {
+ FMC2_ECC_HAM = 1,
+ FMC2_ECC_BCH4 = 4,
+ FMC2_ECC_BCH8 = 8
+};
+
+struct stm32_fmc2_timings {
+ u8 tclr;
+ u8 tar;
+ u8 thiz;
+ u8 twait;
+ u8 thold_mem;
+ u8 tset_mem;
+ u8 thold_att;
+ u8 tset_att;
+};
+
+struct stm32_fmc2_nand {
+ struct nand_chip chip;
+ struct gpio_desc *wp_gpio;
+ struct stm32_fmc2_timings timings;
+ int ncs;
+ int cs_used[FMC2_MAX_CE];
+};
+
+static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip)
+{
+ return container_of(chip, struct stm32_fmc2_nand, chip);
+}
+
+struct stm32_fmc2_nfc {
+ struct nand_controller base;
+ struct stm32_fmc2_nand nand;
+ struct device *dev;
+ struct device *cdev;
+ struct regmap *regmap;
+ void __iomem *data_base[FMC2_MAX_CE];
+ void __iomem *cmd_base[FMC2_MAX_CE];
+ void __iomem *addr_base[FMC2_MAX_CE];
+ struct clk *clk;
+
+ u8 cs_assigned;
+ int cs_sel;
+};
+
+static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base)
+{
+ return container_of(base, struct stm32_fmc2_nfc, base);
+}
+
+static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
+ struct stm32_fmc2_timings *timings = &nand->timings;
+ u32 pmem, patt;
+
+ /* Set tclr/tar timings */
+ regmap_update_bits(nfc->regmap, FMC2_PCR,
+ FMC2_PCR_TCLR | FMC2_PCR_TAR,
+ FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) |
+ FIELD_PREP(FMC2_PCR_TAR, timings->tar));
+
+ /* Set tset/twait/thold/thiz timings in common bank */
+ pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem);
+ pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait);
+ pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem);
+ pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz);
+ regmap_write(nfc->regmap, FMC2_PMEM, pmem);
+
+ /* Set tset/twait/thold/thiz timings in attribut bank */
+ patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att);
+ patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait);
+ patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att);
+ patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz);
+ regmap_write(nfc->regmap, FMC2_PATT, patt);
+}
+
+static void stm32_fmc2_nfc_setup(struct nand_chip *chip)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ u32 pcr = 0, pcr_mask;
+
+ /* Configure ECC algorithm (default configuration is Hamming) */
+ pcr_mask = FMC2_PCR_ECCALG;
+ pcr_mask |= FMC2_PCR_BCHECC;
+ if (chip->ecc.strength == FMC2_ECC_BCH8) {
+ pcr |= FMC2_PCR_ECCALG;
+ pcr |= FMC2_PCR_BCHECC;
+ } else if (chip->ecc.strength == FMC2_ECC_BCH4) {
+ pcr |= FMC2_PCR_ECCALG;
+ }
+
+ /* Set buswidth */
+ pcr_mask |= FMC2_PCR_PWID;
+ if (chip->options & NAND_BUSWIDTH_16)
+ pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16);
+
+ /* Set ECC sector size */
+ pcr_mask |= FMC2_PCR_ECCSS;
+ pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512);
+
+ regmap_update_bits(nfc->regmap, FMC2_PCR, pcr_mask, pcr);
+}
+
+static void stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
+
+ if (nand->cs_used[chipnr] == nfc->cs_sel)
+ return;
+
+ nfc->cs_sel = nand->cs_used[chipnr];
+ stm32_fmc2_nfc_setup(chip);
+ stm32_fmc2_nfc_timings_init(chip);
+}
+
+static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set)
+{
+ u32 pcr;
+
+ pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) :
+ FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8);
+
+ regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, pcr);
+}
+
+static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable)
+{
+ regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN,
+ enable ? FMC2_PCR_ECCEN : 0);
+}
+
+static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc)
+{
+ regmap_write(nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
+}
+
+/*
+ * Enable ECC logic and reset syndrome/parity bits previously calculated
+ * Syndrome/parity bits is cleared by setting the ECCEN bit to 0
+ */
+static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+
+ stm32_fmc2_nfc_set_ecc(nfc, false);
+
+ if (chip->ecc.strength != FMC2_ECC_HAM) {
+ regmap_update_bits(nfc->regmap, FMC2_PCR, FMC2_PCR_WEN,
+ mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0);
+
+ stm32_fmc2_nfc_clear_bch_irq(nfc);
+ }
+
+ stm32_fmc2_nfc_set_ecc(nfc, true);
+}
+
+/*
+ * ECC Hamming calculation
+ * ECC is 3 bytes for 512 bytes of data (supports error correction up to
+ * max of 1-bit)
+ */
+static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
+{
+ ecc[0] = ecc_sta;
+ ecc[1] = ecc_sta >> 8;
+ ecc[2] = ecc_sta >> 16;
+}
+
+static int stm32_fmc2_nfc_ham_calculate(struct nand_chip *chip, const u8 *data,
+ u8 *ecc)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ u32 sr, heccr;
+ int ret;
+
+ ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
+ sr & FMC2_SR_NWRF,
+ 1000 * FMC2_TIMEOUT_MS);
+ if (ret) {
+ dev_err(nfc->dev, "ham timeout\n");
+ return ret;
+ }
+
+ regmap_read(nfc->regmap, FMC2_HECCR, &heccr);
+ stm32_fmc2_nfc_ham_set_ecc(heccr, ecc);
+ stm32_fmc2_nfc_set_ecc(nfc, false);
+
+ return 0;
+}
+
+static int stm32_fmc2_nfc_ham_correct(struct nand_chip *chip, u8 *dat,
+ u8 *read_ecc, u8 *calc_ecc)
+{
+ u8 bit_position = 0, b0, b1, b2;
+ u32 byte_addr = 0, b;
+ u32 i, shifting = 1;
+
+ /* Indicate which bit and byte is faulty (if any) */
+ b0 = read_ecc[0] ^ calc_ecc[0];
+ b1 = read_ecc[1] ^ calc_ecc[1];
+ b2 = read_ecc[2] ^ calc_ecc[2];
+ b = b0 | (b1 << 8) | (b2 << 16);
+
+ /* No errors */
+ if (likely(!b))
+ return 0;
+
+ /* Calculate bit position */
+ for (i = 0; i < 3; i++) {
+ switch (b % 4) {
+ case 2:
+ bit_position += shifting;
+ break;
+ case 1:
+ break;
+ default:
+ return -EBADMSG;
+ }
+ shifting <<= 1;
+ b >>= 2;
+ }
+
+ /* Calculate byte position */
+ shifting = 1;
+ for (i = 0; i < 9; i++) {
+ switch (b % 4) {
+ case 2:
+ byte_addr += shifting;
+ break;
+ case 1:
+ break;
+ default:
+ return -EBADMSG;
+ }
+ shifting <<= 1;
+ b >>= 2;
+ }
+
+ /* Flip the bit */
+ dat[byte_addr] ^= (1 << bit_position);
+
+ return 1;
+}
+
+/*
+ * ECC BCH calculation and correction
+ * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
+ * max of 4-bit/8-bit)
+ */
+static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data,
+ u8 *ecc)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ u32 bchisr, bchpbr;
+ int ret;
+
+ /* Wait until the BCH code is ready */
+ ret = regmap_read_poll_timeout(nfc->regmap, FMC2_BCHISR, bchisr,
+ bchisr & FMC2_BCHISR_EPBRF,
+ 1000 * FMC2_TIMEOUT_MS);
+ if (ret) {
+ dev_err(nfc->dev, "bch timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ /* Read parity bits */
+ regmap_read(nfc->regmap, FMC2_BCHPBR1, &bchpbr);
+ ecc[0] = bchpbr;
+ ecc[1] = bchpbr >> 8;
+ ecc[2] = bchpbr >> 16;
+ ecc[3] = bchpbr >> 24;
+
+ regmap_read(nfc->regmap, FMC2_BCHPBR2, &bchpbr);
+ ecc[4] = bchpbr;
+ ecc[5] = bchpbr >> 8;
+ ecc[6] = bchpbr >> 16;
+
+ if (chip->ecc.strength == FMC2_ECC_BCH8) {
+ ecc[7] = bchpbr >> 24;
+
+ regmap_read(nfc->regmap, FMC2_BCHPBR3, &bchpbr);
+ ecc[8] = bchpbr;
+ ecc[9] = bchpbr >> 8;
+ ecc[10] = bchpbr >> 16;
+ ecc[11] = bchpbr >> 24;
+
+ regmap_read(nfc->regmap, FMC2_BCHPBR4, &bchpbr);
+ ecc[12] = bchpbr;
+ }
+
+ stm32_fmc2_nfc_set_ecc(nfc, false);
+
+ return 0;
+}
+
+static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
+{
+ u32 bchdsr0 = ecc_sta[0];
+ u32 bchdsr1 = ecc_sta[1];
+ u32 bchdsr2 = ecc_sta[2];
+ u32 bchdsr3 = ecc_sta[3];
+ u32 bchdsr4 = ecc_sta[4];
+ u16 pos[8];
+ int i, den;
+ unsigned int nb_errs = 0;
+
+ /* No errors found */
+ if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF)))
+ return 0;
+
+ /* Too many errors detected */
+ if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE))
+ return -EBADMSG;
+
+ pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1);
+ pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1);
+ pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2);
+ pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2);
+ pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3);
+ pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3);
+ pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4);
+ pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4);
+
+ den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0);
+ for (i = 0; i < den; i++) {
+ if (pos[i] < eccsize * 8) {
+ change_bit(pos[i], (unsigned long *)dat);
+ nb_errs++;
+ }
+ }
+
+ return nb_errs;
+}
+
+static int stm32_fmc2_nfc_bch_correct(struct nand_chip *chip, u8 *dat,
+ u8 *read_ecc, u8 *calc_ecc)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ u32 bchisr, ecc_sta[5];
+ int ret;
+
+ /* Wait until the decoding error is ready */
+ ret = regmap_read_poll_timeout(nfc->regmap, FMC2_BCHISR, bchisr,
+ bchisr & FMC2_BCHISR_DERF,
+ 1000 * FMC2_TIMEOUT_MS);
+ if (ret) {
+ dev_err(nfc->dev, "bch timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ regmap_bulk_read(nfc->regmap, FMC2_BCHDSR0, ecc_sta, 5);
+
+ stm32_fmc2_nfc_set_ecc(nfc, false);
+
+ return stm32_fmc2_nfc_bch_decode(chip->ecc.size, dat, ecc_sta);
+}
+
+static int stm32_fmc2_nfc_read_page(struct nand_chip *chip, u8 *buf,
+ int oob_required, int page)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int ret, i, s, stat, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ int eccstrength = chip->ecc.strength;
+ u8 *p = buf;
+ u8 *ecc_calc = chip->ecc.calc_buf;
+ u8 *ecc_code = chip->ecc.code_buf;
+ unsigned int max_bitflips = 0;
+
+ ret = nand_read_page_op(chip, page, 0, NULL, 0);
+ if (ret)
+ return ret;
+
+ for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
+ s++, i += eccbytes, p += eccsize) {
+ chip->ecc.hwctl(chip, NAND_ECC_READ);
+
+ /* Read the nand page sector (512 bytes) */
+ ret = nand_change_read_column_op(chip, s * eccsize, p,
+ eccsize, false);
+ if (ret)
+ return ret;
+
+ /* Read the corresponding ECC bytes */
+ ret = nand_change_read_column_op(chip, i, ecc_code,
+ eccbytes, false);
+ if (ret)
+ return ret;
+
+ /* Correct the data */
+ stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc);
+ if (stat == -EBADMSG)
+ /* Check for empty pages with bitflips */
+ stat = nand_check_erased_ecc_chunk(p, eccsize,
+ ecc_code, eccbytes,
+ NULL, 0,
+ eccstrength);
+
+ if (stat < 0) {
+ mtd->ecc_stats.failed++;
+ } else {
+ mtd->ecc_stats.corrected += stat;
+ max_bitflips = max_t(unsigned int, max_bitflips, stat);
+ }
+ }
+
+ /* Read oob */
+ if (oob_required) {
+ ret = nand_change_read_column_op(chip, mtd->writesize,
+ chip->oob_poi, mtd->oobsize,
+ false);
+ if (ret)
+ return ret;
+ }
+
+ return max_bitflips;
+}
+
+static void stm32_fmc2_nfc_read_data(struct nand_chip *chip, void *buf,
+ unsigned int len, bool force_8bit)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ void __iomem *io_addr_r = nfc->data_base[nfc->cs_sel];
+
+ if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+ /* Reconfigure bus width to 8-bit */
+ stm32_fmc2_nfc_set_buswidth_16(nfc, false);
+
+ if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
+ if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
+ *(u8 *)buf = readb_relaxed(io_addr_r);
+ buf += sizeof(u8);
+ len -= sizeof(u8);
+ }
+
+ if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
+ len >= sizeof(u16)) {
+ *(u16 *)buf = readw_relaxed(io_addr_r);
+ buf += sizeof(u16);
+ len -= sizeof(u16);
+ }
+ }
+
+ /* Buf is aligned */
+ while (len >= sizeof(u32)) {
+ *(u32 *)buf = readl_relaxed(io_addr_r);
+ buf += sizeof(u32);
+ len -= sizeof(u32);
+ }
+
+ /* Read remaining bytes */
+ if (len >= sizeof(u16)) {
+ *(u16 *)buf = readw_relaxed(io_addr_r);
+ buf += sizeof(u16);
+ len -= sizeof(u16);
+ }
+
+ if (len)
+ *(u8 *)buf = readb_relaxed(io_addr_r);
+
+ if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+ /* Reconfigure bus width to 16-bit */
+ stm32_fmc2_nfc_set_buswidth_16(nfc, true);
+}
+
+static void stm32_fmc2_nfc_write_data(struct nand_chip *chip, const void *buf,
+ unsigned int len, bool force_8bit)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ void __iomem *io_addr_w = nfc->data_base[nfc->cs_sel];
+
+ if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+ /* Reconfigure bus width to 8-bit */
+ stm32_fmc2_nfc_set_buswidth_16(nfc, false);
+
+ if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) {
+ if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) {
+ writeb_relaxed(*(u8 *)buf, io_addr_w);
+ buf += sizeof(u8);
+ len -= sizeof(u8);
+ }
+
+ if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
+ len >= sizeof(u16)) {
+ writew_relaxed(*(u16 *)buf, io_addr_w);
+ buf += sizeof(u16);
+ len -= sizeof(u16);
+ }
+ }
+
+ /* Buf is aligned */
+ while (len >= sizeof(u32)) {
+ writel_relaxed(*(u32 *)buf, io_addr_w);
+ buf += sizeof(u32);
+ len -= sizeof(u32);
+ }
+
+ /* Write remaining bytes */
+ if (len >= sizeof(u16)) {
+ writew_relaxed(*(u16 *)buf, io_addr_w);
+ buf += sizeof(u16);
+ len -= sizeof(u16);
+ }
+
+ if (len)
+ writeb_relaxed(*(u8 *)buf, io_addr_w);
+
+ if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+ /* Reconfigure bus width to 16-bit */
+ stm32_fmc2_nfc_set_buswidth_16(nfc, true);
+}
+
+static int stm32_fmc2_nfc_waitrdy(struct nand_chip *chip,
+ unsigned long timeout_ms)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ const struct nand_sdr_timings *timings;
+ u32 isr, sr;
+
+ /* Check if there is no pending requests to the NAND flash */
+ if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr,
+ sr & FMC2_SR_NWRF,
+ 1000 * FMC2_TIMEOUT_MS))
+ dev_warn(nfc->dev, "Waitrdy timeout\n");
+
+ /* Wait tWB before R/B# signal is low */
+ timings = nand_get_sdr_timings(nand_get_interface_config(chip));
+ ndelay(PSEC_TO_NSEC(timings->tWB_max));
+
+ /* R/B# signal is low, clear high level flag */
+ regmap_write(nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF);
+
+ /* Wait R/B# signal is high */
+ return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr,
+ isr & FMC2_ISR_IHLF,
+ 1000 * FMC2_TIMEOUT_MS);
+}
+
+static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip,
+ const struct nand_operation *op,
+ bool check_only)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ const struct nand_op_instr *instr = NULL;
+ unsigned int op_id, i, timeout;
+ int ret = 0;
+
+ if (check_only)
+ return 0;
+
+ stm32_fmc2_nfc_select_chip(chip, op->cs);
+
+ for (op_id = 0; op_id < op->ninstrs; op_id++) {
+ instr = &op->instrs[op_id];
+
+ switch (instr->type) {
+ case NAND_OP_CMD_INSTR:
+ writeb_relaxed(instr->ctx.cmd.opcode,
+ nfc->cmd_base[nfc->cs_sel]);
+ break;
+
+ case NAND_OP_ADDR_INSTR:
+ for (i = 0; i < instr->ctx.addr.naddrs; i++)
+ writeb_relaxed(instr->ctx.addr.addrs[i],
+ nfc->addr_base[nfc->cs_sel]);
+ break;
+
+ case NAND_OP_DATA_IN_INSTR:
+ stm32_fmc2_nfc_read_data(chip, instr->ctx.data.buf.in,
+ instr->ctx.data.len,
+ instr->ctx.data.force_8bit);
+ break;
+
+ case NAND_OP_DATA_OUT_INSTR:
+ stm32_fmc2_nfc_write_data(chip, instr->ctx.data.buf.out,
+ instr->ctx.data.len,
+ instr->ctx.data.force_8bit);
+ break;
+
+ case NAND_OP_WAITRDY_INSTR:
+ timeout = instr->ctx.waitrdy.timeout_ms;
+ ret = stm32_fmc2_nfc_waitrdy(chip, timeout);
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc)
+{
+ u32 pcr;
+
+ regmap_read(nfc->regmap, FMC2_PCR, &pcr);
+
+ /* Set CS used to undefined */
+ nfc->cs_sel = -1;
+
+ /* Enable wait feature and nand flash memory bank */
+ pcr |= FMC2_PCR_PWAITEN;
+ pcr |= FMC2_PCR_PBKEN;
+
+ /* Set buswidth to 8 bits mode for identification */
+ pcr &= ~FMC2_PCR_PWID;
+
+ /* ECC logic is disabled */
+ pcr &= ~FMC2_PCR_ECCEN;
+
+ /* Default mode */
+ pcr &= ~FMC2_PCR_ECCALG;
+ pcr &= ~FMC2_PCR_BCHECC;
+ pcr &= ~FMC2_PCR_WEN;
+
+ /* Set default ECC sector size */
+ pcr &= ~FMC2_PCR_ECCSS;
+ pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048);
+
+ /* Set default tclr/tar timings */
+ pcr &= ~FMC2_PCR_TCLR;
+ pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT);
+ pcr &= ~FMC2_PCR_TAR;
+ pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT);
+
+ /* Enable FMC2 controller */
+ if (nfc->dev == nfc->cdev)
+ regmap_update_bits(nfc->regmap, FMC2_BCR1,
+ FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
+
+ regmap_write(nfc->regmap, FMC2_PCR, pcr);
+ regmap_write(nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT);
+ regmap_write(nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT);
+}
+
+static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
+ const struct nand_sdr_timings *sdrt)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
+ struct stm32_fmc2_timings *tims = &nand->timings;
+ unsigned long hclk = clk_get_rate(nfc->clk);
+ unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
+ unsigned long timing, tar, tclr, thiz, twait;
+ unsigned long tset_mem, tset_att, thold_mem, thold_att;
+
+ tar = max_t(unsigned long, hclkp, sdrt->tAR_min);
+ timing = DIV_ROUND_UP(tar, hclkp) - 1;
+ tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
+
+ tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min);
+ timing = DIV_ROUND_UP(tclr, hclkp) - 1;
+ tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK);
+
+ tims->thiz = FMC2_THIZ;
+ thiz = (tims->thiz + 1) * hclkp;
+
+ /*
+ * tWAIT > tRP
+ * tWAIT > tWP
+ * tWAIT > tREA + tIO
+ */
+ twait = max_t(unsigned long, hclkp, sdrt->tRP_min);
+ twait = max_t(unsigned long, twait, sdrt->tWP_min);
+ twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO);
+ timing = DIV_ROUND_UP(twait, hclkp);
+ tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
+
+ /*
+ * tSETUP_MEM > tCS - tWAIT
+ * tSETUP_MEM > tALS - tWAIT
+ * tSETUP_MEM > tDS - (tWAIT - tHIZ)
+ */
+ tset_mem = hclkp;
+ if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait))
+ tset_mem = sdrt->tCS_min - twait;
+ if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait))
+ tset_mem = sdrt->tALS_min - twait;
+ if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
+ (tset_mem < sdrt->tDS_min - (twait - thiz)))
+ tset_mem = sdrt->tDS_min - (twait - thiz);
+ timing = DIV_ROUND_UP(tset_mem, hclkp);
+ tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
+
+ /*
+ * tHOLD_MEM > tCH
+ * tHOLD_MEM > tREH - tSETUP_MEM
+ * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
+ */
+ thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min);
+ if (sdrt->tREH_min > tset_mem &&
+ (thold_mem < sdrt->tREH_min - tset_mem))
+ thold_mem = sdrt->tREH_min - tset_mem;
+ if ((sdrt->tRC_min > tset_mem + twait) &&
+ (thold_mem < sdrt->tRC_min - (tset_mem + twait)))
+ thold_mem = sdrt->tRC_min - (tset_mem + twait);
+ if ((sdrt->tWC_min > tset_mem + twait) &&
+ (thold_mem < sdrt->tWC_min - (tset_mem + twait)))
+ thold_mem = sdrt->tWC_min - (tset_mem + twait);
+ timing = DIV_ROUND_UP(thold_mem, hclkp);
+ tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
+
+ /*
+ * tSETUP_ATT > tCS - tWAIT
+ * tSETUP_ATT > tCLS - tWAIT
+ * tSETUP_ATT > tALS - tWAIT
+ * tSETUP_ATT > tRHW - tHOLD_MEM
+ * tSETUP_ATT > tDS - (tWAIT - tHIZ)
+ */
+ tset_att = hclkp;
+ if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait))
+ tset_att = sdrt->tCS_min - twait;
+ if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait))
+ tset_att = sdrt->tCLS_min - twait;
+ if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait))
+ tset_att = sdrt->tALS_min - twait;
+ if (sdrt->tRHW_min > thold_mem &&
+ (tset_att < sdrt->tRHW_min - thold_mem))
+ tset_att = sdrt->tRHW_min - thold_mem;
+ if (twait > thiz && (sdrt->tDS_min > twait - thiz) &&
+ (tset_att < sdrt->tDS_min - (twait - thiz)))
+ tset_att = sdrt->tDS_min - (twait - thiz);
+ timing = DIV_ROUND_UP(tset_att, hclkp);
+ tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
+
+ /*
+ * tHOLD_ATT > tALH
+ * tHOLD_ATT > tCH
+ * tHOLD_ATT > tCLH
+ * tHOLD_ATT > tCOH
+ * tHOLD_ATT > tDH
+ * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
+ * tHOLD_ATT > tADL - tSETUP_MEM
+ * tHOLD_ATT > tWH - tSETUP_MEM
+ * tHOLD_ATT > tWHR - tSETUP_MEM
+ * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
+ * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
+ */
+ thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min);
+ thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min);
+ if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) &&
+ (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem))
+ thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem;
+ if (sdrt->tADL_min > tset_mem &&
+ (thold_att < sdrt->tADL_min - tset_mem))
+ thold_att = sdrt->tADL_min - tset_mem;
+ if (sdrt->tWH_min > tset_mem &&
+ (thold_att < sdrt->tWH_min - tset_mem))
+ thold_att = sdrt->tWH_min - tset_mem;
+ if (sdrt->tWHR_min > tset_mem &&
+ (thold_att < sdrt->tWHR_min - tset_mem))
+ thold_att = sdrt->tWHR_min - tset_mem;
+ if ((sdrt->tRC_min > tset_att + twait) &&
+ (thold_att < sdrt->tRC_min - (tset_att + twait)))
+ thold_att = sdrt->tRC_min - (tset_att + twait);
+ if ((sdrt->tWC_min > tset_att + twait) &&
+ (thold_att < sdrt->tWC_min - (tset_att + twait)))
+ thold_att = sdrt->tWC_min - (tset_att + twait);
+ timing = DIV_ROUND_UP(thold_att, hclkp);
+ tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK);
+}
+
+static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr,
+ const struct nand_interface_config *conf)
+{
+ const struct nand_sdr_timings *sdrt;
+
+ sdrt = nand_get_sdr_timings(conf);
+ if (IS_ERR(sdrt))
+ return PTR_ERR(sdrt);
+
+ if (conf->timings.mode > 3)
+ return -EOPNOTSUPP;
+
+ if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
+ return 0;
+
+ stm32_fmc2_nfc_calc_timings(chip, sdrt);
+ stm32_fmc2_nfc_timings_init(chip);
+
+ return 0;
+}
+
+static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip)
+{
+ /*
+ * Specific callbacks to read/write a page depending on
+ * the mode (polling/sequencer) and the algo used (Hamming, BCH).
+ */
+ chip->ecc.hwctl = stm32_fmc2_nfc_hwctl;
+ if (chip->ecc.strength == FMC2_ECC_HAM) {
+ /* Hamming is used */
+ chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate;
+ chip->ecc.correct = stm32_fmc2_nfc_ham_correct;
+ chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
+ } else {
+ /* BCH is used */
+ chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate;
+ chip->ecc.correct = stm32_fmc2_nfc_bch_correct;
+ chip->ecc.read_page = stm32_fmc2_nfc_read_page;
+ }
+
+ /* Specific configurations depending on the algo used */
+ if (chip->ecc.strength == FMC2_ECC_HAM)
+ chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
+ else if (chip->ecc.strength == FMC2_ECC_BCH8)
+ chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
+ else
+ chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
+}
+
+static int stm32_fmc2_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->length = ecc->total;
+ oobregion->offset = FMC2_BBM_LEN;
+
+ return 0;
+}
+
+static int stm32_fmc2_nfc_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN;
+ oobregion->offset = ecc->total + FMC2_BBM_LEN;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops stm32_fmc2_nfc_ooblayout_ops = {
+ .ecc = stm32_fmc2_nfc_ooblayout_ecc,
+ .free = stm32_fmc2_nfc_ooblayout_free,
+};
+
+static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength)
+{
+ /* Hamming */
+ if (strength == FMC2_ECC_HAM)
+ return 4;
+
+ /* BCH8 */
+ if (strength == FMC2_ECC_BCH8)
+ return 14;
+
+ /* BCH4 */
+ return 8;
+}
+
+NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes,
+ FMC2_ECC_STEP_SIZE,
+ FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
+
+static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip)
+{
+ struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller);
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int ret;
+
+ /* Default ECC settings in case they are not set in the device tree */
+ if (!chip->ecc.size)
+ chip->ecc.size = FMC2_ECC_STEP_SIZE;
+
+ if (!chip->ecc.strength)
+ chip->ecc.strength = FMC2_ECC_BCH8;
+
+ ret = nand_ecc_choose_conf(chip, &stm32_fmc2_nfc_ecc_caps,
+ mtd->oobsize - FMC2_BBM_LEN);
+ if (ret) {
+ dev_err(nfc->dev, "no valid ECC settings set\n");
+ return ret;
+ }
+
+ if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) {
+ dev_err(nfc->dev, "nand page size is not supported\n");
+ return -EINVAL;
+ }
+
+ if (chip->bbt_options & NAND_BBT_USE_FLASH)
+ chip->bbt_options |= NAND_BBT_NO_OOB;
+
+ stm32_fmc2_nfc_nand_callbacks_setup(chip);
+
+ mtd_set_ooblayout(mtd, &stm32_fmc2_nfc_ooblayout_ops);
+
+ stm32_fmc2_nfc_setup(chip);
+
+ return 0;
+}
+
+static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = {
+ .attach_chip = stm32_fmc2_nfc_attach_chip,
+ .exec_op = stm32_fmc2_nfc_exec_op,
+ .setup_interface = stm32_fmc2_nfc_setup_interface,
+};
+
+static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand)
+{
+ if (nand->wp_gpio)
+ gpiod_set_value(nand->wp_gpio, 1);
+}
+
+static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand)
+{
+ if (nand->wp_gpio)
+ gpiod_set_value(nand->wp_gpio, 0);
+}
+
+static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc,
+ struct device_node *dn)
+{
+ struct stm32_fmc2_nand *nand = &nfc->nand;
+ u32 cs;
+ int ret, i;
+
+ if (!of_get_property(dn, "reg", &nand->ncs))
+ return -EINVAL;
+
+ nand->ncs /= sizeof(u32);
+ if (!nand->ncs) {
+ dev_err(nfc->dev, "invalid reg property size\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < nand->ncs; i++) {
+ ret = of_property_read_u32_index(dn, "reg", i, &cs);
+ if (ret) {
+ dev_err(nfc->dev, "could not retrieve reg property: %d\n",
+ ret);
+ return ret;
+ }
+
+ if (cs >= FMC2_MAX_CE) {
+ dev_err(nfc->dev, "invalid reg value: %d\n", cs);
+ return -EINVAL;
+ }
+
+ if (nfc->cs_assigned & BIT(cs)) {
+ dev_err(nfc->dev, "cs already assigned: %d\n", cs);
+ return -EINVAL;
+ }
+
+ nfc->cs_assigned |= BIT(cs);
+ nand->cs_used[i] = cs;
+ }
+
+ nand->wp_gpio = dev_gpiod_get(nfc->dev, dn, "wp", GPIOD_OUT_HIGH, "wp");
+ if (IS_ERR(nand->wp_gpio)) {
+ ret = PTR_ERR(nand->wp_gpio);
+ if (ret != -ENOENT)
+ return dev_err_probe(nfc->dev, ret,
+ "failed to request WP GPIO\n");
+
+ nand->wp_gpio = NULL;
+ }
+
+ nand_set_flash_node(&nand->chip, dn);
+
+ return 0;
+}
+
+static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc)
+{
+ struct device_node *dn = nfc->dev->of_node;
+ struct device_node *child;
+ int nchips = of_get_child_count(dn);
+ int ret = 0;
+
+ if (!nchips) {
+ dev_err(nfc->dev, "NAND chip not defined\n");
+ return -EINVAL;
+ }
+
+ if (nchips > 1) {
+ dev_err(nfc->dev, "too many NAND chips defined\n");
+ return -EINVAL;
+ }
+
+ for_each_child_of_node(dn, child) {
+ ret = stm32_fmc2_nfc_parse_child(nfc, child);
+ if (ret < 0) {
+ of_node_put(child);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc)
+{
+ struct device *dev = nfc->dev;
+ bool ebi_found = false;
+
+ if (dev->parent && of_device_is_compatible(dev->parent->of_node,
+ "st,stm32mp1-fmc2-ebi"))
+ ebi_found = true;
+
+ if (of_device_is_compatible(dev->of_node, "st,stm32mp1-fmc2-nfc")) {
+ if (ebi_found) {
+ nfc->cdev = dev->parent;
+
+ return 0;
+ }
+
+ return -EINVAL;
+ }
+
+ if (ebi_found)
+ return -EINVAL;
+
+ nfc->cdev = dev;
+
+ return 0;
+}
+
+static int __init stm32_fmc2_nfc_probe(struct device *dev)
+{
+ struct stm32_fmc2_nfc *nfc;
+ struct stm32_fmc2_nand *nand;
+ struct mtd_info *mtd;
+ struct nand_chip *chip;
+ struct resource cres;
+ int chip_cs, mem_region, ret;
+ int start_region = 0;
+
+ nfc = kzalloc(sizeof(*nfc), GFP_KERNEL);
+ if (!nfc)
+ return -ENOMEM;
+
+ nfc->dev = dev;
+ nand_controller_init(&nfc->base);
+ nfc->base.ops = &stm32_fmc2_nfc_controller_ops;
+
+ ret = stm32_fmc2_nfc_set_cdev(nfc);
+ if (ret)
+ return ret;
+
+ ret = stm32_fmc2_nfc_parse_dt(nfc);
+ if (ret)
+ return ret;
+
+ ret = of_address_to_resource(nfc->cdev->of_node, 0, &cres);
+ if (ret)
+ return ret;
+
+ nfc->regmap = device_node_to_regmap(nfc->cdev->of_node);
+ if (IS_ERR(nfc->regmap))
+ return PTR_ERR(nfc->regmap);
+
+ if (nfc->dev == nfc->cdev)
+ start_region = 1;
+
+ for (chip_cs = 0, mem_region = start_region; chip_cs < FMC2_MAX_CE;
+ chip_cs++, mem_region += 3) {
+ if (!(nfc->cs_assigned & BIT(chip_cs)))
+ continue;
+
+ nfc->data_base[chip_cs] = of_iomap(dev->of_node, mem_region);
+ if (IS_ERR(nfc->data_base[chip_cs]))
+ return PTR_ERR(nfc->data_base[chip_cs]);
+
+ nfc->cmd_base[chip_cs] = of_iomap(dev->of_node, mem_region + 1);
+ if (IS_ERR(nfc->cmd_base[chip_cs]))
+ return PTR_ERR(nfc->cmd_base[chip_cs]);
+
+ nfc->addr_base[chip_cs] = of_iomap(dev->of_node, mem_region + 2);
+ if (IS_ERR(nfc->addr_base[chip_cs]))
+ return PTR_ERR(nfc->addr_base[chip_cs]);
+ }
+
+ nfc->clk = clk_get(nfc->cdev, NULL);
+ if (IS_ERR(nfc->clk))
+ return PTR_ERR(nfc->clk);
+
+ ret = clk_prepare_enable(nfc->clk);
+ if (ret) {
+ dev_err(dev, "can not enable the clock\n");
+ return ret;
+ }
+
+ ret = device_reset_us(dev, 2);
+ if (ret)
+ goto err_clk_disable;
+
+ stm32_fmc2_nfc_init(nfc);
+
+ nand = &nfc->nand;
+ chip = &nand->chip;
+ mtd = nand_to_mtd(chip);
+ mtd->dev.parent = dev;
+
+ chip->controller = &nfc->base;
+ chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE;
+
+ /* Default ECC settings */
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.size = FMC2_ECC_STEP_SIZE;
+ chip->ecc.strength = FMC2_ECC_BCH8;
+
+ stm32_fmc2_nfc_wp_disable(nand);
+
+ /* Scan to find existence of the device */
+ ret = nand_scan(chip, nand->ncs);
+ if (ret)
+ goto err_wp_enable;
+
+ ret = add_mtd_nand_device(mtd, "nand");
+ if (ret)
+ goto err_nand_cleanup;
+
+ return 0;
+
+err_nand_cleanup:
+ nand_cleanup(chip);
+
+err_wp_enable:
+ stm32_fmc2_nfc_wp_enable(nand);
+
+err_clk_disable:
+ clk_disable_unprepare(nfc->clk);
+
+ return ret;
+}
+
+static __maybe_unused struct of_device_id stm32_fmc2_nfc_match[] = {
+ { .compatible = "st,stm32mp15-fmc2", },
+ { .compatible = "st,stm32mp1-fmc2-nfc", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match);
+
+static struct driver stm32_fmc2_nfc_driver = {
+ .name = "stm32_fmc2_nfc",
+ .probe = stm32_fmc2_nfc_probe,
+ .of_compatible = DRV_OF_COMPAT(stm32_fmc2_nfc_match),
+};
+coredevice_platform_driver(stm32_fmc2_nfc_driver);
--
2.39.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support
2023-08-30 10:47 [PATCH 1/3] memory: Add driver for FMC2 External Bus Interface on STM32MP SoCs Alexander Shiyan
2023-08-30 10:47 ` [PATCH 2/3] mtd: nand: Add driver for NAND controller " Alexander Shiyan
@ 2023-08-30 10:47 ` Alexander Shiyan
2023-08-30 14:41 ` Ahmad Fatoum
1 sibling, 1 reply; 10+ messages in thread
From: Alexander Shiyan @ 2023-08-30 10:47 UTC (permalink / raw)
To: barebox; +Cc: Alexander Shiyan
Add basic support for the MyirTech MYD-YA15XC-T development board [1].
...
deep-probe: supported due to myir,myc-stm32mp15x
stm32mp-init: detected STM32MP151AAC Rev.Z
STM32 RCC reset reason POR (MP_RSTSR: 0x00000015)
Boot from SD...
psci psci.of: detected version 1.1
stpmic1-i2c stpmic10: PMIC Chip Version: 0x21
stm32-usbphyc 5a006000.usbphyc@5a006000.of: registered rev:1.0
nand_base: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
nand_base: Micron MT29F2G08ABAEAWP
nand_base: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
nand_read_bbt: bad block at 0x000000d60000
nand_read_bbt: bad block at 0x000000fa0000
nand_read_bbt: bad block at 0x00000d460000
stm32_sdmmc 58005000.mmc@58005000.of: registered as mmc0
mmc0: detected SD card version 2.0
mmc0: registered mmc0
stm32_sdmmc 58007000.mmc@58007000.of: registered as mmc1
stm32-iwdg 5a002000.watchdog@5a002000.of: probed
Product name: MYC-YA151C-256N256D-65-I-T
Product serial: TW202103290400145
malloc space: 0xc7ef7a80 -> 0xcfdef4ff (size 127 MiB)
envfs: no envfs (magic mismatch) - envfs never written?
NOTICE: ubi0: scanning is finished
NOTICE: ubi0: registering /dev/nand0.system.ubi
NOTICE: ubi0: registering kernel as /dev/nand0.system.ubi.kernel
NOTICE: ubi0: registering root as /dev/nand0.system.ubi.root
NOTICE: ubi0: registering bbox as /dev/nand0.system.ubi.bbox
NOTICE: ubi0: attached mtd0 (name "nand0.system", size 237 MiB) to ubi0
NOTICE: ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
NOTICE: ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
NOTICE: ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
NOTICE: ubi0: good PEBs: 1895, bad PEBs: 5, corrupted PEBs: 0
NOTICE: ubi0: user volume: 3, internal volumes: 1, max. volumes count: 128
NOTICE: ubi0: max/mean erase counter: 1/0, WL threshold: 65536, image sequence number: 3389077539
NOTICE: ubi0: available PEBs: 529, total reserved PEBs: 1366, PEBs reserved for bad PEB handling: 35
Hit m for menu or any to stop autoboot: 2
barebox@MYC-YA151C-256N256D-65-I-T:/
...
[1] https://www.myirtech.com/list.asp?id=659
Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/myirtech-stm32/Makefile | 4 +
arch/arm/boards/myirtech-stm32/board.c | 143 +++++++
arch/arm/boards/myirtech-stm32/lowlevel.c | 27 ++
arch/arm/dts/Makefile | 1 +
arch/arm/dts/stm32mp15x-myirtech-myc.dtsi | 351 +++++++++++++++++
arch/arm/dts/stm32mp15x-myirtech-myd.dts | 458 ++++++++++++++++++++++
arch/arm/mach-stm32mp/Kconfig | 7 +
images/Makefile.stm32mp | 2 +
9 files changed, 994 insertions(+)
create mode 100644 arch/arm/boards/myirtech-stm32/Makefile
create mode 100644 arch/arm/boards/myirtech-stm32/board.c
create mode 100644 arch/arm/boards/myirtech-stm32/lowlevel.c
create mode 100644 arch/arm/dts/stm32mp15x-myirtech-myc.dtsi
create mode 100644 arch/arm/dts/stm32mp15x-myirtech-myd.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 83a3179185..2ff10329b2 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -140,6 +140,7 @@ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/
obj-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp15xx-dkx/
obj-$(CONFIG_MACH_STM32MP13XX_DK) += stm32mp13xx-dk/
obj-$(CONFIG_MACH_LXA_MC1) += lxa-mc1/
+obj-$(CONFIG_MACH_MYIRTECH_STM32MP1) += myirtech-stm32/
obj-$(CONFIG_MACH_STM32MP15X_EV1) += stm32mp15x-ev1/
obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += technexion-pico-hobbit/
obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/
diff --git a/arch/arm/boards/myirtech-stm32/Makefile b/arch/arm/boards/myirtech-stm32/Makefile
new file mode 100644
index 0000000000..511d4971fa
--- /dev/null
+++ b/arch/arm/boards/myirtech-stm32/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/myirtech-stm32/board.c b/arch/arm/boards/myirtech-stm32/board.c
new file mode 100644
index 0000000000..187a3b8a59
--- /dev/null
+++ b/arch/arm/boards/myirtech-stm32/board.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <bootsource.h>
+#include <common.h>
+#include <deep-probe.h>
+#include <envfs.h>
+#include <environment.h>
+#include <globalvar.h>
+#include <init.h>
+#include <machine_id.h>
+#include <net.h>
+#include <of.h>
+#include <mach/stm32mp/bbu.h>
+
+struct id_eeprom {
+ u8 hrcw_primary[0x10];
+ u8 pn[64];
+ u8 sn[64];
+ u8 mac0[6];
+ u8 mac1[6];
+} __packed;
+
+static int stm32mp15x_myirtech_serial_fixup(struct device_node *root, void *unused)
+{
+ char *serial;
+
+ serial = basprintf("%s", getenv("global.machine_id"));
+ of_set_property(root, "serial-number", serial, strlen(serial) + 1, 1);
+ free(serial);
+
+ return 0;
+}
+
+static int stm32mp15x_myirtech_eeprom_init(void)
+{
+ struct id_eeprom eeprom;
+ struct cdev *cdev;
+ char str[64];
+ int len;
+
+ if (!of_machine_is_compatible("myir,myc-stm32mp15x"))
+ return 0;
+
+ cdev = cdev_by_name("eeprom0");
+ if (!cdev) {
+ pr_err("Can't find EEPROM\n");
+ return -ENODEV;
+ }
+
+ if (cdev_read(cdev, &eeprom, sizeof(eeprom), 0, 0) < 0) {
+ pr_err("Can't read EEPROM\n");
+ return -EIO;
+ }
+
+ len = (eeprom.pn[0] - '0');
+ if ((len < 8) || (len > 64)) {
+ pr_err("Unable to get product name\n");
+ return -EINVAL;
+ }
+
+ strncpy(str, &eeprom.pn[1], len);
+ str[len] = '\0';
+ pr_info("Product name: %s\n", str);
+ globalvar_add_simple("model", str);
+
+ len = (eeprom.sn[0] - '0');
+ if ((len < 8) || (len > 64)) {
+ pr_err("Unable to get product serial\n");
+ return -EINVAL;
+ }
+
+ strncpy(str, &eeprom.sn[1], len);
+ str[len] = '\0';
+ pr_info("Product serial: %s\n", str);
+ machine_id_set_hashable(str, len);
+ of_register_fixup(stm32mp15x_myirtech_serial_fixup, NULL);
+
+ if (!is_valid_ether_addr(eeprom.mac0)) {
+ int i, j;
+
+ /* Make fixed MAC-address based on serial number */
+ memcpy(eeprom.mac0, str, sizeof(eeprom.mac0));
+ for (i = sizeof(eeprom.mac0); i < len; i++)
+ for (j = 0; j < sizeof(eeprom.mac0); j++)
+ eeprom.mac0[j] ^= str[i];
+ }
+
+ eth_register_ethaddr(0, eeprom.mac0);
+
+ return 0;
+}
+of_populate_initcall(stm32mp15x_myirtech_eeprom_init);
+
+static int stm32mp15x_myirtech_probe(struct device *dev)
+{
+ int instance = bootsource_get_instance(), def = -1;
+ const enum bootsource bs = bootsource_get();
+
+ barebox_set_hostname("myir-stm32");
+
+ switch (bs) {
+ case BOOTSOURCE_MMC:
+ if (instance == 0) {
+ of_device_enable_path("/chosen/environment-sd");
+ pr_info("Boot from SD...\n");
+ } else {
+ of_device_enable_path("/chosen/environment-emmc");
+ pr_info("Boot from eMMC...\n");
+ }
+ def = instance;
+ break;
+ case BOOTSOURCE_NAND:
+ of_device_enable_path("/chosen/environment-nand");
+ pr_info("Boot from NAND...\n");
+ def = 2;
+ break;
+ default:
+ return 0;
+ }
+
+ stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl",
+ (def == 0) ? BBU_HANDLER_FLAG_DEFAULT : 0);
+
+ stm32mp_bbu_mmc_register_handler("emmc", "/dev/mmc1.ssbl",
+ (def == 1) ? BBU_HANDLER_FLAG_DEFAULT : 0);
+
+ //TODO: NAND
+
+ return 0;
+}
+
+static const struct of_device_id stm32mp15x_myirtech_of_match[] = {
+ { .compatible = "myir,myc-stm32mp15x" },
+ { },
+};
+BAREBOX_DEEP_PROBE_ENABLE(stm32mp15x_myirtech_of_match);
+
+static struct driver stm32mp15x_myirtech_board_driver = {
+ .name = "board-myirtech-stm32",
+ .probe = stm32mp15x_myirtech_probe,
+ .of_compatible = stm32mp15x_myirtech_of_match,
+};
+device_platform_driver(stm32mp15x_myirtech_board_driver);
diff --git a/arch/arm/boards/myirtech-stm32/lowlevel.c b/arch/arm/boards/myirtech-stm32/lowlevel.c
new file mode 100644
index 0000000000..715a8eeb96
--- /dev/null
+++ b/arch/arm/boards/myirtech-stm32/lowlevel.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <mach/stm32mp/entry.h>
+#include <debug_ll.h>
+
+extern char __dtb_z_stm32mp15x_myirtech_myd_start[];
+
+static void setup_uart(void)
+{
+ /* first stage has set up the UART, so nothing to do here */
+ putc_ll('>');
+}
+
+ENTRY_FUNCTION(start_stm32mp15x_myir, r0, r1, r2)
+{
+ void *fdt;
+
+ stm32mp_cpu_lowlevel_init();
+
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ setup_uart();
+
+ fdt = __dtb_z_stm32mp15x_myirtech_myd_start + get_runtime_offset();
+
+ stm32mp1_barebox_entry(fdt);
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 81e11bb6a3..b882c4942b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -143,6 +143,7 @@ lwl-$(CONFIG_MACH_SEEED_ODYSSEY) += stm32mp157c-odyssey.dtb.o
lwl-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp157c-dk2.dtb.o stm32mp157a-dk1.dtb.o
lwl-$(CONFIG_MACH_STM32MP13XX_DK) += stm32mp135f-dk.dtb.o
lwl-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o
+lwl-$(CONFIG_MACH_MYIRTECH_STM32MP1) += stm32mp15x-myirtech-myd.dtb.o
lwl-$(CONFIG_MACH_STM32MP15X_EV1) += stm32mp157c-ev1.dtb.o
lwl-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o
lwl-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o
diff --git a/arch/arm/dts/stm32mp15x-myirtech-myc.dtsi b/arch/arm/dts/stm32mp15x-myirtech-myc.dtsi
new file mode 100644
index 0000000000..7f843ad2ab
--- /dev/null
+++ b/arch/arm/dts/stm32mp15x-myirtech-myc.dtsi
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
+
+#include <arm/stm32mp151.dtsi>
+#include <arm/stm32mp15-pinctrl.dtsi>
+#include <arm/stm32mp15xxac-pinctrl.dtsi>
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ model = "MYIR MYC-YA15XC-T";
+ compatible = "myir,myc-stm32mp15x", "st,stm32mp151";
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ i2c4 = &i2c5;
+ i2c5 = &i2c6;
+ };
+
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x10000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mcuram2: mcuram2@10000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10000000 0x40000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@10040000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10040000 0x1000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@10041000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10041000 0x1000>;
+ no-map;
+ };
+
+ vdev0buffer: vdev0buffer@10042000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10042000 0x4000>;
+ no-map;
+ };
+
+ mcuram: mcuram@30000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x30000000 0x40000>;
+ no-map;
+ };
+
+ retram: retram@38000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x38000000 0x10000>;
+ no-map;
+ };
+
+ optee: optee@0xde000000 {
+ reg = <0xde000000 0x02000000>;
+ no-map;
+ };
+ };
+
+ vin_som: vin_som {
+ compatible = "regulator-fixed";
+ regulator-name = "vin_som";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ led_cpu: led_cpu {
+ label = "som:cpu";
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_CPU;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ linux,default-trigger = LED_FUNCTION_CPU;
+ };
+ };
+};
+
+&bsec {
+ board_id: board_id@ec {
+ reg = <0xec 0x4>;
+ st,non-secure-otp;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vddcore>;
+};
+
+&dts {
+ status = "okay";
+};
+
+&fmc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&fmc_pins_a>;
+ pinctrl-1 = <&fmc_sleep_pins_a>;
+ status = "okay";
+
+ nand-controller@4,0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand_parts: partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "fsbl1";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "fsbl2";
+ reg = <0x80000 0x80000>;
+ };
+
+ partition@100000 {
+ label = "matadata1";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "matadata2";
+ reg = <0x180000 0x80000>;
+ };
+
+ partition@200000 {
+ label = "fip-a1";
+ reg = <0x200000 0x400000>;
+ };
+
+ partition@600000 {
+ label = "fip-a2";
+ reg = <0x600000 0x400000>;
+ };
+
+ partition@a00000 {
+ label = "fip-b1";
+ reg = <0xa00000 0x400000>;
+ };
+
+ partition@e00000 {
+ label = "fip-b2";
+ reg = <0xe00000 0x400000>;
+ };
+
+ partition@1200000 {
+ label = "system";
+ reg = <0x01200000 0>;
+ };
+ };
+ };
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c4_pins_a>;
+ pinctrl-1 = <&i2c4_sleep_pins_a>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+ buck1-supply = <&vin_som>;
+ buck2-supply = <&vin_som>;
+ buck3-supply = <&vin_som>;
+ buck4-supply = <&vin_som>;
+ ldo1-supply = <&v3v3>;
+ ldo4-supply = <&vin_som>;
+ vref_ddr-supply = <&vin_som>;
+ boost-supply = <&vin_som>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ vdda: ldo1 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-always-on;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ regulator-active-discharge;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ regulator-active-discharge;
+ };
+ };
+
+ onkey: onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ };
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ pagesize = <32>;
+ num-addresses = <8>;
+ wp-gpios = <&gpioa 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ };
+};
+
+&ipcc {
+ status = "okay";
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&m4_rproc {
+ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
+ <&vdev0vring1>, <&vdev0buffer>;
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
+ mbox-names = "vq0", "vq1", "shutdown", "detach";
+ interrupt-parent = <&exti>;
+ interrupts = <68 IRQ_TYPE_EDGE_RISING>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd>;
+ mmc-ddr-3_3v;
+ status = "okay";
+};
diff --git a/arch/arm/dts/stm32mp15x-myirtech-myd.dts b/arch/arm/dts/stm32mp15x-myirtech-myd.dts
new file mode 100644
index 0000000000..b15a4312d4
--- /dev/null
+++ b/arch/arm/dts/stm32mp15x-myirtech-myd.dts
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
+
+/dts-v1/;
+
+#include "stm32mp15x-myirtech-myc.dtsi"
+
+#include <dt-bindings/net/qca-ar803x.h>
+
+/ {
+ model = "MYIR MYD-YA15XC-T";
+ compatible = "myir,myd-stm32mp15x", "myir,myc-stm32mp15x", "st,stm32mp151";
+
+ aliases {
+ ethernet0 = ðernet0;
+ serial0 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 100000 0>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <256>;
+ default-brightness-level = <255>;
+ };
+
+ panel: panel {
+ compatible = "panel-lvds";
+ backlight = <&backlight>;
+ data-mapping = "vesa-24";
+ enable-gpios = <&gpioi 3 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
+ power-supply = <&vdd_3v3>;
+ height-mm = <0>;
+ width-mm = <0>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+ };
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_3v3: vdd_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&v3v3>;
+ };
+};
+
+&leds {
+ led_live: led_live {
+ label = "board:live";
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&extgpio 4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = LED_FUNCTION_HEARTBEAT;
+ panic-indicator;
+ };
+};
+
+&vin_som {
+ vin-supply = <&vin>;
+};
+
+&i2c2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins &i2c2_pins_z>;
+ pinctrl-1 = <&i2c2_sleep_pins &i2c2_sleep_pins_z>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ extgpio: pcf8575@20 {
+ compatible = "nxp,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ typec: stusb1600@28 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&stusb1600_pins>;
+ compatible = "st,stusb1600";
+ reg = <0x28>;
+ interrupt-parent = <&gpioa>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&vin>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ power-opmode = "default";
+
+ port {
+ con_usbotg_hs_ep: endpoint {
+ remote-endpoint = <&usbotg_hs_ep>;
+ };
+ };
+ };
+ };
+
+ rx8025: rtc@32 {
+ compatible = "epson,rx8025";
+ reg = <0x32>;
+ };
+};
+
+ðernet0 {
+ pinctrl-0 = <ðernet0_rgmii_pins_a>;
+ pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ max-speed = <1000>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ reset-gpios = <&gpiog 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-delay-us = <10000>;
+ reset-post-delay-us = <2000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@6 {
+ reg = <6>;
+ qca,clk-out-frequency = <125000000>;
+ qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
+ };
+ };
+};
+
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins>;
+ pinctrl-1 = <<dc_sleep_pins>;
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&sai1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai1_pins>;
+ pinctrl-1 = <&sai1_sleep_pins>;
+ clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "x8k", "x11k";
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ cd-gpios = <&gpioa 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ disable-wp;
+ st,neg-edge;
+ vmmc-supply = <&vdd>;
+ status = "okay";
+};
+
+&spi5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi5_pins>;
+ cs-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>,
+ <&gpiof 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ status = "okay";
+};
+
+&timers2 {
+ status = "okay";
+
+ pwm2: pwm {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&tim2_pwm_pins>;
+ pinctrl-1 = <&tim2_pwm_sleep_pins>;
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&uart4_pins>;
+ pinctrl-1 = <&uart4_sleep_pins>;
+ pinctrl-2 = <&uart4_idle_pins>;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ phy-names = "usb";
+ status = "okay";
+};
+
+&usbotg_hs {
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ usb-role-switch;
+ vbus-supply = <&vbus_otg>;
+ status = "okay";
+
+ port {
+ usbotg_hs_ep: endpoint {
+ remote-endpoint = <&con_usbotg_hs_ep>;
+ };
+ };
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vin>;
+ };
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+ st,tune-hs-dc-level = <2>;
+ st,enable-fs-rftime-tuning;
+ st,enable-hs-rftime-reduction;
+ st,trim-hs-current = <15>;
+ st,trim-hs-impedance = <1>;
+ st,tune-squelch-level = <3>;
+ st,tune-hs-rx-offset = <2>;
+ st,no-lsfs-sc;
+};
+
+&pinctrl {
+ i2c2_pins: i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF4)>; /* I2C2_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins: i2c2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, ANALOG)>; /* I2C2_SCL */
+ };
+ };
+
+ ltdc_pins: ltdc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
+ <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
+ <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 14, AF14)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
+ <STM32_PINMUX('I', 5, AF14)>, /* LCD_B5 */
+ <STM32_PINMUX('I', 6, AF14)>, /* LCD_B6 */
+ <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ ltdc_sleep_pins: ltdc-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('E', 14, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('I', 5, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('I', 6, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
+ sai1_pins: sai1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 2, AF6)>, /* SAI1_SD_A */
+ <STM32_PINMUX('F', 8, AF6)>, /* SAI1_SCK_B */
+ <STM32_PINMUX('F', 9, AF6)>, /* SAI1_FS_B */
+ <STM32_PINMUX('F', 7, AF6)>; /* SAI1_MCLK_B */
+ slew-rate = <0>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 6, AF6)>; /* SAI1_SD_B */
+ bias-disable;
+ };
+ };
+
+ sai1_sleep_pins: sai1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* SAI1_SD_A */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* SAI1_SCK_B */
+ <STM32_PINMUX('F', 9, ANALOG)>, /* SAI1_FS_B */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* SAI1_MCLK_B */
+ <STM32_PINMUX('F', 6, ANALOG)>; /* SAI1_SD_B */
+ };
+ };
+
+ spi5_pins: spi5-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 6, AF5)>, /* SPI5_SCK */
+ <STM32_PINMUX('F', 11, AF5)>; /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('H', 7, AF5)>; /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
+ stusb1600_pins: stusb1600-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* STUSB1600 IRQ */
+ bias-pull-up;
+ };
+ };
+
+ tim2_pwm_pins: tim2-pwm-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 8, AF1)>; /* TIM2_CH1 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ tim2_pwm_sleep_pins: tim2-pwm-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 8, ANALOG)>; /* TIM2_CH1 */
+ };
+ };
+
+ uart4_pins: uart4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 11, AF6)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_idle_pins: uart4-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 11, AF6)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
+
+ uart4_sleep_pins: uart4-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
+ <STM32_PINMUX('A', 11, ANALOG)>; /* UART4_RX */
+ };
+ };
+};
+
+&pinctrl_z {
+ i2c2_pins_z: i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 7, AF3)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_sleep_pins_z: i2c2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C2_SDA */
+ };
+ };
+};
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index bc0a48d64c..358aad940c 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -29,6 +29,13 @@ config MACH_LXA_MC1
select ARCH_STM32MP157
bool "Linux Automation MC-1 board"
+config MACH_MYIRTECH_STM32MP1
+ bool "MYIR Tech Limited SOMs"
+ select ARCH_STM32MP157
+ select MACHINE_ID
+ help
+ Say Y here if you are using a STM32MP15x based MYIR SOM
+
config MACH_SEEED_ODYSSEY
select ARCH_STM32MP157
bool "Seeed Studio Odyssey"
diff --git a/images/Makefile.stm32mp b/images/Makefile.stm32mp
index 59d6572207..344dd41eb7 100644
--- a/images/Makefile.stm32mp
+++ b/images/Makefile.stm32mp
@@ -36,6 +36,8 @@ $(call build_stm32mp_image, CONFIG_MACH_STM32MP15X_EV1, start_stm32mp15x_ev1, st
$(call build_stm32mp_image, CONFIG_MACH_LXA_MC1, start_stm32mp157c_lxa_mc1, stm32mp157c-lxa-mc1)
+$(call build_stm32mp_image, CONFIG_MACH_MYIRTECH_STM32MP1, start_stm32mp15x_myir, stm32mp15x-myir)
+
$(call build_stm32mp_image, CONFIG_MACH_PROTONIC_STM32MP1, start_prtt1a, prtt1a)
$(call build_stm32mp_image, CONFIG_MACH_PROTONIC_STM32MP1, start_prtt1s, prtt1s)
$(call build_stm32mp_image, CONFIG_MACH_PROTONIC_STM32MP1, start_prtt1c, prtt1c)
--
2.39.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support
2023-08-30 10:47 ` [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support Alexander Shiyan
@ 2023-08-30 14:41 ` Ahmad Fatoum
2023-08-31 6:40 ` Alexander Shiyan
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Ahmad Fatoum @ 2023-08-30 14:41 UTC (permalink / raw)
To: Alexander Shiyan, barebox
Hello Alexander,
Thanks for your patch. A few comments below.
On 30.08.23 12:47, Alexander Shiyan wrote:
> Add basic support for the MyirTech MYD-YA15XC-T development board [1].
> ...
> deep-probe: supported due to myir,myc-stm32mp15x
> stm32mp-init: detected STM32MP151AAC Rev.Z
> STM32 RCC reset reason POR (MP_RSTSR: 0x00000015)
> Boot from SD...
> psci psci.of: detected version 1.1
> stpmic1-i2c stpmic10: PMIC Chip Version: 0x21
> stm32-usbphyc 5a006000.usbphyc@5a006000.of: registered rev:1.0
> nand_base: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
> nand_base: Micron MT29F2G08ABAEAWP
> nand_base: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
> Bad block table found at page 131008, version 0x01
> Bad block table found at page 130944, version 0x01
> nand_read_bbt: bad block at 0x000000d60000
> nand_read_bbt: bad block at 0x000000fa0000
> nand_read_bbt: bad block at 0x00000d460000
> stm32_sdmmc 58005000.mmc@58005000.of: registered as mmc0
> mmc0: detected SD card version 2.0
> mmc0: registered mmc0
> stm32_sdmmc 58007000.mmc@58007000.of: registered as mmc1
> stm32-iwdg 5a002000.watchdog@5a002000.of: probed
> Product name: MYC-YA151C-256N256D-65-I-T
> Product serial: TW202103290400145
> malloc space: 0xc7ef7a80 -> 0xcfdef4ff (size 127 MiB)
> envfs: no envfs (magic mismatch) - envfs never written?
> NOTICE: ubi0: scanning is finished
> NOTICE: ubi0: registering /dev/nand0.system.ubi
> NOTICE: ubi0: registering kernel as /dev/nand0.system.ubi.kernel
> NOTICE: ubi0: registering root as /dev/nand0.system.ubi.root
> NOTICE: ubi0: registering bbox as /dev/nand0.system.ubi.bbox
> NOTICE: ubi0: attached mtd0 (name "nand0.system", size 237 MiB) to ubi0
> NOTICE: ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
> NOTICE: ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
> NOTICE: ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
> NOTICE: ubi0: good PEBs: 1895, bad PEBs: 5, corrupted PEBs: 0
> NOTICE: ubi0: user volume: 3, internal volumes: 1, max. volumes count: 128
> NOTICE: ubi0: max/mean erase counter: 1/0, WL threshold: 65536, image sequence number: 3389077539
> NOTICE: ubi0: available PEBs: 529, total reserved PEBs: 1366, PEBs reserved for bad PEB handling: 35
>
> Hit m for menu or any to stop autoboot: 2
> barebox@MYC-YA151C-256N256D-65-I-T:/
> ...
>
> [1] https://www.myirtech.com/list.asp?id=659
>
> Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
> ---
> arch/arm/boards/Makefile | 1 +
> arch/arm/boards/myirtech-stm32/Makefile | 4 +
> arch/arm/boards/myirtech-stm32/board.c | 143 +++++++
> arch/arm/boards/myirtech-stm32/lowlevel.c | 27 ++
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/stm32mp15x-myirtech-myc.dtsi | 351 +++++++++++++++++
> arch/arm/dts/stm32mp15x-myirtech-myd.dts | 458 ++++++++++++++++++++++
> arch/arm/mach-stm32mp/Kconfig | 7 +
> images/Makefile.stm32mp | 2 +
> 9 files changed, 994 insertions(+)
> create mode 100644 arch/arm/boards/myirtech-stm32/Makefile
> create mode 100644 arch/arm/boards/myirtech-stm32/board.c
> create mode 100644 arch/arm/boards/myirtech-stm32/lowlevel.c
> create mode 100644 arch/arm/dts/stm32mp15x-myirtech-myc.dtsi
> create mode 100644 arch/arm/dts/stm32mp15x-myirtech-myd.dts
>
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index 83a3179185..2ff10329b2 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -140,6 +140,7 @@ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/
> obj-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp15xx-dkx/
> obj-$(CONFIG_MACH_STM32MP13XX_DK) += stm32mp13xx-dk/
> obj-$(CONFIG_MACH_LXA_MC1) += lxa-mc1/
> +obj-$(CONFIG_MACH_MYIRTECH_STM32MP1) += myirtech-stm32/
> obj-$(CONFIG_MACH_STM32MP15X_EV1) += stm32mp15x-ev1/
> obj-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += technexion-pico-hobbit/
> obj-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += technexion-wandboard/
> diff --git a/arch/arm/boards/myirtech-stm32/Makefile b/arch/arm/boards/myirtech-stm32/Makefile
> new file mode 100644
> index 0000000000..511d4971fa
> --- /dev/null
> +++ b/arch/arm/boards/myirtech-stm32/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +lwl-y += lowlevel.o
> +obj-y += board.o
> diff --git a/arch/arm/boards/myirtech-stm32/board.c b/arch/arm/boards/myirtech-stm32/board.c
> new file mode 100644
> index 0000000000..187a3b8a59
> --- /dev/null
> +++ b/arch/arm/boards/myirtech-stm32/board.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <bootsource.h>
> +#include <common.h>
> +#include <deep-probe.h>
> +#include <envfs.h>
> +#include <environment.h>
> +#include <globalvar.h>
> +#include <init.h>
> +#include <machine_id.h>
> +#include <net.h>
> +#include <of.h>
> +#include <mach/stm32mp/bbu.h>
> +
> +struct id_eeprom {
> + u8 hrcw_primary[0x10];
> + u8 pn[64];
> + u8 sn[64];
> + u8 mac0[6];
> + u8 mac1[6];
> +} __packed;
You could describe this as nvmem-cells in the DT and you'd automatically
get the MAC addresses assigned.
> +
> +static int stm32mp15x_myirtech_serial_fixup(struct device_node *root, void *unused)
> +{
> + char *serial;
> +
> + serial = basprintf("%s", getenv("global.machine_id"));
> + of_set_property(root, "serial-number", serial, strlen(serial) + 1, 1);
> + free(serial);
> +
> + return 0;
> +}
> +
> +static int stm32mp15x_myirtech_eeprom_init(void)
> +{
> + struct id_eeprom eeprom;
> + struct cdev *cdev;
> + char str[64];
> + int len;
> +
> + if (!of_machine_is_compatible("myir,myc-stm32mp15x"))
> + return 0;
> +
> + cdev = cdev_by_name("eeprom0");
> + if (!cdev) {
> + pr_err("Can't find EEPROM\n");
> + return -ENODEV;
> + }
I think using nvmem cells would make the code less verbose.
> +
> + if (cdev_read(cdev, &eeprom, sizeof(eeprom), 0, 0) < 0) {
> + pr_err("Can't read EEPROM\n");
> + return -EIO;
> + }
> +
> + len = (eeprom.pn[0] - '0');
> + if ((len < 8) || (len > 64)) {
> + pr_err("Unable to get product name\n");
> + return -EINVAL;
> + }
> +
> + strncpy(str, &eeprom.pn[1], len);
> + str[len] = '\0';
> + pr_info("Product name: %s\n", str);
> + globalvar_add_simple("model", str);
barebox_set_model()?
> +
> + len = (eeprom.sn[0] - '0');
> + if ((len < 8) || (len > 64)) {
> + pr_err("Unable to get product serial\n");
> + return -EINVAL;
> + }
> +
> + strncpy(str, &eeprom.sn[1], len);
> + str[len] = '\0';
> + pr_info("Product serial: %s\n", str);
Would barebox_set_serial_number() work for you?
> + machine_id_set_hashable(str, len);
Any particular reason why not to just use the SoC serial?
> + of_register_fixup(stm32mp15x_myirtech_serial_fixup, NULL);
> +
> + if (!is_valid_ether_addr(eeprom.mac0)) {
> + int i, j;
> +
> + /* Make fixed MAC-address based on serial number */
> + memcpy(eeprom.mac0, str, sizeof(eeprom.mac0));
> + for (i = sizeof(eeprom.mac0); i < len; i++)
> + for (j = 0; j < sizeof(eeprom.mac0); j++)
> + eeprom.mac0[j] ^= str[i];
> + }
> +
> + eth_register_ethaddr(0, eeprom.mac0);
You could check if the nvmem cell exists and only do the fixup
if it doesn't. Check Marco's recent Debix patches for an example
of how to call nvmem from board code.
> +
> + return 0;
> +}
> +of_populate_initcall(stm32mp15x_myirtech_eeprom_init);
Why can't this be moved into the probe function below?
You may need to lookup the cdev device by alias though.
> +static int stm32mp15x_myirtech_probe(struct device *dev)
> +{
> + int instance = bootsource_get_instance(), def = -1;
> + const enum bootsource bs = bootsource_get();
> +
> + barebox_set_hostname("myir-stm32");
> +
> + switch (bs) {
> + case BOOTSOURCE_MMC:
> + if (instance == 0) {
> + of_device_enable_path("/chosen/environment-sd");
> + pr_info("Boot from SD...\n");
> + } else {
> + of_device_enable_path("/chosen/environment-emmc");
> + pr_info("Boot from eMMC...\n");
> + }
> + def = instance;
> + break;
> + case BOOTSOURCE_NAND:
> + of_device_enable_path("/chosen/environment-nand");
> + pr_info("Boot from NAND...\n");
> + def = 2;
> + break;
> + default:
> + return 0;
> + }
> +
> + stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl",
> + (def == 0) ? BBU_HANDLER_FLAG_DEFAULT : 0);
> +
> + stm32mp_bbu_mmc_register_handler("emmc", "/dev/mmc1.ssbl",
> + (def == 1) ? BBU_HANDLER_FLAG_DEFAULT : 0);
What version of TF-A do you use? New versions only support FIP, so
stm32mp_bbu_mmc_fip_register() is what you actually want to use.
> +
> + //TODO: NAND
> +
> + return 0;
> +}
> +
> +static const struct of_device_id stm32mp15x_myirtech_of_match[] = {
> + { .compatible = "myir,myc-stm32mp15x" },
> + { },
> +};
> +BAREBOX_DEEP_PROBE_ENABLE(stm32mp15x_myirtech_of_match);
> +
> +static struct driver stm32mp15x_myirtech_board_driver = {
> + .name = "board-myirtech-stm32",
> + .probe = stm32mp15x_myirtech_probe,
> + .of_compatible = stm32mp15x_myirtech_of_match,
> +};
> +device_platform_driver(stm32mp15x_myirtech_board_driver);
> diff --git a/arch/arm/boards/myirtech-stm32/lowlevel.c b/arch/arm/boards/myirtech-stm32/lowlevel.c
> new file mode 100644
> index 0000000000..715a8eeb96
> --- /dev/null
> +++ b/arch/arm/boards/myirtech-stm32/lowlevel.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <common.h>
> +#include <mach/stm32mp/entry.h>
> +#include <debug_ll.h>
> +
> +extern char __dtb_z_stm32mp15x_myirtech_myd_start[];
> +
> +static void setup_uart(void)
> +{
> + /* first stage has set up the UART, so nothing to do here */
> + putc_ll('>');
> +}
> +
> +ENTRY_FUNCTION(start_stm32mp15x_myir, r0, r1, r2)
> +{
> + void *fdt;
> +
> + stm32mp_cpu_lowlevel_init();
> +
> + if (IS_ENABLED(CONFIG_DEBUG_LL))
> + setup_uart();
> +
> + fdt = __dtb_z_stm32mp15x_myirtech_myd_start + get_runtime_offset();
> +
> + stm32mp1_barebox_entry(fdt);
Same question: Do you use an old TF-A or why do you need a specific entry
point instead of barebox-stm32mp-generic-bl33.img?
> +}
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 81e11bb6a3..b882c4942b 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -143,6 +143,7 @@ lwl-$(CONFIG_MACH_SEEED_ODYSSEY) += stm32mp157c-odyssey.dtb.o
> lwl-$(CONFIG_MACH_STM32MP15XX_DKX) += stm32mp157c-dk2.dtb.o stm32mp157a-dk1.dtb.o
> lwl-$(CONFIG_MACH_STM32MP13XX_DK) += stm32mp135f-dk.dtb.o
> lwl-$(CONFIG_MACH_LXA_MC1) += stm32mp157c-lxa-mc1.dtb.o
> +lwl-$(CONFIG_MACH_MYIRTECH_STM32MP1) += stm32mp15x-myirtech-myd.dtb.o
> lwl-$(CONFIG_MACH_STM32MP15X_EV1) += stm32mp157c-ev1.dtb.o
> lwl-$(CONFIG_MACH_SCB9328) += imx1-scb9328.dtb.o
> lwl-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o
> diff --git a/arch/arm/dts/stm32mp15x-myirtech-myc.dtsi b/arch/arm/dts/stm32mp15x-myirtech-myc.dtsi
> new file mode 100644
> index 0000000000..7f843ad2ab
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp15x-myirtech-myc.dtsi
> @@ -0,0 +1,351 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
> +
> +#include <arm/stm32mp151.dtsi>
> +#include <arm/stm32mp15-pinctrl.dtsi>
> +#include <arm/stm32mp15xxac-pinctrl.dtsi>
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/mfd/st,stpmic1.h>
> +
> +/ {
> + model = "MYIR MYC-YA15XC-T";
> + compatible = "myir,myc-stm32mp15x", "st,stm32mp151";
> +
> + aliases {
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> + i2c3 = &i2c4;
> + i2c4 = &i2c5;
> + i2c5 = &i2c6;
> + };
You can add these to arch/arm/dts/stm32mp151.dtsi, so it's fixed for
other boards as well.
> +
> + memory@c0000000 {
> + device_type = "memory";
> + reg = <0xc0000000 0x10000000>;
> + };
barebox will dynamically determine memory size and fix it up,
so you can drop this node.
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + mcuram2: mcuram2@10000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x10000000 0x40000>;
> + no-map;
> + };
> +
> + vdev0vring0: vdev0vring0@10040000 {
> + compatible = "shared-dma-pool";
> + reg = <0x10040000 0x1000>;
> + no-map;
> + };
> +
> + vdev0vring1: vdev0vring1@10041000 {
> + compatible = "shared-dma-pool";
> + reg = <0x10041000 0x1000>;
> + no-map;
> + };
> +
> + vdev0buffer: vdev0buffer@10042000 {
> + compatible = "shared-dma-pool";
> + reg = <0x10042000 0x4000>;
> + no-map;
> + };
> +
> + mcuram: mcuram@30000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x30000000 0x40000>;
> + no-map;
> + };
> +
> + retram: retram@38000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x38000000 0x10000>;
> + no-map;
> + };
> +
> + optee: optee@0xde000000 {
> + reg = <0xde000000 0x02000000>;
> + no-map;
> + };
> + };
> +
> + vin_som: vin_som {
> + compatible = "regulator-fixed";
> + regulator-name = "vin_som";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + leds: leds {
> + compatible = "gpio-leds";
> +
> + led_cpu: led_cpu {
> + label = "som:cpu";
> + color = <LED_COLOR_ID_BLUE>;
> + default-state = "off";
> + function = LED_FUNCTION_CPU;
> + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
> + linux,default-trigger = LED_FUNCTION_CPU;
> + };
> + };
> +};
> +
> +&bsec {
> + board_id: board_id@ec {
> + reg = <0xec 0x4>;
> + st,non-secure-otp;
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&vddcore>;
> +};
> +
> +&dts {
> + status = "okay";
> +};
> +
> +&fmc {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&fmc_pins_a>;
> + pinctrl-1 = <&fmc_sleep_pins_a>;
> + status = "okay";
> +
> + nand-controller@4,0 {
> + status = "okay";
> +
> + nand@0 {
> + reg = <0>;
> + nand-on-flash-bbt;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + nand_parts: partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "fsbl1";
> + reg = <0x0 0x80000>;
> + };
> +
> + partition@80000 {
> + label = "fsbl2";
> + reg = <0x80000 0x80000>;
> + };
> +
> + partition@100000 {
> + label = "matadata1";
> + reg = <0x100000 0x80000>;
> + };
> +
> + partition@180000 {
> + label = "matadata2";
> + reg = <0x180000 0x80000>;
> + };
> +
> + partition@200000 {
> + label = "fip-a1";
> + reg = <0x200000 0x400000>;
> + };
> +
> + partition@600000 {
> + label = "fip-a2";
> + reg = <0x600000 0x400000>;
> + };
> +
> + partition@a00000 {
> + label = "fip-b1";
> + reg = <0xa00000 0x400000>;
> + };
> +
> + partition@e00000 {
> + label = "fip-b2";
> + reg = <0xe00000 0x400000>;
> + };
> +
> + partition@1200000 {
> + label = "system";
> + reg = <0x01200000 0>;
> + };
> + };
> + };
> + };
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c4_pins_a>;
> + pinctrl-1 = <&i2c4_sleep_pins_a>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + pmic: stpmic@33 {
> + compatible = "st,stpmic1";
> + reg = <0x33>;
> + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + regulators {
> + compatible = "st,stpmic1-regulators";
> + buck1-supply = <&vin_som>;
> + buck2-supply = <&vin_som>;
> + buck3-supply = <&vin_som>;
> + buck4-supply = <&vin_som>;
> + ldo1-supply = <&v3v3>;
> + ldo4-supply = <&vin_som>;
> + vref_ddr-supply = <&vin_som>;
> + boost-supply = <&vin_som>;
> + pwr_sw1-supply = <&bst_out>;
> + pwr_sw2-supply = <&bst_out>;
> +
> + vddcore: buck1 {
> + regulator-name = "vddcore";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + regulator-initial-mode = <0>;
> + regulator-over-current-protection;
> + };
> +
> + vdd_ddr: buck2 {
> + regulator-name = "vdd_ddr";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + regulator-initial-mode = <0>;
> + regulator-over-current-protection;
> + };
> +
> + vdd: buck3 {
> + regulator-name = "vdd";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + st,mask-reset;
> + regulator-initial-mode = <0>;
> + regulator-over-current-protection;
> + };
> +
> + v3v3: buck4 {
> + regulator-name = "v3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-over-current-protection;
> + regulator-initial-mode = <0>;
> + };
> +
> + vdda: ldo1 {
> + regulator-name = "vdda";
> + regulator-min-microvolt = <1700000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vtt_ddr: ldo3 {
> + regulator-name = "vtt_ddr";
> + regulator-always-on;
> + };
> +
> + vdd_usb: ldo4 {
> + regulator-name = "vdd_usb";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vref_ddr: vref_ddr {
> + regulator-name = "vref_ddr";
> + regulator-always-on;
> + regulator-over-current-protection;
> + };
> +
> + bst_out: boost {
> + regulator-name = "bst_out";
> + };
> +
> + vbus_otg: pwr_sw1 {
> + regulator-name = "vbus_otg";
> + regulator-active-discharge;
> + };
> +
> + vbus_sw: pwr_sw2 {
> + regulator-name = "vbus_sw";
> + regulator-active-discharge;
> + };
> + };
> +
> + onkey: onkey {
> + compatible = "st,stpmic1-onkey";
> + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
> + interrupt-names = "onkey-falling", "onkey-rising";
> + power-off-time-sec = <10>;
> + };
> + };
> +
> + eeprom: eeprom@50 {
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + pagesize = <32>;
> + num-addresses = <8>;
> + wp-gpios = <&gpioa 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + };
> +};
> +
> +&ipcc {
> + status = "okay";
> +};
> +
> +&iwdg2 {
> + timeout-sec = <32>;
> + status = "okay";
> +};
> +
> +&m4_rproc {
> + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
> + <&vdev0vring1>, <&vdev0buffer>;
> + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
> + mbox-names = "vq0", "vq1", "shutdown", "detach";
> + interrupt-parent = <&exti>;
> + interrupts = <68 IRQ_TYPE_EDGE_RISING>;
> + status = "okay";
> +};
> +
> +&pwr_regulators {
> + vdd-supply = <&vdd>;
> + vdd_3v3_usbfs-supply = <&vdd_usb>;
> +};
> +
> +&rng1 {
> + status = "okay";
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +&sdmmc2 {
> + pinctrl-names = "default", "opendrain", "sleep";
> + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
> + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
> + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
> + non-removable;
> + no-sd;
> + no-sdio;
> + st,neg-edge;
> + bus-width = <8>;
> + vmmc-supply = <&v3v3>;
> + vqmmc-supply = <&vdd>;
> + mmc-ddr-3_3v;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/stm32mp15x-myirtech-myd.dts b/arch/arm/dts/stm32mp15x-myirtech-myd.dts
> new file mode 100644
> index 0000000000..b15a4312d4
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp15x-myirtech-myd.dts
> @@ -0,0 +1,458 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
> +
> +/dts-v1/;
> +
> +#include "stm32mp15x-myirtech-myc.dtsi"
> +
> +#include <dt-bindings/net/qca-ar803x.h>
> +
> +/ {
> + model = "MYIR MYD-YA15XC-T";
> + compatible = "myir,myd-stm32mp15x", "myir,myc-stm32mp15x", "st,stm32mp151";
> +
> + aliases {
> + ethernet0 = ðernet0;
> + serial0 = &uart4;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm2 0 100000 0>;
> + brightness-levels = <0 255>;
> + num-interpolated-steps = <256>;
> + default-brightness-level = <255>;
> + };
> +
> + panel: panel {
> + compatible = "panel-lvds";
> + backlight = <&backlight>;
> + data-mapping = "vesa-24";
> + enable-gpios = <&gpioi 3 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
> + power-supply = <&vdd_3v3>;
> + height-mm = <0>;
> + width-mm = <0>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <<dc_ep0_out>;
> + };
> + };
> + };
Do you intend to enable a boot splash? :>
I only tested the LTDC driver with parallel output.
> +
> + vin: vin {
> + compatible = "regulator-fixed";
> + regulator-name = "vin";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +
> + vdd_3v3: vdd_3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + vin-supply = <&v3v3>;
> + };
> +};
> +
> +&leds {
> + led_live: led_live {
> + label = "board:live";
> + color = <LED_COLOR_ID_BLUE>;
> + default-state = "off";
> + function = LED_FUNCTION_HEARTBEAT;
> + gpios = <&extgpio 4 GPIO_ACTIVE_LOW>;
> + linux,default-trigger = LED_FUNCTION_HEARTBEAT;
> + panic-indicator;
> + };
> +};
> +
> +&vin_som {
> + vin-supply = <&vin>;
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c2_pins &i2c2_pins_z>;
> + pinctrl-1 = <&i2c2_sleep_pins &i2c2_sleep_pins_z>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + extgpio: pcf8575@20 {
> + compatible = "nxp,pcf8575";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + typec: stusb1600@28 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&stusb1600_pins>;
> + compatible = "st,stusb1600";
> + reg = <0x28>;
> + interrupt-parent = <&gpioa>;
> + interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
> + vdd-supply = <&vin>;
> +
> + connector {
> + compatible = "usb-c-connector";
> + label = "USB-C";
> + power-role = "dual";
> + power-opmode = "default";
> +
> + port {
> + con_usbotg_hs_ep: endpoint {
> + remote-endpoint = <&usbotg_hs_ep>;
> + };
> + };
> + };
> + };
FYI, there's a simple Type C driver framework now, so you could port
the stusb1600 driver from Linux quite easily if you want to base
decisions on whether the device is in device or host mode.
> +
> + rx8025: rtc@32 {
> + compatible = "epson,rx8025";
> + reg = <0x32>;
> + };
> +};
> +
> +ðernet0 {
> + pinctrl-0 = <ðernet0_rgmii_pins_a>;
> + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
> + pinctrl-names = "default", "sleep";
> + max-speed = <1000>;
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + reset-gpios = <&gpiog 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
> + reset-delay-us = <10000>;
> + reset-post-delay-us = <2000>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phy0: ethernet-phy@6 {
> + reg = <6>;
> + qca,clk-out-frequency = <125000000>;
> + qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
> + };
> + };
> +};
> +
> +<dc {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <<dc_pins>;
> + pinctrl-1 = <<dc_sleep_pins>;
> + status = "okay";
> +
> + port {
> + ltdc_ep0_out: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&panel_in>;
> + };
> + };
> +};
> +
> +&sai1 {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sai1_pins>;
> + pinctrl-1 = <&sai1_sleep_pins>;
> + clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
> + clock-names = "pclk", "x8k", "x11k";
> + status = "okay";
> +};
> +
> +&sdmmc1 {
> + pinctrl-names = "default", "opendrain", "sleep";
> + pinctrl-0 = <&sdmmc1_b4_pins_a>;
> + pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
> + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> + cd-gpios = <&gpioa 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
> + disable-wp;
> + st,neg-edge;
> + vmmc-supply = <&vdd>;
> + status = "okay";
> +};
> +
> +&spi5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi5_pins>;
> + cs-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>,
> + <&gpiof 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
> + status = "okay";
> +};
> +
> +&timers2 {
> + status = "okay";
> +
> + pwm2: pwm {
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&tim2_pwm_pins>;
> + pinctrl-1 = <&tim2_pwm_sleep_pins>;
> + status = "okay";
> + };
> +};
> +
> +&uart4 {
> + pinctrl-names = "default", "sleep", "idle";
> + pinctrl-0 = <&uart4_pins>;
> + pinctrl-1 = <&uart4_sleep_pins>;
> + pinctrl-2 = <&uart4_idle_pins>;
> + status = "okay";
> +};
> +
> +&usbh_ehci {
> + phys = <&usbphyc_port0>;
> + phy-names = "usb";
> + status = "okay";
> +};
> +
> +&usbotg_hs {
> + phys = <&usbphyc_port1 0>;
> + phy-names = "usb2-phy";
> + usb-role-switch;
> + vbus-supply = <&vbus_otg>;
> + status = "okay";
> +
> + port {
> + usbotg_hs_ep: endpoint {
> + remote-endpoint = <&con_usbotg_hs_ep>;
> + };
> + };
> +};
> +
> +&usbphyc {
> + status = "okay";
> +};
> +
> +&usbphyc_port0 {
> + phy-supply = <&vdd_usb>;
> + st,tune-hs-dc-level = <2>;
> + st,enable-fs-rftime-tuning;
> + st,enable-hs-rftime-reduction;
> + st,trim-hs-current = <15>;
> + st,trim-hs-impedance = <1>;
> + st,tune-squelch-level = <3>;
> + st,tune-hs-rx-offset = <2>;
> + st,no-lsfs-sc;
> +
> + connector {
> + compatible = "usb-a-connector";
> + vbus-supply = <&vin>;
> + };
> +};
> +
> +&usbphyc_port1 {
> + phy-supply = <&vdd_usb>;
> + st,tune-hs-dc-level = <2>;
> + st,enable-fs-rftime-tuning;
> + st,enable-hs-rftime-reduction;
> + st,trim-hs-current = <15>;
> + st,trim-hs-impedance = <1>;
> + st,tune-squelch-level = <3>;
> + st,tune-hs-rx-offset = <2>;
> + st,no-lsfs-sc;
> +};
> +
> +&pinctrl {
> + i2c2_pins: i2c2-0 {
> + pins {
> + pinmux = <STM32_PINMUX('H', 4, AF4)>; /* I2C2_SCL */
> + bias-disable;
> + drive-open-drain;
> + slew-rate = <0>;
> + };
> + };
> +
> + i2c2_sleep_pins: i2c2-sleep-0 {
> + pins {
> + pinmux = <STM32_PINMUX('H', 4, ANALOG)>; /* I2C2_SCL */
> + };
> + };
> +
> + ltdc_pins: ltdc-0 {
> + pins {
> + pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
> + <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
> + <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
> + <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
> + <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
> + <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
> + <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
> + <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
> + <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
> + <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
> + <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
> + <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
> + <STM32_PINMUX('E', 14, AF14)>, /* LCD_G0 */
> + <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
> + <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
> + <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
> + <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
> + <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
> + <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
> + <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
> + <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
> + <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
> + <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
> + <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
> + <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
> + <STM32_PINMUX('I', 5, AF14)>, /* LCD_B5 */
> + <STM32_PINMUX('I', 6, AF14)>, /* LCD_B6 */
> + <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <1>;
> + };
> + };
> +
> + ltdc_sleep_pins: ltdc-sleep-0 {
> + pins {
> + pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
> + <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
> + <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
> + <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
> + <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
> + <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
> + <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
> + <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
> + <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
> + <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
> + <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
> + <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
> + <STM32_PINMUX('E', 14, ANALOG)>, /* LCD_G0 */
> + <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
> + <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
> + <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
> + <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
> + <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
> + <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
> + <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
> + <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
> + <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
> + <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
> + <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
> + <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
> + <STM32_PINMUX('I', 5, ANALOG)>, /* LCD_B5 */
> + <STM32_PINMUX('I', 6, ANALOG)>, /* LCD_B6 */
> + <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */
> + };
> + };
> +
> + sai1_pins: sai1-0 {
> + pins1 {
> + pinmux = <STM32_PINMUX('B', 2, AF6)>, /* SAI1_SD_A */
> + <STM32_PINMUX('F', 8, AF6)>, /* SAI1_SCK_B */
> + <STM32_PINMUX('F', 9, AF6)>, /* SAI1_FS_B */
> + <STM32_PINMUX('F', 7, AF6)>; /* SAI1_MCLK_B */
> + slew-rate = <0>;
> + drive-push-pull;
> + bias-disable;
> + };
> + pins2 {
> + pinmux = <STM32_PINMUX('F', 6, AF6)>; /* SAI1_SD_B */
> + bias-disable;
> + };
> + };
> +
> + sai1_sleep_pins: sai1-sleep-0 {
> + pins {
> + pinmux = <STM32_PINMUX('B', 2, ANALOG)>, /* SAI1_SD_A */
> + <STM32_PINMUX('F', 8, ANALOG)>, /* SAI1_SCK_B */
> + <STM32_PINMUX('F', 9, ANALOG)>, /* SAI1_FS_B */
> + <STM32_PINMUX('F', 7, ANALOG)>, /* SAI1_MCLK_B */
> + <STM32_PINMUX('F', 6, ANALOG)>; /* SAI1_SD_B */
> + };
> + };
> +
> + spi5_pins: spi5-0 {
> + pins {
> + pinmux = <STM32_PINMUX('H', 6, AF5)>, /* SPI5_SCK */
> + <STM32_PINMUX('F', 11, AF5)>; /* SPI5_MOSI */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <1>;
> + };
> + pins2 {
> + pinmux = <STM32_PINMUX('H', 7, AF5)>; /* SPI5_MISO */
> + bias-disable;
> + };
> + };
> +
> + stusb1600_pins: stusb1600-0 {
> + pins {
> + pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* STUSB1600 IRQ */
> + bias-pull-up;
> + };
> + };
> +
> + tim2_pwm_pins: tim2-pwm-0 {
> + pins {
> + pinmux = <STM32_PINMUX('G', 8, AF1)>; /* TIM2_CH1 */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + };
> +
> + tim2_pwm_sleep_pins: tim2-pwm-sleep-0 {
> + pins {
> + pinmux = <STM32_PINMUX('G', 8, ANALOG)>; /* TIM2_CH1 */
> + };
> + };
> +
> + uart4_pins: uart4-0 {
> + pins1 {
> + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
> + bias-disable;
> + drive-push-pull;
> + slew-rate = <0>;
> + };
> + pins2 {
> + pinmux = <STM32_PINMUX('A', 11, AF6)>; /* UART4_RX */
> + bias-disable;
> + };
> + };
> +
> + uart4_idle_pins: uart4-idle-0 {
> + pins1 {
> + pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
> + };
> + pins2 {
> + pinmux = <STM32_PINMUX('A', 11, AF6)>; /* UART4_RX */
> + bias-disable;
> + };
> + };
> +
> + uart4_sleep_pins: uart4-sleep-0 {
> + pins1 {
> + pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
> + <STM32_PINMUX('A', 11, ANALOG)>; /* UART4_RX */
> + };
> + };
> +};
> +
> +&pinctrl_z {
> + i2c2_pins_z: i2c2-0 {
> + pins {
> + pinmux = <STM32_PINMUX('Z', 7, AF3)>; /* I2C2_SDA */
> + bias-disable;
> + drive-open-drain;
> + slew-rate = <0>;
> + };
> + };
> +
> + i2c2_sleep_pins_z: i2c2-sleep-0 {
> + pins {
> + pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C2_SDA */
> + };
> + };
> +};
> diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
> index bc0a48d64c..358aad940c 100644
> --- a/arch/arm/mach-stm32mp/Kconfig
> +++ b/arch/arm/mach-stm32mp/Kconfig
> @@ -29,6 +29,13 @@ config MACH_LXA_MC1
> select ARCH_STM32MP157
> bool "Linux Automation MC-1 board"
>
> +config MACH_MYIRTECH_STM32MP1
> + bool "MYIR Tech Limited SOMs"
> + select ARCH_STM32MP157
> + select MACHINE_ID
> + help
> + Say Y here if you are using a STM32MP15x based MYIR SOM
> +
> config MACH_SEEED_ODYSSEY
> select ARCH_STM32MP157
> bool "Seeed Studio Odyssey"
> diff --git a/images/Makefile.stm32mp b/images/Makefile.stm32mp
> index 59d6572207..344dd41eb7 100644
> --- a/images/Makefile.stm32mp
> +++ b/images/Makefile.stm32mp
> @@ -36,6 +36,8 @@ $(call build_stm32mp_image, CONFIG_MACH_STM32MP15X_EV1, start_stm32mp15x_ev1, st
>
> $(call build_stm32mp_image, CONFIG_MACH_LXA_MC1, start_stm32mp157c_lxa_mc1, stm32mp157c-lxa-mc1)
>
> +$(call build_stm32mp_image, CONFIG_MACH_MYIRTECH_STM32MP1, start_stm32mp15x_myir, stm32mp15x-myir)
> +
> $(call build_stm32mp_image, CONFIG_MACH_PROTONIC_STM32MP1, start_prtt1a, prtt1a)
> $(call build_stm32mp_image, CONFIG_MACH_PROTONIC_STM32MP1, start_prtt1s, prtt1s)
> $(call build_stm32mp_image, CONFIG_MACH_PROTONIC_STM32MP1, start_prtt1c, prtt1c)
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support
2023-08-30 14:41 ` Ahmad Fatoum
@ 2023-08-31 6:40 ` Alexander Shiyan
2023-09-04 7:17 ` Sascha Hauer
2023-08-31 9:41 ` Alexander Shiyan
2023-09-11 16:09 ` Ahmad Fatoum
2 siblings, 1 reply; 10+ messages in thread
From: Alexander Shiyan @ 2023-08-31 6:40 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hello Ahmad.
> Thanks for your patch. A few comments below.
...
> > +ENTRY_FUNCTION(start_stm32mp15x_myir, r0, r1, r2)
> > +{
> > + void *fdt;
> > +
> > + stm32mp_cpu_lowlevel_init();
> > +
> > + if (IS_ENABLED(CONFIG_DEBUG_LL))
> > + setup_uart();
> > +
> > + fdt = __dtb_z_stm32mp15x_myirtech_myd_start + get_runtime_offset();
> > +
> > + stm32mp1_barebox_entry(fdt);
>
> Same question: Do you use an old TF-A or why do you need a specific entry
> point instead of barebox-stm32mp-generic-bl33.img?
Initially, I used the old version of TF-A, to facilitate the first
start-up of the board.
Now I'm using new version and FIP, so yes, this piece of code can be removed.
Thanks for the comments on the patch, I'll rework some parts of the code.
2 Sascha: Is it possible to commit the first two parts of the patch
now to minimize the overall work?
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support
2023-08-30 14:41 ` Ahmad Fatoum
2023-08-31 6:40 ` Alexander Shiyan
@ 2023-08-31 9:41 ` Alexander Shiyan
2023-09-05 8:25 ` Ahmad Fatoum
2023-09-11 16:09 ` Ahmad Fatoum
2 siblings, 1 reply; 10+ messages in thread
From: Alexander Shiyan @ 2023-08-31 9:41 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
> > +struct id_eeprom {
> > + u8 hrcw_primary[0x10];
> > + u8 pn[64];
> > + u8 sn[64];
> > + u8 mac0[6];
> > + u8 mac1[6];
> > +} __packed;
>
> You could describe this as nvmem-cells in the DT and you'd automatically
> get the MAC addresses assigned.
...
> > + if (!is_valid_ether_addr(eeprom.mac0)) {
> > + int i, j;
> > +
> > + /* Make fixed MAC-address based on serial number */
> > + memcpy(eeprom.mac0, str, sizeof(eeprom.mac0));
> > + for (i = sizeof(eeprom.mac0); i < len; i++)
> > + for (j = 0; j < sizeof(eeprom.mac0); j++)
> > + eeprom.mac0[j] ^= str[i];
> > + }
> > +
> > + eth_register_ethaddr(0, eeprom.mac0);
> You could check if the nvmem cell exists and only do the fixup
> if it doesn't. Check Marco's recent Debix patches for an example
> of how to call nvmem from board code.
I can't find a way to know if an MAC address that was automatically
assigned via nvmem is valid.
So in this case we always need to use eth_register_ethaddr() manually?
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support
2023-08-31 6:40 ` Alexander Shiyan
@ 2023-09-04 7:17 ` Sascha Hauer
0 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2023-09-04 7:17 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: Ahmad Fatoum, barebox
Hi Alexander,
On Thu, Aug 31, 2023 at 09:40:16AM +0300, Alexander Shiyan wrote:
> Hello Ahmad.
>
> > Thanks for your patch. A few comments below.
> ...
> > > +ENTRY_FUNCTION(start_stm32mp15x_myir, r0, r1, r2)
> > > +{
> > > + void *fdt;
> > > +
> > > + stm32mp_cpu_lowlevel_init();
> > > +
> > > + if (IS_ENABLED(CONFIG_DEBUG_LL))
> > > + setup_uart();
> > > +
> > > + fdt = __dtb_z_stm32mp15x_myirtech_myd_start + get_runtime_offset();
> > > +
> > > + stm32mp1_barebox_entry(fdt);
> >
> > Same question: Do you use an old TF-A or why do you need a specific entry
> > point instead of barebox-stm32mp-generic-bl33.img?
>
> Initially, I used the old version of TF-A, to facilitate the first
> start-up of the board.
> Now I'm using new version and FIP, so yes, this piece of code can be removed.
>
> Thanks for the comments on the patch, I'll rework some parts of the code.
>
> 2 Sascha: Is it possible to commit the first two parts of the patch
> now to minimize the overall work?
Just did that.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support
2023-08-31 9:41 ` Alexander Shiyan
@ 2023-09-05 8:25 ` Ahmad Fatoum
2023-09-11 16:01 ` Ahmad Fatoum
0 siblings, 1 reply; 10+ messages in thread
From: Ahmad Fatoum @ 2023-09-05 8:25 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
On 31.08.23 11:41, Alexander Shiyan wrote:
>>> +struct id_eeprom {
>>> + u8 hrcw_primary[0x10];
>>> + u8 pn[64];
>>> + u8 sn[64];
>>> + u8 mac0[6];
>>> + u8 mac1[6];
>>> +} __packed;
>>
>> You could describe this as nvmem-cells in the DT and you'd automatically
>> get the MAC addresses assigned.
> ...
>>> + if (!is_valid_ether_addr(eeprom.mac0)) {
>>> + int i, j;
>>> +
>>> + /* Make fixed MAC-address based on serial number */
>>> + memcpy(eeprom.mac0, str, sizeof(eeprom.mac0));
>>> + for (i = sizeof(eeprom.mac0); i < len; i++)
>>> + for (j = 0; j < sizeof(eeprom.mac0); j++)
>>> + eeprom.mac0[j] ^= str[i];
>>> + }
>>> +
>>> + eth_register_ethaddr(0, eeprom.mac0);
>> You could check if the nvmem cell exists and only do the fixup
>> if it doesn't. Check Marco's recent Debix patches for an example
>> of how to call nvmem from board code.
>
> I can't find a way to know if an MAC address that was automatically
> assigned via nvmem is valid.
> So in this case we always need to use eth_register_ethaddr() manually?
You could fetch the nvmem cell and verify it yourself before MAC address
is assigned. What I'd like to have eventually is a Kconfig option to
generate a MAC address out of the serial number automatically if one was
set and if not, only then fall back to randomization.
I even have patches somewhere. Let me check.
Cheers,
Ahmad
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support
2023-09-05 8:25 ` Ahmad Fatoum
@ 2023-09-11 16:01 ` Ahmad Fatoum
0 siblings, 0 replies; 10+ messages in thread
From: Ahmad Fatoum @ 2023-09-11 16:01 UTC (permalink / raw)
To: Alexander Shiyan; +Cc: barebox
On 05.09.23 10:25, Ahmad Fatoum wrote:
> On 31.08.23 11:41, Alexander Shiyan wrote:
>>>> +struct id_eeprom {
>>>> + u8 hrcw_primary[0x10];
>>>> + u8 pn[64];
>>>> + u8 sn[64];
>>>> + u8 mac0[6];
>>>> + u8 mac1[6];
>>>> +} __packed;
>>>
>>> You could describe this as nvmem-cells in the DT and you'd automatically
>>> get the MAC addresses assigned.
>> ...
>>>> + if (!is_valid_ether_addr(eeprom.mac0)) {
>>>> + int i, j;
>>>> +
>>>> + /* Make fixed MAC-address based on serial number */
>>>> + memcpy(eeprom.mac0, str, sizeof(eeprom.mac0));
>>>> + for (i = sizeof(eeprom.mac0); i < len; i++)
>>>> + for (j = 0; j < sizeof(eeprom.mac0); j++)
>>>> + eeprom.mac0[j] ^= str[i];
>>>> + }
>>>> +
>>>> + eth_register_ethaddr(0, eeprom.mac0);
>>> You could check if the nvmem cell exists and only do the fixup
>>> if it doesn't. Check Marco's recent Debix patches for an example
>>> of how to call nvmem from board code.
>>
>> I can't find a way to know if an MAC address that was automatically
>> assigned via nvmem is valid.
>> So in this case we always need to use eth_register_ethaddr() manually?
>
> You could fetch the nvmem cell and verify it yourself before MAC address
> is assigned. What I'd like to have eventually is a Kconfig option to
> generate a MAC address out of the serial number automatically if one was
> set and if not, only then fall back to randomization.
>
> I even have patches somewhere. Let me check.
I reworked them a bit and just sent them out. Looking forward to your feedback.
>
> Cheers,
> Ahmad
>
>>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support
2023-08-30 14:41 ` Ahmad Fatoum
2023-08-31 6:40 ` Alexander Shiyan
2023-08-31 9:41 ` Alexander Shiyan
@ 2023-09-11 16:09 ` Ahmad Fatoum
2 siblings, 0 replies; 10+ messages in thread
From: Ahmad Fatoum @ 2023-09-11 16:09 UTC (permalink / raw)
To: Alexander Shiyan, barebox
Hi,
On 30.08.23 16:41, Ahmad Fatoum wrote:
> On 30.08.23 12:47, Alexander Shiyan wrote:
>> +
>> + len = (eeprom.sn[0] - '0');
>> + if ((len < 8) || (len > 64)) {
>> + pr_err("Unable to get product serial\n");
>> + return -EINVAL;
>> + }
>> +
>> + strncpy(str, &eeprom.sn[1], len);
>> + str[len] = '\0';
>> + pr_info("Product serial: %s\n", str);
>
> Would barebox_set_serial_number() work for you?
>
>> + machine_id_set_hashable(str, len);
>
> Any particular reason why not to just use the SoC serial?
We had a discussion two years ago[1], where it turned out that the unique
ID on STM32MP1 SoCs wasn't randomized, so it's probably better board vendors
indeed set their own if that would have more entropy. The ugly thing about
that is that the last call to machine_id_set_hasable wins, so I wanted to
change it to be set in device tree instead, e.g.:
/chosen { barebox,machine-id-path = &bsec; }.
Alas I never sent a v2. Anyways, existing users will have to be grandfathered
in, so it's fine for me if you choose to call machine_id_set_hashable from
your board code.
[1]: https://lore.barebox.org/barebox/dad3cc59-5a25-9889-88a5-58467f576d8e@pengutronix.de/
>> +ENTRY_FUNCTION(start_stm32mp15x_myir, r0, r1, r2)
>> +{
>> + void *fdt;
>> +
>> + stm32mp_cpu_lowlevel_init();
>> +
>> + if (IS_ENABLED(CONFIG_DEBUG_LL))
>> + setup_uart();
>> +
>> + fdt = __dtb_z_stm32mp15x_myirtech_myd_start + get_runtime_offset();
>> +
>> + stm32mp1_barebox_entry(fdt);
>
> Same question: Do you use an old TF-A or why do you need a specific entry
> point instead of barebox-stm32mp-generic-bl33.img?
Rethinking this, such an image is the only way to chainload barebox over
the network. So you may want to keep it until barebox can boot FIP images..
Cheers,
Ahmad
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-09-11 16:11 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-30 10:47 [PATCH 1/3] memory: Add driver for FMC2 External Bus Interface on STM32MP SoCs Alexander Shiyan
2023-08-30 10:47 ` [PATCH 2/3] mtd: nand: Add driver for NAND controller " Alexander Shiyan
2023-08-30 10:47 ` [PATCH 3/3] ARM: boards: Add MyirTech MYD-YA15XC-T development board support Alexander Shiyan
2023-08-30 14:41 ` Ahmad Fatoum
2023-08-31 6:40 ` Alexander Shiyan
2023-09-04 7:17 ` Sascha Hauer
2023-08-31 9:41 ` Alexander Shiyan
2023-09-05 8:25 ` Ahmad Fatoum
2023-09-11 16:01 ` Ahmad Fatoum
2023-09-11 16:09 ` Ahmad Fatoum
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