[PATCH 1/4] ARM: boards: polyhex-debix: fix RGMII pin setup

[PATCH 1/4] ARM: boards: polyhex-debix: fix RGMII pin setup

[Marco Felsch]

On the Debix SBC the EQOS interface is used as primary interface, the
FEC pins are routed to the extension header. On the other hand the Debix
SoM/Baseboard combination both interfaces are used. So fix the RGMII pin
setup by adding the EQOS pin as well and keep the FEC.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/arm/boards/polyhex-debix/board.c | 3 ++-
 include/mach/imx/iomux-mx8mp.h        | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boards/polyhex-debix/board.c b/arch/arm/boards/polyhex-debix/board.c
index d668dd1816f8..46cb18c5889c 100644
--- a/arch/arm/boards/polyhex-debix/board.c
+++ b/arch/arm/boards/polyhex-debix/board.c
@@ -28,7 +28,8 @@ static int polyhex_debix_probe(struct device *dev)
 
 	/* Enable RGMII TX clk output */
 	val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
-	val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN;
+	val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN |
+	       MX8MP_IOMUXC_GPR1_ENET_QOS_RGMII_EN;
 	writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
 
 	return 0;
diff --git a/include/mach/imx/iomux-mx8mp.h b/include/mach/imx/iomux-mx8mp.h
index b410eaebc8ac..98e340d3dad1 100644
--- a/include/mach/imx/iomux-mx8mp.h
+++ b/include/mach/imx/iomux-mx8mp.h
@@ -1099,5 +1099,6 @@ static inline void imx8mp_setup_pad(iomux_v3_cfg_t pad)
 
 #define MX8MP_IOMUXC_GPR1			0x4
 #define MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN	BIT(22)
+#define MX8MP_IOMUXC_GPR1_ENET_QOS_RGMII_EN	BIT(21)
 
 #endif  /* __ASM_ARCH_IMX8MP_PINS_H__ */
-- 
2.39.2

[PATCH 2/4] ARM: boards: polyhex-debix: add SoM/Baseboard combination compatible

[Marco Felsch]

Upstream [1] did not accept the "polyhex,imx8mp-debix" since it is to
generic. We could add "polyhex,imx8mp-debix" it to our barebox
devicetree but since we need to differentiate between the SBC and SOM
anyway, add the upstream landed compatible.

[1] https://lore.kernel.org/all/20230809071026.3546605-3-m.felsch@pengutronix.de/

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/arm/boards/polyhex-debix/board.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boards/polyhex-debix/board.c b/arch/arm/boards/polyhex-debix/board.c
index 46cb18c5889c..f81666ce0c93 100644
--- a/arch/arm/boards/polyhex-debix/board.c
+++ b/arch/arm/boards/polyhex-debix/board.c
@@ -37,6 +37,7 @@ static int polyhex_debix_probe(struct device *dev)
 
 static const struct of_device_id polyhex_debix_of_match[] = {
 	{ .compatible = "polyhex,imx8mp-debix" },
+	{ .compatible = "polyhex,imx8mp-debix-som-a-bmb-08" },
 	{ /* Sentinel */ }
 };
 BAREBOX_DEEP_PROBE_ENABLE(polyhex_debix_of_match);
-- 
2.39.2

[PATCH 3/4] ARM: boards: polyhex-debix: add support to read MAC addresses

[Marco Felsch]

For the Debix SoM/Baseboard combination the MAC addresses are stored on
a baseboard EEPROM in ASCII format. This commit adds the support to read
the MAC addresses from the EEPROM and set it accordingly.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/arm/boards/polyhex-debix/board.c | 66 ++++++++++++++++++++++++++-
 1 file changed, 65 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boards/polyhex-debix/board.c b/arch/arm/boards/polyhex-debix/board.c
index f81666ce0c93..ea4fc26a0ceb 100644
--- a/arch/arm/boards/polyhex-debix/board.c
+++ b/arch/arm/boards/polyhex-debix/board.c
@@ -6,11 +6,67 @@
 #include <envfs.h>
 #include <init.h>
 #include <io.h>
+#include <linux/nvmem-consumer.h>
 #include <mach/imx/bbu.h>
 #include <mach/imx/iomux-mx8mp.h>
+#include <net.h>
+
+struct debix_polyhex_machine_data {
+	void (*ethernet_setup)(void);
+};
+
+#define ETH_ALEN_ASCII	12
+
+static int polyhex_debix_eth_register_ethaddr(struct device_node *np)
+{
+	u8 mac[ETH_ALEN];
+	u8 *data;
+	int ret;
+
+	data = nvmem_cell_get_and_read(np, "mac-address", ETH_ALEN_ASCII);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+
+	ret = hex2bin(mac, data, ETH_ALEN);
+	if (ret)
+		goto err;
+
+	of_eth_register_ethaddr(np, mac);
+err:
+	free(data);
+
+	return ret;
+}
+
+static void polyhex_debix_ethernet_init(void)
+{
+	static const char * const aliases[] = { "ethernet0", "ethernet1" };
+	struct device_node *np, *root;
+	unsigned int i;
+
+	root = of_get_root_node();
+
+	for (i = 0; i < ARRAY_SIZE(aliases); i++) {
+		const char *alias = aliases[i];
+		int ret;
+
+		np = of_find_node_by_alias(root, alias);
+		if (!np) {
+			pr_warn("Failed to find %s\n", alias);
+			continue;
+		}
+
+		ret = polyhex_debix_eth_register_ethaddr(np);
+		if (ret) {
+			pr_warn("Failed to register MAC for %s\n", alias);
+			continue;
+		}
+	}
+}
 
 static int polyhex_debix_probe(struct device *dev)
 {
+	const struct debix_polyhex_machine_data *machine_data;
 	int emmc_bbu_flag = 0;
 	int sd_bbu_flag = 0;
 	u32 val;
@@ -32,12 +88,20 @@ static int polyhex_debix_probe(struct device *dev)
 	       MX8MP_IOMUXC_GPR1_ENET_QOS_RGMII_EN;
 	writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1);
 
+	machine_data = device_get_match_data(dev);
+	if (machine_data && machine_data->ethernet_setup)
+		machine_data->ethernet_setup();
+
 	return 0;
 }
 
+static const struct debix_polyhex_machine_data debix_som_a_bmb_08 = {
+	.ethernet_setup = polyhex_debix_ethernet_init,
+};
+
 static const struct of_device_id polyhex_debix_of_match[] = {
 	{ .compatible = "polyhex,imx8mp-debix" },
-	{ .compatible = "polyhex,imx8mp-debix-som-a-bmb-08" },
+	{ .compatible = "polyhex,imx8mp-debix-som-a-bmb-08", .data = &debix_som_a_bmb_08 },
 	{ /* Sentinel */ }
 };
 BAREBOX_DEEP_PROBE_ENABLE(polyhex_debix_of_match);
-- 
2.39.2

[PATCH 4/4] ARM: dts: imx8mp-debix-som-a-bmb-08-upstream: sync with mainlined kernel version

[Marco Felsch]

Sync the *-upstream.dts(i) versions with the mainlined kernel version [1]
available with v6.6.

[1] https://lore.kernel.org/all/20230809071026.3546605-4-m.felsch@pengutronix.de/

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 .../imx8mp-debix-som-a-bmb-08-upstream.dts    | 126 ++++++++----------
 arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi |  36 +++--
 2 files changed, 85 insertions(+), 77 deletions(-)

diff --git a/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts b/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts
index 79c505d141c2..59334ce30c8a 100644
--- a/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts
+++ b/arch/arm/dts/imx8mp-debix-som-a-bmb-08-upstream.dts
@@ -11,20 +11,27 @@
 / {
 	model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
 	compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
-		     "polyhex,imx8mp-debix", "fsl,imx8mp";
+		     "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &fec;
+	};
 
 	chosen {
 		stdout-path = &uart2;
 	};
 
-	regulator-baseboard-vdd3v3 {
+	reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
 		compatible = "regulator-fixed";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-name = "BB_VDD3V3";
+		/* Required timings for ethernet phy's */
+		startup-delay-us = <50000>;
+		off-on-delay-us = <110000>;
 		gpio = <&expander0 10 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
-		regulator-always-on;
 	};
 
 	reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 {
@@ -56,17 +63,6 @@ regulator-som-vdd3v3 {
 		regulator-always-on;
 	};
 
-	reg_usdhc2_vmmc: regulator-usdhc2 {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
-		regulator-name = "VSD_3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
 	regulator-vbus-usb20 {
 		compatible = "regulator-fixed";
 		regulator-min-microvolt = <5000000>;
@@ -102,10 +98,11 @@ reg_vdd5v0: regulator-vdd5v0 {
 &eqos {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_eqos>;
-	phy-mode = "rgmii-id";
+	nvmem-cells = <&ethmac1>;
+	nvmem-cell-names = "mac-address";
+	phy-supply = <&reg_baseboard_vdd3v3>;
 	phy-handle = <&ethphy0>;
-	snps,reset-gpio = <&gpio4 18 GPIO_ACTIVE_LOW>;
-	snps,reset-delays-us = <10 20 200000>;
+	phy-mode = "rgmii-id";
 	status = "okay";
 
 	mdio {
@@ -113,16 +110,14 @@ mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy0: ethernet-phy@0 {
+		ethphy0: ethernet-phy@1 {
 			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-			qca,disable-smarteee;
-			vddio-supply = <&vddio_phy0>;
-
-			vddio_phy0: vddio-phy0-regulator {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-			};
+			reg = <1>;
+			reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <20000>;
+			reset-deassert-us = <150000>;
+			eee-broken-1000t;
+			realtek,clkout-disable;
 		};
 	};
 };
@@ -130,28 +125,26 @@ vddio_phy0: vddio-phy0-regulator {
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
-	phy-mode = "rgmii-id";
+	nvmem-cells = <&ethmac2>;
+	nvmem-cell-names = "mac-address";
+	phy-supply = <&reg_baseboard_vdd3v3>;
 	phy-handle = <&ethphy1>;
+	phy-mode = "rgmii-id";
 	fsl,magic-packet;
-	phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
-	phy-reset-duration = <10>;
-	phy-reset-post-delay = <150>;
 	status = "okay";
 
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy1: ethernet-phy@0 {
+		ethphy1: ethernet-phy@1 {
 			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-			qca,disable-smarteee;
-			vddio-supply = <&vddio_phy1>;
-
-			vddio_phy1: vddio-phy1-regulator {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-			};
+			reg = <1>;
+			reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <20000>;
+			reset-deassert-us = <150000>;
+			eee-broken-1000t;
+			realtek,clkout-disable;
 		};
 	};
 };
@@ -201,7 +194,7 @@ expander1: gpio@23 {
 		#gpio-cells = <0x02>;
 
 		/*
-		 * Since USB1 is binded to peripheral mode we need to ensure
+		 * Since USB1 is bound to peripheral mode we need to ensure
 		 * that VBUS is turned off.
 		 */
 		usb30-otg-hog {
@@ -212,12 +205,6 @@ usb30-otg-hog {
 		};
 	};
 
-	eeprom@52 {
-		compatible = "atmel,24c02";
-		reg = <0x52>;
-		pagesize = <16>;
-	};
-
 	rtc@51 {
 		compatible = "haoyu,hym8563";
 		reg = <0x51>;
@@ -227,6 +214,23 @@ rtc@51 {
 		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
 		#clock-cells = <0>;
 	};
+
+	eeprom@52 {
+		compatible = "atmel,24c02";
+		reg = <0x52>;
+		pagesize = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* MACs stored in ASCII */
+		ethmac1: mac-address@0 {
+			reg = <0x0 0xc>;
+		};
+
+		ethmac2: mac-address@c {
+			reg = <0xc 0xc>;
+		};
+	};
 };
 
 &snvs_pwrkey {
@@ -301,16 +305,16 @@ &usb3_phy1 {
 /* µSD Card */
 &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-	vmmc-supply = <&reg_usdhc2_vmmc>;
-	bus-width = <4>;
-
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 	assigned-clock-rates = <400000000>;
-
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	disable-wp;
+	no-sdio;
+	no-mmc;
 	status = "okay";
 };
 
@@ -409,12 +413,6 @@ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41
 		>;
 	};
 
-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41
-		>;
-	};
-
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x14f
@@ -468,13 +466,7 @@ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
 			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
 			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
 			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
-			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 	0xc1
-		>;
-	};
-
-	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
 		>;
 	};
 };
diff --git a/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi b/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi
index ae12f322bce2..9e0d19a2a72c 100644
--- a/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi
+++ b/arch/arm/dts/imx8mp-debix-som-a-upstream.dtsi
@@ -8,7 +8,18 @@
 
 / {
 	model = "Polyhex i.MX8MPlus Debix SOM A";
-	compatible = "polyhex,imx8mp-debix-som-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
+	compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp";
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 };
 
 &A53_0 {
@@ -38,9 +49,8 @@ pmic@25 {
 		reg = <0x25>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
-
 		interrupt-parent = <&gpio1>;
-		interrupts = <3 GPIO_ACTIVE_LOW>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 
 		regulators {
 			buck1: BUCK1 {
@@ -63,7 +73,7 @@ buck2: BUCK2 {
 				nxp,dvs-standby-voltage = <850000>;
 			};
 
-			buck4: BUCK4{
+			buck4: BUCK4 {
 				regulator-name = "BUCK4";
 				regulator-min-microvolt = <600000>;
 				regulator-max-microvolt = <3400000>;
@@ -71,7 +81,7 @@ buck4: BUCK4{
 				regulator-always-on;
 			};
 
-			buck5: BUCK5{
+			buck5: BUCK5 {
 				regulator-name = "BUCK5";
 				regulator-min-microvolt = <600000>;
 				regulator-max-microvolt = <3400000>;
@@ -139,7 +149,6 @@ &i2c4 {
 	adc@48 {
 		 compatible = "ti,ads1115";
 		 reg = <0x48>;
-
 		 #address-cells = <1>;
 		 #size-cells = <0>;
 
@@ -148,16 +157,19 @@ channel@4 {
 			 ti,gain = <1>;
 			 ti,datarate = <7>;
 		 };
+
 		 channel@5 {
 			 reg = <5>;
 			 ti,gain = <1>;
 			 ti,datarate = <7>;
 		 };
+
 		 channel@6 {
 			 reg = <6>;
 			 ti,gain = <1>;
 			 ti,datarate = <7>;
 		 };
+
 		 channel@7 {
 			 reg = <7>;
 			 ti,gain = <1>;
@@ -176,12 +188,10 @@ &usdhc3 {
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-	bus-width = <8>;
-	non-removable;
-
 	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
 	assigned-clock-rates = <400000000>;
-
+	bus-width = <8>;
+	non-removable;
 	status = "okay";
 };
 
@@ -213,6 +223,12 @@ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x41
 		>;
 	};
 
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41
+		>;
+	};
+
 	pinctrl_usdhc3: usdhc3grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
-- 
2.39.2

Re: [PATCH 1/4] ARM: boards: polyhex-debix: fix RGMII pin setup

[Sascha Hauer]

On Tue, Aug 29, 2023 at 02:43:53PM +0200, Marco Felsch wrote:
> On the Debix SBC the EQOS interface is used as primary interface, the
> FEC pins are routed to the extension header. On the other hand the Debix
> SoM/Baseboard combination both interfaces are used. So fix the RGMII pin
> setup by adding the EQOS pin as well and keep the FEC.
> 
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
>  arch/arm/boards/polyhex-debix/board.c | 3 ++-
>  include/mach/imx/iomux-mx8mp.h        | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)

Applied, thanks

Sascha

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