[PATCH] MIPS: qemu-malta: use 320 MHz input clock for CP0 clocksource

[Antony Pavlov <antonynpavlov@gmail.com>]

Modern qemu uses 24Kf CPU at 320 MHz for malta board.
By default arch/mips/lib/csrc-r4k.c clocksource driver
relies on CPU running at 200 MHz and CP0 timer runs
at the half of CPU clock that is 100 MHz.
As a result the `sleep 15` command runs for only
9 seconds on qemu-malta.

Setting CPU clock to 320 MHz in the qemu-malta.dts file
fixes the problem.

See these qemu commits for details:

  eea1f5bac6f hw/mips/malta: Set CPU frequency to 320 MHz
  a7519f2b39b mips: malta/boston: replace cpu_model with cpu_type

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
---
 arch/mips/Kconfig            |  3 +++
 arch/mips/dts/qemu-malta.dts | 20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e05ee2d7f1a..89fc16be133 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -79,6 +79,9 @@ config MACH_MIPS_MALTA
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_LITTLE_ENDIAN
 	select HAS_DEBUG_LL
+	select COMMON_CLK
+	select COMMON_CLK_OF_PROVIDER
+	select CLKDEV_LOOKUP
 	select GPIOLIB
 	select HW_HAS_PCI
 	select HAVE_PBL_IMAGE
diff --git a/arch/mips/dts/qemu-malta.dts b/arch/mips/dts/qemu-malta.dts
index f08832735f8..c2bc03dd463 100644
--- a/arch/mips/dts/qemu-malta.dts
+++ b/arch/mips/dts/qemu-malta.dts
@@ -19,6 +19,26 @@ memory@0 {
 		reg = <0x00000000 0x10000000>;
 	};
 
+	clocks {
+		ref_clk: ref_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <320000000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kf";
+			clocks = <&ref_clk>;
+			reg = <0>;
+		};
+	};
+
 	uart0: serial@180003f8 {
 		compatible = "ns16550a";
 		reg = <0x180003f8 0x08>;
-- 
2.39.0