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Fri, 10 Nov 2023 13:58:03 +0100 Received: from sha by dude02.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1r1R5G-008s1Y-31; Fri, 10 Nov 2023 13:58:02 +0100 From: Sascha Hauer To: Barebox List Date: Fri, 10 Nov 2023 13:57:52 +0100 Message-Id: <20231110125800.1901232-18-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231110125800.1901232-1-s.hauer@pengutronix.de> References: <20231110125800.1901232-1-s.hauer@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231110_125814_721878_C4BEE56B X-CRM114-Status: GOOD ( 13.83 ) X-BeenThere: barebox@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "barebox" X-SA-Exim-Connect-IP: 2607:7c80:54:3::133 X-SA-Exim-Mail-From: barebox-bounces+lore=pengutronix.de@lists.infradead.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on metis.whiteo.stw.pengutronix.de X-Spam-Level: X-Spam-Status: No, score=-4.9 required=4.0 tests=AWL,BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Subject: [PATCH 17/25] ARM: i.MX93: Add DDR size read support X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on metis.whiteo.stw.pengutronix.de) Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/esdctl.c | 42 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 2fca0a44a1..ac35a2de66 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -28,6 +28,7 @@ #include #include #include +#include struct imx_esdctl_data { unsigned long base0; @@ -555,6 +556,39 @@ static int imx8mn_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) return _imx8m_ddrc_add_mem(mmdcbase, data, 16); } +#define IMX9_DDRC_CS_CONFIG(n) (0x80 + (n) * 4) +#define IMX9_DDRC_CS_ROW_BITS GENMASK(10, 8) +#define IMX9_DDRC_CS_COL_BITS GENMASK(2, 0) +#define IMX9_DDRC_CS_EN BIT(31) + +static int imx9_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data) +{ + int width = 2; + int banks = 8; + unsigned long mem = 0; + int i; + + for (i = 0; i < 2; i++) { + int rows, cols; + u32 cs, col_bits; + + cs = readl(mmdcbase + IMX9_DDRC_CS_CONFIG(i)); + if (!(cs & IMX9_DDRC_CS_EN)) + continue; + + rows = FIELD_GET(IMX9_DDRC_CS_ROW_BITS, cs) + 12; + col_bits = FIELD_GET(IMX9_DDRC_CS_COL_BITS, cs); + if (col_bits == 7) + cols = 7; + else + cols = col_bits + 8; + + mem += memory_sdram_size(cols, rows, banks, width); + } + + return arm_add_mem_device("ram0", data->base0, mem); +} + static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc) { const u32 addrmap[DDRC_ADDRMAP_LENGTH] = { @@ -695,6 +729,11 @@ static __maybe_unused struct imx_esdctl_data imx8mn_data = { .add_mem = imx8mn_ddrc_add_mem, }; +static __maybe_unused struct imx_esdctl_data imx9_data = { + .base0 = MX9_DDR_CSD1_BASE_ADDR, + .add_mem = imx9_ddrc_add_mem, +}; + static __maybe_unused struct imx_esdctl_data imx7d_data = { .base0 = MX7_DDR_BASE_ADDR, .add_mem = imx7d_ddrc_add_mem, @@ -770,6 +809,9 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = { }, { .compatible = "fsl,imx8mn-ddrc", .data = &imx8mn_data + }, { + .compatible = "fsl,imx93-ddrc", + .data = &imx9_data }, { .compatible = "fsl,imx7d-ddrc", .data = &imx7d_data -- 2.39.2